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July 2012

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications

FXMA2104

Dual-Supply, 4-Bit Voltage Translator / Buffer / Repeater / Isolator for Open-Drain Applications

Features



Bi-Directional Interface between Any Two Levels:

1.65V to 5.5V



Direction Control not Needed



System GPIO Resources Not Required when OE Tied to VCCA



I²C 400pF Buffer / Repeater



I²C-Bus^® Isolation



A/B Port VOL = 175mV (Typical), VIL = 150mV, IOL = 6mA



Open-Drain Inputs / Outputs



Accommodates Standard-Mode and Fast-Mode I²C-Bus Devices



Supports I²C Clock Stretching & Multi-Master



Fully Configurable: Inputs and Outputs Track VCC



Non-Preferential Power-Up; Either VCC May Be Powered-Up First



Outputs Switch to 3-State if Either VCC is at GND



Tolerant Output Enable: 5V



Packaged in 12-Lead Ultrathin MLP (1.8mm x 1.8mm)



ESD Protection Exceeds:

- 5kV HBM ESD (per JESD22-A114) - 2kV CDM (per JESD22-C101)

Description

The FXMA2104 is a 4-bit high-performance, configurable dual-voltage supply, open-drain translator for bi-directional voltage translation over a wide range of input and output voltages levels.

Intended for use as a voltage translator in applications using the I²C-Bus^® interface, the input and output voltage levels are compatible with I²C device specification voltage levels. External pull-up resistors are required.

The device is designed so that the A port tracks the VCCA level and the B port tracks the VCCB level. This allows for bi-directional A/B port voltage translation between any two levels from 1.65V to 5.5V. VCCA can equal VCCB from 1.65V to 5.5V.

Non-preferential power-up means either VCC can be powered-up first. Internal power-down control circuits place the device in 3-state if either VCC is removed.

The two ports of the device have automatic direction- sense capability. Either port may sense an input signal and transfer it as an output signal to the other port.

Ordering Information

Part Number

Operating Temperature

Range

Top

Mark Package Packing

Method

5000 Units on

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications Block Diagram

VCCB

VCCA

A B

OE

Dynamic Driver (with Time Out)

Dynamic Driver (with Time Out)

VbiasA VbiasB

Internal Direction Generator &

Control

Internal Direction Generator &

Control

Figure 1. Block Diagram, 1 of 4 Channels

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications Pin Configuration

Figure 2. UMLP (Top-Through View)

Pin Definitions

Pin # Name Description

1 VCCB B-Side Power Supply

2 VCCA A-Side Power Supply

3, 4, 5, 6 A0, A1, A2, A3 A-Side Inputs or 3-State Outputs

7 GND Ground

8 OE Output Enable Input

9, 10, 11, 12 B3, B2, B1, B0, B-Side Inputs or 3-State Outputs

Truth Table

Control

Outputs OE

LOW Logic Level 3-State

HIGH Logic Level Normal Operation

Note:

1. If the OE pin is driven LOW, the FXMA2104 is disabled and the A0, A1, A2, A3, B0, B1, B2 and B3 pins (including dynamic drivers) are forced into 3-state.

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications Absolute Maximum Ratings

Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Units

VCCA, VCCB Supply Voltage -0.5 7.0

VIN DC Input Voltage V

A Port -0.5 7.0

B Port -0.5 7.0

Control Input (OE) -0.5 7.0

VO Output Voltage⁽²⁾

An Outputs 3-State -0.5 7.0 Bn Outputs 3-State -0.5 7.0 V An Outputs Active -0.5 VCCA + 0.5V Bn Outputs Active -0.5 VCCB + 0.5V

IIK DC Input Diode Current At VIN < 0V -50 mA

IOK DC Output Diode Current At VO < 0V -50

At VO > VCC +50 mA

IOH / IOL DC Output Source/Sink Current -50 +50 mA

ICC DC VCC or Ground Current per Supply Pin ±100 mA

PD Power Dissipation At 400KHz 0.129 mW

TSTG Storage Temperature Range -65 +150 °C

ESD Electrostatic Discharge Capability

Human Body Model, JESD22-A114 5

Charged Device Mode, JESD22-C101 2 kV Note:

2. IO absolute maximum rating must be observed.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Max. Units

VCCA, VCCB Power Supply Operating 1.65 5.50 V

VIN Input Voltage

A Port 0 5.5

V

B Port 0 5.5

Control Input (OE) 0 VCCA

Θ^JA Thermal Resistance 301.5 C°/W

TA Free Air Operating Temperature -40 +85 °C

Note:

3. All unused inputs and I/O pins must be held at VCCI or GND, VCCI is the VCC associated with the input side.

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications Functional Description

Power-Up/Power-Down Sequencing

FXM translators offer an advantage in that either VCC

may be powered up first. This benefit derives from the chip design. When either VCC is at 0V, outputs are in a high-impedance state. The control input (OE) is designed to track the VCCA supply. A pull-down resistor tying OE to GND should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up/power-down. The size of the pull- down resistor is based upon the current-sinking capability of the device driving the OE pin.

The recommended power-up sequence is:

1. Apply power to the first VCC. 2. Apply power to the second VCC.

3. Drive the OE input HIGH to enable the device.

The recommended power-down sequence is:

1. Drive OE input LOW to disable the device.

2. Remove power from either VCC. 3. Remove power from other VCC. Note:

4. Alternatively, the OE pin can be hardwired to VCCA

to save GPIO pins. If OE is hardwired to VCCA, either VCC can be powered up or down first.

Application Circuit

Figure 3. Application Circuit

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications Application Information

The FXMA2104 has open-drain I/Os and requires external pull-up resistors on the eight data I/O pins, as shown in Figure 3. If a pair of data I/O pins (An/Bn) is not used, both pins should be tied to GND (or both to VCC).

In this case, pull-down or pull-up resistors are not required. The recommended values for the pull-up resistors (RPUs) are 1KΩ to 10K, depending on the total bus capacitance, the user is free to vary the pull-up resistor value to meet the maximum I²C edge rate per the I²C specification (UM10204 rev. 03, June 19, 2007).

For example, the maximum edge rate (30% - 70%) during Fast Mode (400kbit/s) is 300ns. If bus capacitance is approaching the maximum 400pF, lower the RPU value to keep the rise time below 300ns (Fast Mode). Section 7.1 of the I²C specification provides an excellent guideline for pull-up resistor sizing.

Theory of Operation

The FXMA2104 is designed for high-performance level shifting and buffer / repeating in an I²C application.

Figure 1 shows that each bi-directional channel contains two series-Npassgates and two dynamic drivers. This hybrid architecture is highly beneficial in an I²C application where auto-direction is a necessity.

For example, during the following three I²C protocol events:

 Clock Stretching

 Slave’s ACK Bit (9^th bit = 0) following a Master’s Write Bit (8^th bit = 0)

 Clock Synchronization and Multi Master Arbitration

the bus direction needs to change from master-to-slave to slave-to-master without the occurrence of an edge. If there is an I²C translator between the master and slave in these examples, the I²C translator must change direction when both A and B ports are LOW. The Npassgates can accomplish this task very efficiently because, when both A and B ports are LOW, the Npassgates act as a low resistive short between the two (A and B) ports.

Due to I²C’s open-drain topology, I²C masters and slaves are not push-pull drivers. Logic LOWs are “pulled down” (Isink), while logic HIGHs are “let go” (3-state). For example, when the master lets go of SCL (SCL always comes from the master), the rise time of SCL is largely determined by the RC time constant, where R = RPU and C = the bus capacitance. If the FXMA2104 is attached to the master [on the A port] and there is a slave on the B port, the Npassgates act as a low resistive short

between the ports until either of the port’s VCC/2 thresholds are reached. After the RC time constant has reached the VCC/2 threshold of either port, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the LOW-to-HIGH (LH) direction, accelerating the rising edge. The resulting rise time resembles the scope shot in Figure 4. Effectively, two distinct slew rates appear in rise time. The first slew rate (slower) is the RC time constant of the bus. The second slew rate (much faster) is the dynamic driver accelerating the edge.

If both the A and B ports of the translator are HIGH, a high-impedance path exists between the A and B ports because both the Npassgates are turned off. If a master or slave device decides to pull SCL or SDA LOW, that device’s driver pulls down (Isink) SCL or SDA until the edge reaches the A or B port VCC/2 threshold. When either the A or B port threshold is reached, the port’s edge detector triggers both dynamic drivers to drive their respective ports in the HIGH-to-LOW (HL) direction, accelerating the falling edge.

Figure 4. Waveform C: 600pF, Total RPU: 2.2KΩ

FXMA2104 — Dual-S upply, 4-Bit Voltag e Translator / Buffer / Re peater / for Open-Drain Applications

Buffer / Repeater Performance

The FXMA2104 dynamic drivers have enough current- sourcing capability to drive a 400pF capacitive bus. This is beneficial when an I²C buffer / repeater is required.

The I²C specification stipulates a maximum bus capacitance of 400pF. If an I²C segment exceeds 400pF, an I²C buffer / repeater is required to split the segment into two segments, each of which is less than 400pF. Figure 4 is a scope shot of an FXMA2104 driving a lumped load of 600pF. Notice the (30% - 70%) rise time is only 112ns (total RPU = 2.2K). This is well below the maximum edge rate of 300ns. Not only does the FXMA2104 drive 400Pf; it also provides excellent headroom below the I²C specification maximum edge rate of 300ns.

V

_OL

vs. I

_OL

The I²C specification mandates a maximum VIL (IOL of 3mA) of VCC • 0.3 and a maximum VOL of 0.4V. If there is a master on the A port of an I²C translator with a VCC

of 1.65V and a slave on the I²C translator B port with a VCC of 3.3V, the maximum VIL of the master is (1.65V x 0.3) 495mV. The slave could legally transmit a valid logic LOW of 0.4V to the master.

If the I²C translator’s channel resistance is too high, the voltage drop across the translator could present a VIL to the master greater than 495mV. To complicate matters, the I²C specification states that 6mA of IOL is recommended for bus capacitances approaching 400pF. More IOL increases the voltage drop across the I²C translator. The I²C application benefits when I²C translators exhibit low VOL performance. Figure 5 depicts typical FXMA2104 VOL performance vs. a competitor, given a 0.4V VIL.

Figure 5. VOL vs. IOL

0.4 0.45 0.5 0.55 0.6 0.65

0 2 4 6 8 10

VOL(V):

I

_OL

(mA):

V

_OL

: FXMA2104 vs. Device B, V

_IL

= 0.4V

Device B VIL = 0.4V FXMA2104 VIL = 0.4V

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications

I

²

C Bus Isolation

The FXMA2104 supports I²C-Bus^® isolation for the following conditions:



Bus isolation if bus clear



Bus isolation if either VCC goes to ground Bus Clear

Because the I²C specification defines the minimum SCL frequency of DC, the SCL signal can be held LOW forever; however, this condition shuts down the I²C bus.

The I²C specification refers to this condition as Bus Clear. In Figure 6, if slave #2 holds down SCL forever, the master and slave #1 are not able to communicate because the FXMA2104 passes the SCL stuck-LOW

condition from slave #2 to slave #1 as well as the master. However, if the OE pin is pulled LOW (disabled), both ports (A and B) are 3-stated. This results in the FXMA2104 isolating slave #2 from the master and slave #1, allowing full communication between the master and slave #1.

Either VCC to GND

If slave #2 is a camera that is suddenly removed from the I²C bus, resulting in VCCB transitioning from a valid VCC (1.65V – 5.5V) to 0V; the FXMA2104 automatically forces all I/Os on both its A and B ports into 3-state.

Once VCCB has reached 0V, full I²C communication between the master and slave #1 remains undisturbed.

Figure 6. Bus Isolation

Master

FXMA 2104 I2C Buffer Translator

SCL1

SDA1

Slave #2 SCL1

SDA1 Slave #1

SCL1 SDA1

VCCB VCCA

OE

OE: High Enable Low Disable

VCCB: 1.65V – 5.5V VCC

Domain VCCA:

1.65V – 5.5V VCC

Domain

Slave #3 SCL2

SDA 2 SCL2

SDA2

GPIO3 SCL1 SDA1

VCC = 3.3V VCC = 1.8V

SCL2 SCL2

SDA 2 SDA2

VCC = 1.8V VCC = 3.3V

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications

DC Electrical Characteristics

TA = –40°C to +85°C.

Symbol Parameter Condition V

CCA

(V) V

CCB

(V) Min. Max. Unit

VIHA High Level Input

Voltage A

Data Inputs An 1.65–5.50 1.65–5.50 VCCA – 0.4 Control Input OE 1.65–5.50 1.65–5.50 0.7 x VCCA V

VIHB High Level Input

Voltage B Data Inputs Bn 1.65–5.50 1.65–5.50 VCCB – 0.4 V VILA Low Level Input

Voltage A

Data Inputs An 1.65–5.50 1.65–5.50 0.4 Control Input OE 1.65–5.50 1.65–5.50 0.3 x VCCA V

VILB Low Level Input

Voltage B Data Inputs Bn 1.65–5.50 1.65–5.50 0.4 V

VOL Low Level Output Voltage

VIL = 0.15V

1.65–5.50 1.65–5.50 0.4 V IOL = 6mA

IL Input Leakage Current

Control Input OE,

VIN = VCCA or GND 1.65–5.50 1.65–5.50 ±1 µA

IOFF Power-Off Leakage Current

An VIN or VO = 0V to

5.5V 0 5.50 ±2

µA Bn VIN or VO = 0V to

5.5V 5.50 0 ±2

IOZ 3-State Output Leakage⁽⁶⁾

An, Bn

VO = 0V to 5.5V,

OE = VIL 5.50 5.50 ±2

µA An VO = 0V to 5.5V,

OE = Don’t Care 5.50 0 ±2

Bn VO = 0V to 5.5V,

OE = Don’t Care 0 5.50 ±2

ICCA/B Quiescent Supply Current^(7,8)

VIN = VCCI or GND,

IO = 0 1.65–5.50 1.65–5.50 5 µA

ICCZ Quiescent Supply Current⁽⁷⁾

VIN = VCCI or GND, IO = 0,

OE = VIL

1.65–5.50 1.65–5.50 5 µA

ICCA Quiescent Supply Current⁽⁶⁾

VIN = 5.5V or GND, IO = 0,

OE = Don’t Care, Bn to An

0 1.65–5.50 -2

1.65–5.50 0 2 µA

ICCB Quiescent Supply Current⁽⁶⁾

VIN = 5.5V or GND, IO = 0,

OE = Don’t Care, An to Bn

1.65–5.50 0 -2

0 1.65–5.50 2 µA

Notes:

5. This table contains the output voltage for static conditions. Dynamic drive specifications are given in Dynamic Output Electrical Characteristics.

6. “Don’t Care” indicates any valid logic level.

7. VCCI is the VCC associated with the input side.

8. Reflects current per supply, VCCA or VCCB.

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications

Dynamic Output Electrical Characteristics Output Rise / Fall Time

Output load: CL = 50pF, RPU = 2.2kΩ, push / pull driver, and T^A = -40°C to +85°C.

Symbol Parameter

V

CCO (10)

Unit 4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V 1.65 to 1.95V

Typical

trise Output Rise Time; A Port, B Port⁽¹¹⁾ 3 4 5 7 ns

tfall Output Fall Time; A Port, B Port⁽¹²⁾ 11 8 6 4 ns

Notes:

9. Output rise and fall times guaranteed by design simulation and characterization; not production tested.

10. VCCO is the VCC associated with the output side.

11. See Figure 11.

12. See Figure 12.

Maximum Data Rate

⁽¹³⁾

Output load: CL = 50pF, RPU = 2.2kΩ, push-pull driver, and T^A = -40°C to +85°C.

V

CCA

Direction

V

CCB

Unit 4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V 1.65 to 1.95V

Minimum

4.5V to 5.5V A to B 26 20 16 9

B to A 26 20 16 9 MHz

3.0V to 3.6V A to B 26 20 16 9

B to A 26 20 16 9 MHz

2.3V to 2.7V A to B 26 20 16 9

B to A 26 20 16 9 MHz

1.65V to 1.95V A to B 26 20 16 9

B to A 26 20 16 9 MHz

Note:

13. F-toggle guaranteed by design simulation; not production tested.

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications AC Characteristics

⁽¹⁷⁾

Output Load: CL = 50pF, RPU = 2.2kΩ, and T^A = -40°C to +85°C.

Symbol Parameter

V

CCB

Units 4.5 to 5.5V 3.0 to 3.6V 2.3 to 2.7V 1.65 to 1.95V Typ. Max. Typ. Max. Typ. Max. Typ. Max.

VCCA = 4.5 to 5.5V tPLH

A to B 1 3 1 3 1 3 1 3

B to A 1 3 2 4 3 5 4 7 ns

tPHL

A to B 2 4 3 5 4 6 6 7

B to A 2 4 2 5 2 6 5 7 ns

tPZL OE to A 4 5 6 10 5 9 7 15

OE to B 3 5 4 7 5 8 10 15 ns

tPLZ

OE to A 65 100 65 105 65 105 65 105

OE to B 5 9 6 10 7 12 9 16 ns

tskew A Port, B Port⁽¹⁴⁾ 0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 ns VCCA = 3.0 to 3.6V

tPLH A to B 2.0 5.0 1.5 3.0 1.5 3.0 1.5 3.0

B to A 1.5 3.0 1.5 4.0 2.0 6.0 3.0 9.0 ns

tPHL

A to B 2 4 2 4 2 5 6 7

B to A 2 4 2 4 2 5 3 5 ns

tPZL

OE to A 4 8 5 9 6 11 7 15

OE to B 4 8 6 9 8 11 10 14 ns

tPLZ

OE to A 100 115 100 115 100 115 100 115

OE to B 5 10 4 8 5 10 9 15 ns

tskew A Port, B Port⁽¹⁴⁾ 0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 ns VCCA = 2.3 to 2.7V

tPLH

A to B 2.5 5.0 2.5 5.0 2.0 4.0 1.0 3.0

B to A 1.5 3.0 2.0 4.0 3.0 6.0 5.0 10.0 ns

tPHL

A to B 2 5 2 5 2 5 5 6

B to A 2 5 2 5 2 5 3 6 ns

tPZL

OE to A 5 10 5 10 6 12 9.0 18.0

OE to B 4.0 8.0 4.5 9.0 5.0 10.0 9.0 18.0 ns

tPLZ OE to A 100 115 100 115 100 115 100 115

OE to B 65 110 65 110 65 115 12 25 ns

tskew A Port, B Port⁽¹⁴⁾ 0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 ns VCCA = 1.65 to 1.95V

tPLH

A to B 4.0 7.0 40. 7.0 5.0 8.0 5.0 10.0

B to A 1.0 2.0 1.0 2.0 1.5 3.0 5.0 10.0 ns

tPHL A to B 5 8 3 7 3 7 8 9

B to A 4 8 3 7 3 7 3 7 ns

tPZL

OE to A 11 15 11 14 14 28 14 23

OE to B 6 14 6 14 6 14 9 19 ns

tPLZ

OE to A 75 115 75 115 75 115 75 115

OE to B 75 115 75 115 75 115 75 115 ns

tskew A Port, B Port⁽¹⁴⁾ 0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 ns

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications Capacitance

TA = +25°C.

Symbol Parameter Condition Typical Unit

CIN Input Capacitance Control Pin (OE) VCCA = VCCB = GND 2.2 pF CI/O Input / Output Capacitance, An, Bn VCCA = VCCB = 5.0V, OE = GND 13.0 pF Cpd Power Dissipation Capacitance VCCA = VCCB = 5.0V, VIN = 0V or VCC, f = 400KHz 13.5 pF

Figure 7. AC Test Circuit

Table 1. Propagation Delay Table

⁽¹⁷⁾

Test Input Signal Output Enable Control

tPLH, tPHL Data Pulses VCCA

tPZL (OE to An, Bn) 0V LOW to HIGH Switch

tPLZ (OE to An, Bn) 0V HIGH to LOW Switch

Table 2. AC Load Table

V

CCO

C

L

R

L

1.8 ± 0.15V 50pF 2.2kΩ

2.5 ± 0.2V 50pF 2.2kΩ

3.3 ± 0.3V 50pF 2.2kΩ

5.0 ± 0.5V 50pF 2.2kΩ

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications Timing Diagrams

Figure 8. Waveform for Inverting and Non-Inverting Functions⁽¹⁶⁾

Figure 9. 3-STATE Output Low Enable Time⁽¹⁶⁾

Symbol V

CC

Vmi VCCI / 2

Vmo VCCO / 2

VX 0.5 x VCCO

VY 0.1 x VCCO

Figure 10. 3-STATE Output High Enable Time⁽¹⁶⁾

Figure 11. Active Output Rise Time Figure 12. Active Output Fall Time

Figure 13. F-Toggle Rate Figure 14. Output Skew Time Notes:

16. Input tR = tF = 2.0ns, 10% to 90% at VIN = 1.65V to 1.95V;

Input tR = tF = 2.0ns, 10% to 90% at VIN = 2.3 to 2.7V;

VCCI

VCCO GND DATAIN

DATAOUT

t_pxx t_pxx

Vmi

V_mo ^DATAOUT

OUTPUT CONTROL

t_PZL Vmi

V_CCA

VOL GND

VY

DATAOUT OUTPUT CONTROL

tPLZ Vmi VCCA

V_OL

GND Vx

V_CCI V_CCI/ 2 V_CCI/ 2

GND DATAIN

t_period

F-toggle rate, f = 1 / t_period

VCCO V_mo

t_skew t_skew

V_mo

GND OUTPUTDATA

t_skew = (t_pHLmax– t_pHLmin)_or(t_pLHmax– t_pLHmin) V_CCO

Vmo Vmo

GND OUTPUTDATA

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications Physical Dimensions

Figure 15. 12-Lead Ultrathin MLP, 1.8mm x 1.8mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

A B

SEATING C PLANE

RECOMMENDED LAND PATTERN

NOTES:

A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD.

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.

D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY.

E. DRAWING FILENAME: MKT-UMLP12Arev4.

SCALE : 2X LEAD OPTION 1

SCALE : 2X LEAD OPTION 2

DETAIL A SCALE : 2X

PIN#1 IDENT

TOP VIEW

BOTTOM VIEW

0.10 C

0.08 C

0.10 C 2X 2X

SIDE VIEW

0.10 C 0.050.00

3 6

1

0.10 C A B 0.05 C 0.55 MAX.

12

1.80

1.80

0.40

0.250.15(12X) 0.35

0.45

2.10

0.40 2.10

0.563 (11X)

(12X)0.20

1

0.152

9

0.588

DETAIL A PIN#1 IDENT

(11X)

PACKAGE EDGE

0.10

0.10 0.450.35

0.10

FXMA2104 — Dual-S upply, 4-Bit Voltage Translator / Buffer / Re peater / for Open-Drain Applications

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