WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

WEEK 8.1 Registers and Counters

Additional schematic DFF symbols

 Active low set and reset signals.

 Active high set and reset signals.

D Q

R S D Q

R S

Characteristic tables and equations for DFFs

 We can describe the behavior of a flip-flop via a characteristic table. The

characteristic table shows what the next flip-flop output value will be given the current flip-flop input value after the clock makes its active edge transition.

 We can also write this as a characteristic equation:

Toggle flip-flops (TFF)

 Another type of flip-flop that has a different behavior when compared to a DFF.

 Symbol for a positive edge-triggered TFF:

T Q

T Q

 Symbol for a negative edge-triggered TFF:

Characteristic tables and equations for TFFs

 The characteristic table for the TFF:

 The characteristic equation for the TFF:

 So with a TFF, the output toggles (or flips) its value if the input is T=1, otherwise it remains the same.

Making a TFF from a DFF

D Q

T Q

CLOCK

T Q

 We can actually build a TFF using a DFF and a 2-input XOR gate.

JK flip-flops (JKFF)

J Q

K

 Another type of flip-flop that has different behavior compared to a DFF or to a TFF.

 Positive edge-triggered JKFF:

 Negative edge-triggered JKFF:

Characteristic tables and equations for JKFFs

 The characteristic table for the JKFF:

 We can derive the characteristic equation for the JKFF (I find it easy to explain via a K- Map):

JK

Q(t) 0

1

00 01 11 10

0

1

0

0

1

1 1

0

Making a JKFF from a DFF

 We can actually build a JKFF using a DFF and some other gates.

J Q

K

D Q

J

Q

CLOCK K

Timing analysis with flip-flops

 There are some important things to understand when we go to actually make and implement a circuit with flip-flops.

 In reality, it takes time for gates to change their output values according to the input values – i.e., there are propagation delays due to resistance, capacitance, etc.

 Changes in flip-flop outputs occur at the active clock edge.

 There are three timing parameters that are especially important:

 Setup Time (TSU).

 Hold Time (TH).

 Clock-To-Output Time (TCO).

Definitions for timing analysis of flip-flops

 Setup Time (TSU):

 The setup time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) PRIOR to the arrival of the active clock edge.

 Hold Time (TH):

 The hold time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) AFTER the arrival of the active clock edge.

 Clock-To-Output (TCO):

 The clock-to-output time of a flip-flop is the amount of time it takes for the output to become stable (at its new value) AFTER the arrival of the active clock edge.

Comments

 If these timing specifications are not met, then it is possible that the flip-flop will not behave as expected.

 That is, if we don’t observe setup and hold times at the data inputs, then our output might not change as expected.

 That is, if we don’t wait long enough (clock-to-output time) for the output to change, then we might use an incorrect value.

 If we violate any of these timing parameters, then we have a timing violation.

 These timing parameters (as we will see later) have an influence on how fast we can clock a circuit.

Illustration of timing parameters (for a DFF)

CLOCK

D

Q

TSU TH

D should not change in this interval TCO

Q not stable (trustworthy) until this interval ends

D Q

Registers

 A single FF stores one bit – A group of n FFs stores n-bits and is called an n-bit register.

 Illustration:

 When clear=0, all flip-flop outputs are forced to zero (active low reset).

 When clear=1, the rising edge of the clock (the active clock edge), results in the 4-bit input transferred to register output.

D Q R

D Q R

D Q R D Q

R

clock clear I3

I2 I1 I0

A3 A2 A1 A0

Parallel loads (1)

 We might want to prevent the transfer of data from input to output even though the active clock edge arrives – we want the register to HOLD ITS CURRENT VALUE.

 We can do this by feeding the register outputs back to the inputs and adding some additional logic to control the register operation.

Parallel loads (2)

D Q

R

D Q

R

D Q

R D Q

R

clock clear I3

I2 I1 I0

A3 A2 A1 A0

load

 When load=1, the data inputs reach the D-input of the flip-flop.

 When the active clock edge arrives, the data gets transferred, or loaded, to the register output.

 When load=0, the data output of each flip-flop is fed back to its D-input.

 When the active clock edge arrives, the data input gets transferred to the register output, but since the values are the same for all flip-flops, the register holds its current value.

Shift registers

 Might want a register that can shift data serially in a direction… This type of register is called a shift register.

 Illustration of a 4-bit shift register.

D Q

R

D Q

R

D Q

R

D Q

R

clock serial

in serial

out

clear

 As active clock edges arrive, the data present at the serial input gets transferred

towards the serial output – so, data gets shifted to the right one bit at a time as clock edges arrive.

Comment

 Whenever we would like to add an “operation” to our register, we are simply placing a MUX in from of each DFF in order to “direct” the correct information to the DFF inputs in order to obtain the correct operation.

Universal shift registers (1)

 Perhaps we want a more general circuit – e.g., we want to be able to clear the register, load the register, and perform both a shift right and a shift left operation.

Universal shift registers (2)

 4-bit register capable of multiple operations (use multiplexers instead of AND/OR gates at FF inputs):

D Q R

D Q R

D Q R D Q

R

I3 I2 I1 I0

A3 A2 A1 A0

00 01 10 11

00 01 10 11

00 01 10 11

00 01 10 11

data in (rshift)

Universal shift registers (3)

 Has an asynchronous clear signal…

 Has a clock signal…

 Has data inputs for parallel load…

 Has data inputs for both left and right shifts…

 Has two control inputs that determine behavior:

Counters

 A counter is a register whose outputs go through a prescribed sequence of states upon the arrival of the active edge of some triggering signal (e.g., like a clock).

 The prescribed sequence of states, or register outputs, can be anything.

 Counters can come in two varieties – asynchronous or synchronous.

Ripple counters

 Ripple counters consist of a series of flip-flops where the output Q of one flip-flop is used (somehow) as the clock for the next flip-flop.

 It is the lack of a common clock signal for each flip-flop that makes the counter asynchronous.

Binary ripple counter (1)

 A type of ripple counter that has n-bits, and can count in binary from 0 to 2ⁿ -1 and repeat.

 E.g., count sequence for 4-bits:

Binary ripple counter (2)

 We can make a binary ripple counter easily via observation…

 A₀ always flips…

 A₁ flips with A₀ goes 1 -> 0…

 A₂ flips with A₁ goes 1 -> 0…

 Etc…

 So, the i-th bit complements the (i+1)-th bit when it goes 1 -> 0.

 Binary ripple counter easily done with TFFs.

T Q

R

T Q R

T Q

R T Q

R

1

clear

A3 A2 A1 A0 count

Up and down binary ripple counters

 Up counters count in the sequence 0, 1, 2, … , 2ⁿ-1 and repeats.

 Down counters count in the sequence 2ⁿ-1, … , 2, 1, 0 and repeats.

 Should be able to take our previous example and construct a binary ripple down counter…

Ripple counter delays

 Recall: Flip-flops have clock-to-output times (it takes time for the output to change once the clock signal arrives on the flip-flop).

 Because of this, it can take a lot of time for the higher order bits of a ripple counter to change (remember that the i-th bit output is used as the clock for the (i+1)-th bit).

A0 A1 A2 A3 count

transition time due to clock-to-output times

 So, the FF outputs do not change at the same time due to the ripple effect in the clock inputs. We would like FF outputs to change simultaneously. This is why we prefer to design synchronous counters.

Synchronous counters

 Different from ripple counters in that (the same) clock pulses are applied to the clock inputs of all flip-flops simultaneously.

 Flip-flop outputs then change simultaneously.

Example: Synchronous Binary Up Counter

 Can design a 4-bit synchronous binary up counter with enable: If enable=0 circuit should not count; If enable=1 the circuit should count.

 Observation: A₀ is always toggling…, A₁ toggles if A₀ is 1…, A₂ toggles if A₀, A₁ are 1…, A₃ toggles if A₀, A₁, A₂ are 1…

 Observations motivate the use of TFF…

Example: Synchronous Binary Up Counter

 Synchronous 4-bit binary up counter with enable using TFF:

T Q R

T Q R

T Q R T Q

R

enable

A3 A2 A1 A0

Example: Synchronous Binary Down Counter

 Can design a 4-bit synchronous binary up counter with enable: If enable=0 circuit should not count; If enable=1 the circuit should count.

 Observation: A₀ is always toggling…, A₁ toggles if A₀ is 0… A₂ toggles if A₀, A₁ are 0…, A₃ toggles if A₀, A₁, A₂ are 0…

 Observations motivate the use of TFF…

Example: Synchronous Binary Down Counter

 Synchronous 4-bit binary down counter with enable using TFF:

T Q

R

T Q

R

T Q

R

T Q

R

down

A3 A2 A1 A0

next

Example: Synchronous Binary Up/Down Counter

 Can combine the up and down counter to get an up/down counter (re-use previously built circuits!)

 Trick is getting correct input to the FF in order to perform correct operation.

 Consider the following control inputs which determine circuit behaviour:

Example: Synchronous Binary Up/Down Counter

Example: Synchronous Binary Up/Down Counter With Parallel Load

 Often useful to have a counter that we can load with a “starting” count.

 This requires adding another control line (load) and data inputs:

Example: Synchronous Binary Up/Down Counter With Parallel Load

T Q R

T Q R

T Q R T Q

R

down

A3 A2 A1 A0 up

I3 I2 I1 I0 load

L D U

Comments

 All of the previous counters could have been built using DFF or JKFF.

 Designing counters that perform multiple operations involves:

 Making sure that the correct inputs get to the FF inputs in order to perform the specific function; and…

 The logic feeding the FF input will cause the FF output to change appropriately.

 If the control signals and operations have priority, we need to make sure that the control signal priority disables the operation due to other control lines (e.g., parallel load “turns off” up/down count signals.

Symbols

 We might have different symbols to represent counters:

 E.g.,

A0 A1 A2 A3 I0

I1 I2 I3

CLR UP

Modulo counters

 Sometimes we don’t want to count through the entire sequence of binary numbers.

 E.g., we might want to count 0, 1, ,2 , … , 10 and repeat. (This is effectively a modulo- 10 counter).

 We could design such a counter using synchronous circuit design principles, but we could also attempt something a bit trickier…

 We can use additional circuitry to detect our maximum count number and use a parallel load to restart the counting.

Modulo counter build from a binary counter building block

 E.g., design a counter that counts 0, 1, ,2 , … , 10 and repeats.

A0 A1 A2 A3 I0

I1 I2 I3

CLR UP LOAD CLK

1 1 0 0 0 0

Some Other Types of Counters: Ring counters

 An n-bit counter in which only one output is high at any given time.

 E.g., Can illustrate with a timing diagram for 4-bits:

A0 A1 A2 A3 CLK

 Outputs like this useful to generate timing signals that indicate an order of operation in another circuit block.

Some Other Types of Counters: Ring counters

 Can make an n-bit ring counter with a shift register.

 E.g., 4-bit ring counter:

D Q

R

D Q

R

D Q

R

D Q

R

A0 A1 A2 A3

clk clear

S

 To generate n non-overlapping timing signals, we need a shift register with n flip-flops.

Some Other Types of Counters: Ring counters

 Can also use a combination of a counter and a decoder.

 E.g., 4-bit ring counter with 2-bit counter and decoder.

A0 A1 CLR

COUNT CLK

1 1

2-bit counter

x y

2-to-4 decoder

D0 D1 D2 D3

A0 A1 A2 A3

Some Other Types of Counters: Switch-tail ring counters

 Consider the following 4-bit circuit:

D Q

R

D Q

R

D Q

R

D Q

R

A0 A1 A2 A3

clk clear

 Resembles a 4-bit ring counter, but complement of MSB fed back to LSB.

Some Other Types of Counters: Switch-tail ring counters

 Count pattern can be determined:

 So, with n bits we get a count pattern of 2ⁿ output states.

Some Other Types of Counters: Johnson counters

 We can add additional detection circuitry in order to generate the disjoint timing signals like a ring counter.

 This results in a Johnson Counter.

 With a Johnson Counter, we can get 2ⁿ non-overlapping timing signals using n flip-flops

Closing Remarks

 Synchronous counters are nice because the counter outputs all change at the same time (according to the clock).

 We have only talked about some types of counters; e.g.,

 Binary up/down counters; modulo counters.

 In general, counters are simply an example of a clocked sequential circuit.

 We can design any type of counter (e.g., any sequence of values we want) once we learn about clocked sequential circuit design (coming up in the course).

 E.g., we will see how to design a counter that counts 0, 3, 5, 4, 1, and repeats (if we wanted to).