AN EFFICIENT BIST ARCHITECTURE FOR LOW POWER
APPLICATIONS USING DUAL SLEEP APPROACH AND
TRI MODE LOGIC
Kondepati Madhuri and Shamini G. I.
Department of Electronics and Communication Engineering, Sathyabama University, Jeppiar Nagar, Rajiv Gandhi Salai, Chennai, India E-Mail: madhuri2594@gmail.com
ABSTRACT
BIST, Built In Self Test is a mechanism that is used to test itself the high reliability and low repair cyclic times .It is used to reduce complexity of the circuit it also reduces the cost and decreases the external test equipment. There are different powers gating techniques which are applied to the BIST architecture. In this paper an efficient BIST architecture is implemented using two different power gating schemes namely dual sleep approach and trimode logic. Dual sleep approach reduces the power consumption and dealy, in this technique main advantage is using extra pull up and pull down transistors while sleep state either ON or OFF. Trimode technique is reduces power, in this technique used virtual VDD and virtual VSS instead of normal VDD and VSS. From sleep to active at that time power consumption is more, by adding intermediate mode leakage power reduced. The simulation results show the comparison of these two techniques and give a better low power BIST architecture.
Index Terms:BIST, trimode logic, dual sleep approach, sleep mode, active mode, fault coverage, power mode logic, control signals.
1. INTRODUCTION
BIST design for test for test, BIST is dealing with test problems at an inside chip level is to incorporate BIST capability inside the chip. BIST is testing purpose and it is easy fault detection. The basic diagram for BIST is as shown in Figure-1, it consists of mainly 3 parts, they are test pattern generator, circuit under test, output response analyzer. BIST increases the controllability observability of the testing. Test pattern generator is used to generate the test patterns; these test patterns are generated with the help of automatic test equipment to determine the actual responses matched to the expected once. And these test patterns are applied to the circuit under test, the resulting output patterns are transferred to the output response analyzer, then it will check the expected output with the reference output. If both are matched means no defect is present in that circuit. In this way BIST can be easily implemented and gives high fault coverage.
Figure-1. Basic BIST architecture.
1.1 Features BIST
Reduces the storage and maintenance of test patterns. BIST is High fault coverage and easy fault detection. It can test the functional system speed.
2. EXISTING METHODOLOGY
The existing BIST architecture composed of two cascade normal D Flip flop as shown in Figure-3. In such
flip flops data input D is propagate to output Q on the falling edge of Clock signal. In [1] the clock inputs to the BIST architecture are control signals driven from the power mode logic.
Power mode control logic generates the control signal to BIST architecture according to the inputs SLEEPBAR and PWRONBAR in [1]. Power mode logic contains three states they are ACT mode, DS mode and PO mode as shown in Figure-2 The DF1 to DF6 are the resistive open defects, these power mode applied to BIST architecture in which identify power mode logic error free or not. Power mode logic states are:
ACT MODE: In act mode both SLEEPBAR and
PWRONBAR must be set to be logic 1 and logic 0.
DS MODE: SLEEPBAR must be set to logic 0
regardless PWRONBAR.
PO MODE: SLEEPBAR and PWRONBAR must be
set to logic one.
2.1 Power mode BIST architecture
Figure-3. BIST architecture.
All the control signal driven from the power mode logic are at 0v at that end of wake up phase.
All the control signals reach 0v in expected order.
First flip flop is connected to VDD (that means logic 1), test results output is observed at the out port out in instant of wake up phase is expected to finished out set logic 1, it means error free logic. Out port set to logic 0 falling transition of signals not occur in expected order. In this case failure is detected.
3. PROPOSED METHODLOGY
3.1 DUAL SLEEP APPROACH
In dual sleep approach uses a two extra pull up transistors and pull down transistors in sleep mood either in ON state or OFF state, in [2] sleep transistors are main used to reduce leakage power. Two sleep transistors contain both NMOS and PMOS is as shown in fig, any one transistor used to turn on ON state and other transistor used to turn on the OFF state .In OFF state contains both NMOS and PMOS transistors to reduce the leakage power.
Figure-5. Dual sleep BIST architecture.
Power mode control logic generates the control signal to BIST architecture according to the inputs SLEEPBAR and PWRONBAR. If the output logic is one power mode logic is error free.
3.2 TRIMODE LOGIC
Trimode logic can be explained in header and footer cell. In this trimode logic mainly used the virtual VDD (VVDD) and virtual VSS (VVSS) in [3]. Instead of using normal VDD use replace with virtual VDD by using this power consumption during the power transmission is less. Replace normal ground with virtual ground, so that leakage power will be reduced in sleep mode, is shown in Figure-6.
Figure-6. Trimode D flip flop.
Figure-7. Trimode BIST architecture.
4. SIMULATION RESULTS
Figure-8. Simulation results to power mode logic.
Figure-8 represents the power mode control signals in which input signals are sleepbar and prownbar, easily generate the control signals to the BIST architecture.
Figure-9, output of BIST architecture that is output node, out node logic 1 hence the power mode logic is error free defects.
Figure-9. Simulation results to existing BIST architecture.
When sleep=1 the NMOS transistor is on and when sleep= 0 the PMOS transistor is on state. In off state sleep=1 forced to “0” so the PMOS transistor becomes on and NMOS transistor becomes off. Dual sleep D flip flop simulation is as shown in below Figure-10.
Figure-10. Simulations results to dual sleep D flip flop.
Figure-11. Simulation results to dual sleep BIST architecture.
When s=0, D flip flop works in normal condition always maintain the drowsy node always set to logic one. Simulation results are as shown in Figure-12.
Figure-12. Trimode D flip flop.
Figure-13, output of BIST architecture that is output node, out node logic 1 hence the power mode logic is error free defects. If output node indicates zero, hence is defects present in the power mode logic. First four signals shows the input to the power mode signals, power mode control signals are given to clock signals to BIST
Figure-13. Simulation results to trimode BIST architecture.
Table-1. Performance to different BIST architecture.
Technique
POWER Power
Mode Logic
D Flip
Flop BIST
EXISITING 70mw 62mw 44mw
Dual sleep 70mw 11mw 40mw
Trimode 70mw 3.2mw 39mw
5. CONCLUSIONS
In this paper, different power reduction techniques to reduce the leakage power in BIST architecture. The power mode logic power value is 70mw and power mode BIST architecture power value is 44mw in 130 Nano meter technology. Furthermore to reduce the power in BIST architecture up to 10%, 15% for dual sleep BIST architecture and trimode BIST architecture respectively. These techniques are compared with previously done BIST architecture. The performance comparison of different BIST architecture are shown in Table-1, from this table we can say that modified trimode BIST architecture is an efficient method to reduce the leakage power.
annual Design Automation Conference. USA - June 02-06.
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