Memory and Programmable Logic

Memory and Programmable Logic

EE 200

Presentation Outline

❖ Random Access Memory (RAM)

❖ Read-Only Memory (ROM)

❖ Programmable Logic Device (PLD)

❖ Programmable Logic Array (PLA)

❖ Programmable Array Logic (PAL)

Memory Units

❖ A memory unit is a device that can store binary information ❖ It is a large group of cells, each capable of storing one bit ❖ Two types of memory units: Volatile and Non-Volatile

❖ Random-Access Memory (RAM) is volatile

❖ ROM, PROM, EEPROM, Flash, and FPGA are non-volatile

Memory Unit Volatile Non-Volatile Needs power Does not need power supply to retain bits

Random-Access Memory

❖ Large array of storage cells, capable of storing many 0's and 1's ❖ Random Access: bits can be accessed randomly

❖ Memory is addressable

Memory address consists of k bits Can address 2k _{words in memory}

Each word consists of n bits ❖ Memory capacity = 2k × n bits

❖ Two control functions: Read and Write Read: Data_out  Memory [Address]

Write: Memory [Address]  Data_in

Memory Unit 2k × n bits n Data_in n Data_out k Address Read Write

Memory Capacity

❖ Each memory location is a group of n bits, which is read/written

Byte = group of 8 bits 16-bit word = 2 bytes 32-bit word = 4 bytes

❖ The memory capacity is specified in bytes

1 KB (Kilo Byte) = 210 _{= 1024 bytes (more than thousand = 10}3₎

1 MB (Mega Byte) = 220 _{Bytes (more than million = 10}6₎

Memory Address and Content

❖ Example of a RAM Address = 10 bits 210 _addresses

From 0 to 1023

Each word = 16 bits ❖ Memory capacity =

210 × 16 bits =

16 Kbits = 2 KBytes ❖ Each word can be

addressed randomly ❖ Memory can be read

and written

Control Inputs to a Memory Chip

❖ Real memory chips have a Memory Enable, called chip select Enables a particular memory chip in a multichip large memory ❖ When memory enable is inactive, no operation is performed

❖ When memory enable is active, then memory is read and written ❖ The Read/Write input determines the operation to be performed ❖ The memory read/write operation is controlled by a CPU

Memory Read Cycle

❖ CPU sends address, read signal, and enables memory

❖ Memory outputs data at given address and transfers it to CPU

❖ Access time: time required to read a word from memory

Memory Write Cycle

❖ CPU sends address, data, write signal, and enables memory ❖ Memory stores data at the given address

❖ Cycle time: time required to write a word in memory

Example of a Small 4×4 RAM

❖ Four words only ❖ Each word = 4 bits ❖ BC = Binary Cell ❖ Total = 16 BCs ❖ Address = 2 bits ❖ 2×4 Decoder to select one word ❖ Decoder has a

memory enable

❖ If disabled, no word is selected

The Binary Cell

❖ The Binary Cell (BC) is the building block of memory ❖ The select input enables the cell for reading and writing ❖ The read/write input determines the operation of the cell ❖ The binary cell must be very small

❖ Memory must pack as many cells as possible in a small area ❖ The binary cell can be implemented similar to a latch

RAM Types

❖ Static RAM (SRAM) with 6-Transistor Cell

 Two cross-coupled inverters store bit (latch)  Two pass transistors to access bit

 Row decoder selects the word line

 𝐵𝑖𝑡 (and 𝐵𝑖𝑡) lines for reading/writing cell  Provides fast access time

❖ Dynamic RAM (DRAM)

 One pass transistor and one Capacitor  Bit is stored as a charge on Capacitor

 Cheap, very dense, but slower than SRAM  Typical choice for main memory

 Must be refreshed periodically (leakage of charge from capacitor)

Typical DRAM cell

Word line bit Capacitor Pass Transistor Word line bit bit

Memory Address Decoding

❖ A decoder with k address inputs has 2k _outputs

❖ It requires 2k _{AND gates, each having k inputs}

❖ The cost of the decoder becomes very large for large memories ❖ To reduce the cost of the address decoder …

A two-dimensional memory array is used

The memory address is split into row and column addresses Two decoders are used, each having k/2 inputs (address lines) 1. First one decodes the row address to select a row

Two-Dimensional Memory Structure

❖ 16-bit address: 8-bit row address + 8-bit column address ❖ Two 8×256 small decoders versus 16×65536 large decoder

❖ Address multiplexing

❖ First, 8-bit row address is registered and decoded

❖ Row Address Strobe

𝑅𝐴𝑆 signal

❖ 8-bit column address is registered and decoded

❖ Column Address Strobe

Read-Only Memory (ROM)

❖ Address consists of k bits ➔ 2k _{memory addresses}

❖ At each memory address, there is a word consisting of n bits ❖ The n-bit word appears at the data output of the ROM

❖ ROM does not have data inputs or a write operation

ROM

2k × n bits Data_out

k

ROM Internal Structure (32 x 8-bit)

❖ 5-bit Input ➔ 5-to-32 binary decoder (Only one line is selected) ❖ Each line = 8 bits ➔ 8-bit Data output

0 1 2 3 . . . 28 29 30 31 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 5 -to -32 dec oder Array Logic OR 32×8 = 256 connections Bits are stored at the intersection The 32×8 = 256 intersections are programmable

Implementing a Combinational Circuit

❖ Implementing a Combinational Circuit with a ROM is easy ❖ Store the truth table of the circuit by programming the ROM

I4 I3 I2 I1 I0 F7 F6 F5 F4 F3 F2 F1 F0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 1 0 0 1 0 · · · · · ·

Programming a ROM

Every 1 in the truth table ➔ X (CLOSED) connection Every 0 in the truth table ➔ NO connection

Example: At address 00011 = (decimal 3), the word 10110010 is stored

0 1 2 3 . . . 28 29 30 31 I4 I3 I2 I1 I0 1 0 1 1 0 0 1 0 5 -to -32 dec od er x x x x x x x x x x x x x x x x xx x x x x x x x x x 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 101 10 010 Array Logic OR 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 1 1

Example: Square Function

❖ Design a square function with a minimum size ROM ❖ Input X = 3-bit number, Output Y = X2

❖ Solution: Derive the Truth Table

X₂ X₁ X₀ Square Y₅ Y₄ Y₃ Y₂ Y₁ Y₀ 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 4 0 0 0 1 0 0 0 1 1 9 0 0 1 0 0 1 1 0 0 16 0 1 0 0 0 0

ROM Table

❖ Output Y₀ is identical to input X₀ ➔ No need to store in ROM

❖ Similarly, Output Y₁ is always 0 ➔ No need to store in ROM

❖ ROM table ➔ Only need to store Y₅, Y₄, Y₃, and Y₂ in ROM

X₂ X₁ X₀ Y₅ Y₄ Y₃ Y₂ Y₁ Y₀ 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 1 1 0 0 0 1 8 × 4 ROM X₂ X₁ X₀ Y₅ Y₄ Y₃ Y₂ Y₁ Y₀ 0 Minimal ROM Size = 23 × 4 bits

Types of ROMs

❖ ROM may be programmed in four different ways

1. Mask Programming: done by circuit manufacturer (not by user)

2. Programmable Read-Only Memory (PROM)

 Fuses in the PROM are blown using a high-voltage pulse  Can be programmed only once (irreversible)

3. Erasable PROM (EPROM)

Programming can be erased using ultraviolet light

Programmable Logic Devices (PLDs)

❖ Three major types of Programmable Logic Devices (PLDs) ❖ They differ in the placement of programmable connections

1. Programmable Read-Only Memory (PROM)

Fixed AND array (decoder) and programmable OR array

2. Programmable Array Logic (PAL)

Programmable AND array and fixed OR array

3. Programmable Logic Array (PLA) is the most flexible Programmable AND array and Programmable OR array

Programmable Logic Array (PLA)

❖ Similar to PROM, but no decoder ❖ Does NOT generate all minterms

❖ Decoder is replaced by an array of AND gates

❖ Programmable AND array can generate any product term ❖ Product terms are passed to a programmable OR array ❖ Programmable OR array produce sum-of-product outputs ❖ Programmable XOR gates are used to invert the output

PLA: 3 inputs, 4 product terms, 2 outputs

Array Logic AND

PLA Programming Table: Three Sections

❖ First section lists the product terms numerically

❖ Second section specifies paths from inputs to AND gates

 For each product term, the inputs are marked with 1, 0, or – (blown fuse)

❖ Third section specifies paths from AND to OR gates

 Marked with 1 (AND-OR connection) or – (blown fuse)

PLA Size Parameters

❖ Specified by number of inputs, product terms, and outputs ❖ For example: 16 inputs, 48 product terms, and 8 outputs ❖ For n inputs, k product terms, and m outputs, there are:

n buffer-inverters, k AND, m OR, and m XOR gates

❖ There are 2n × k connections from inputs to the AND array

❖ There are k × m connections from AND array to OR array

❖ There are m connections from OR to XOR array

Designing with a PLA

❖ Reduce number of product terms

 Since PLA has a limited number of AND gates

❖ Simplify each Boolean function to minimum number of terms

 Number of literals per term is not important  All inputs and their complements are available

❖ Both F and F' should be simplified to reduce number of terms ❖ Check for common product terms in different functions

❖ Extract the common product terms to reduce AND gates ❖ Fill the PLA programming table

Example of Designing with PLA

❖ Implement the following two Boolean functions with a PLA

F₁ (A, B, C) = ∑(0, 1, 2, 4) F₂ (A, B, C) = ∑(0, 5, 6, 7) ❖ Using K-maps 𝐹₁ = 𝐵′𝐶′ + 𝐴′𝐵′ + 𝐴′𝐶′ 𝐹₁ = (𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶)′ 𝐹₂ = 𝐴𝐵 + 𝐴𝐶 + 𝐴′𝐵′𝐶′ 𝐹₂ = (𝐴′𝐵 + 𝐴′𝐶 + 𝐴𝐵′𝐶′)′

Programmable Array Logic (PAL)

❖ Programmable AND array ❖ Fixed OR array

❖ Implements SOP expressions ❖ Not as flexible as PLA

❖ But easier to program

❖ Some outputs can be fed back

 To inputs of AND gates

❖ Typical PAL can have

 Eight inputs  Eight outputs

Designing with a PAL

❖ Boolean functions must be simplified to fit into separate sections ❖ Product terms cannot be shared in PALs with fixed OR array

❖ Each function must be simplified by itself

❖ Number of product terms in each section is fixed

❖ If number of terms is large, use two sections to implement function ❖ Example: 𝑤 𝐴, 𝐵, 𝐶, 𝐷 = σ(2, 12, 13) 𝑥 𝐴, 𝐵, 𝐶, 𝐷 = σ(7, 8, 9, 10, 11, 12, 13, 14, 15) 𝑤 = 𝐴𝐵𝐶′ + 𝐴′𝐵′𝐶𝐷′ 𝑥 = 𝐴 + 𝐵𝐶𝐷 𝑦 = 𝐴′𝐵 + 𝐶𝐷 + 𝐵′𝐷′

PAL Programming Table and Diagram

❖ Only AND inputs are programmed

 Inputs marked with 1, 0, or –

❖ Some AND are unused

 Their output is always zero (𝐴𝐴′ = 0)

❖ The w output is fed back