Two-level logic using NAND gates

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Sources: TSR, Katz, Boriello & Vahid

CSE140: Components and Design Techniques for Digital Systems

Two and Multilevel logic implementation

Tajana Simunic Rosing

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Two-level logic using NAND gates

• Replace minterm AND gates with NAND gates

• Place compensating inversion at inputs of OR gate

• OR gate with inverted inputs is a NAND gate

– de Morgan’s: A’ + B’ = (A • B)’

• Two-level NAND-NAND network

– inverted inputs are not counted

– in a typical circuit, inversion is done once and signal distributed

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Two-level logic using NAND and NOR gates

• NAND-NAND and NOR-NOR networks

– de Morgan’s law: (A + B)’ = A’ • B’ (A • B)’ = A’ + B’

– written differently: A + B = (A’ • B’)’ (A • B) = (A’ + B’)’

A B C D

Z

Conversion between forms

• Introduce "bubbles“ - inversions

– conservation of inversions – do not alter logic function

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Conversion between forms

• Example: map AND/OR network to NOR/NOR network

A B C D

Z

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Multiple-Output Circuits

• Many circuits have more than one output

• Can give each a separate circuit, or can share gates

• Ex: F = ab + c’, G = ab + bc

Option 1: Separate circuits Option 2: Shared gates

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Multiple-Output Example:

BCD to 7-Segment Converter

a = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z + w’xyz’ + w’xyz + wx’y’z’ + wx’y’z

abcdefg = 1111110 0110000 1101101 a

f b

d g e c

(b) (a)

b = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz + w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z

Multi-level logic

• x = A D F + A E F + B D F + B E F + C D F + C E F + G – reduced sum-of-products form – already simplified

– 6 x 3-input AND gates + 1 x 7-input OR gate – 25 wires (19 literals plus 6 internal wires)

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Non-Ideal Gate Behavior – Delay

• Real gates don’t respond immediately to input changes

– Rise/fall time – Delay – Pulse width

a F

Time F

a

10

F is not always 0 pulse 3 gate-delays wide D remains high for

three gate delays after A changes from low to high

A B C D F

Momentary changes in outputs

• Can be useful — pulse shaping circuits

• Can be a problem — incorrect circuit operation (glitches/hazards)

• Example: pulse shaping circuit

– A’ • A = 0 – delays matter

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Hazards

• Glitch – unwanted pulse on the output

• Circuit with a potential for a glitch has a hazard

• Three types:

– Static-0 : output should be 0 but has a 1 glitch – Static-1 : output should be 1 but has a 0 glitch – Dynamic: transition 0->1 or 1->0 with a glitch

Eliminating Hazards Example

• F(A,B,C,D)=Σm(1,3,5,7,8,9,12,13)

• Test two single bit input transitions:

– 1100 -> 1101 – 1100 -> 0101

A C’

D

Z

D

0 0

1 1

A

1 1

0 0

B C

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CSE140: Components and Design Techniques for Digital Systems

Regular logic implementation

Tajana Simunic Rosing

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&

2x2 AOI gate + symbol

&

3x2 AOI gate + symbol

NAND NAND Invert

possible implementation AB

CD

Z

AND OR Invert

logical concept AB

CD

Z

AND-OR-invert gates

• AOI function: three stages of logic — AND, OR, Invert

– multiple gates "packaged" as a single circuit block

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Conversion to AOI forms

• General procedure to place in AOI form

– compute the complement of the function in sum-of-products form – by grouping the 0s in the Karnaugh map

• Example: XOR implementation

– A xor B = A’ B + A B’

• • • inputs

AND array

• • • outputs

OR array product

terms

Programmable logic arrays

• Pre-fabricated building block of many AND/OR gates

– "personalized" by making/breaking connections among the gates – programmable array block diagram for sum of products form

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Enabling concept

• Shared product terms among outputs

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A B C

F1 F2 F3

F0 AB B'C AC' B'C' A

Before & after programming

• Two different technologies:

– fuse (normally connected, break unwanted ones)

– anti-fuse (normally disconnected, make wanted connections)

Before After

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A B C F1 F2 F3 F4 F5 F6 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1

A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC A B C

F1 F2 F3 F4 F5 F6

full decoder as for memory address bits stored in memory

Programmable logic array example

• Multiple functions of A, B, C

– F1 = A B C – F2 = A + B + C – F3 = A' B' C' – F4 = A' + B' + C' – F5 = A xor B xor C – F6 = A xnor B xnor C

a given column of the OR array has access to only a subset of

the possible product terms

PALs and PLAs

• Programmable logic array (PLA)

– what we've seen so far

– unconstrained fully-general AND and OR arrays

• Programmable array logic (PAL)

– constrained topology of the OR array – innovation by Monolithic Memories – faster and smaller OR plane

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Example

• Map the following functions to the PLA below:

– W = AB + A’C’ + BC’

– X = ABC + AB’ + A’B – Y = ABC’ + BC + B’C’

A B C

W X Y

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decoder

0 n-1

Address 2 -1n

0

1 1 1 1

word[i] = 0011 word[j] = 1010

bit lines (normally 1; set to 0 by a switch) j

i

internal organization

word lines

Read-only memories

• Two dimensional array of 1s and 0s

– entry (row) is called a "word"

– width of row = word-size – index is called an "address"

– address is input – selected word is output

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ROM structure

• Similar to a PLA structure but with a fully decoded AND array

– completely flexible OR array (unlike PAL)

n address lines

• • • inputs

decoder 2ⁿword lines

• • • outputs memory array (2ⁿwords by m bits)

m data lines

Regular logic structures for two-level logic

• ROM – full AND plane, general OR plane

– cheap (high-volume component) – can implement any function of n inputs – medium speed

• PAL – programmable AND plane, fixed OR plane

– intermediate cost

– can implement functions limited by number of terms

– high speed (only one programmable plane that is much smaller than ROM's decoder)

• PLA – programmable AND and OR planes

– most expensive (most complex in design, need more sophisticated tools) – can implement any function up to a product term limit

– slow (two programmable planes)

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CSE140: Components and Design Techniques for Digital Systems

Muxes and demuxes

Tajana Simunic Rosing

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Multiplexor (Mux)

• Mux routes one of its N data inputs to its one output, based on binary value of select inputs

• 4 input muxÆ needs 2 select inputs to indicate which input to route through

• 8 input muxÆ 3 select inputs

• N inputs Æ log₂(N) selects

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Mux Internal Design

2×1

i1 i0

s0 1

d 2×1

i1 i0

s0 0

d 2×1

i1 i0

s0 d

2x1 mux

Muxes Commonly Together -- N-bit Mux

• Ex: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1 b0)

– 4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B

i0 i1s0

2⋅ 1 d

i0 i1s0

2⋅ 1 d

i0 i1s0

2⋅ 1 d

i0 i1s0

2⋅ 1 d a3

b3

I0

s0

s0 I1

4-bit 2x1

D C

A

B a2

b2

a1 b1

a0 b0 s0

4

C 4 4

4

c3 c2 c1 c0 is short for Simplifying

notation:

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2 -1

I0I1 I2I3 I4 I5I6 I7

A B C mux8:1 Z I0I1

I2I3

A B mux4:1 Z I0

I1

A mux2:1 Z

k=0 n

Multiplexers/selectors (cont'd)

• 2:1 mux: Z = A'I

₀

+ AI

₁

• 4:1 mux: Z = A'B'I

₀

+ A'BI

₁

+ AB'I

₂

+ ABI

₃

• 8:1 mux: Z = A'B'C'I

₀

+ A'B'CI

₁

+ A'BC'I

₂

+ A'BCI

₃

+ AB'C'I

₄

+ AB'CI

₅

+ ABC'I

₆

+ ABCI

₇

• In general: Z = Σ (m

_k

I

_k

)

– in minterm shorthand form for a 2ⁿ:1 Mux

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N-bit Mux Example

• Four possible display items

– Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide

– Choose which to display using two inputs x and y – Use 8-bit 4x1 mux

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Multiplexers as general-purpose logic

• A 2^n-1:1 multiplexer can implement any function of n variables – with n-1 variables used as control inputs and

– the data inputs tied to the last variable or its complement

• Example: F(A,B,C) = m0 + m2 + m6 + m7

1:2 Decoder:

O0 = G • S’

O1 = G • S

2:4 Decoder:

O0 = G • S1’ • S0’

O1 = G • S1’ • S0 O2 = G • S1 • S0’

O3 = G • S1 • S0

3:8 Decoder:

O0 = G • S2’ • S1’ • S0’

O1 = G • S2’ • S1’ • S0 O2 = G • S2’ • S1 • S0’

O3 = G • S2’ • S1 • S0 O4 = G • S2 • S1’ • S0’

O5 = G • S2 • S1’ • S0 O6 = G • S2 • S1 • S0’

O7 = G • S2 • S1 • S0

Demultiplexers/decoders

• Decoders/demultiplexers: general concept

– single data input, n control inputs, 2ⁿ outputs

– control inputs (called “selects” (S)) represent binary index of output to which the input is connected

– data input usually called “enable” (G)

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Gate level implementation of demultiplexers

• 1:2 decoders

• 2:4 decoders

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demultiplexer generates appropriate minterm based on control signals

(it "decodes" control signals)

Demultiplexers as general-purpose logic

• A n:2

ⁿ

decoder can implement any function of n variables

– with the variables used as control inputs – the enable inputs tied to 1 and

– the appropriate minterms summed to form the function

A'B'C' A'B'C A'BC' A'BCAB'C' AB'CABC' ABC

C

A B

01 23 45 67 S2 3:8 DEC

S1 S0

“1”

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Demultiplexers as general-purpose logic (cont’d)

• F1 = A'BC'D + A'B'CD + ABCD

• F2 = ABC'D' + ABC

• F3 = (A' + B' + C' + D')

A B

0 A'B'C'D' 1 A'B'C'D 2 A'B'CD' 3 A'B'CD 4 A'BC'D' 5 A'BC'D 6 A'BCD'

7 A'BCD

8 AB'C'D' 9 AB'C'D 10 AB'CD' 11 AB'CD 12 ABC'D' 13 ABC'D 14 ABCD'

15 ABCD

4:16DEC Enable

C D

multiple input sources

multiple output destinations MUX

A B

Sum Sa

Ss

Sb B0

MUX

DEMUX

Mux and demux combination

• Uses in multi-point connections

B1

A0 A1

S0 S1

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