Hybrid Memory Cube Controller Design Example User Guide

Hybrid Memory Cube Controller Design Example User Guide

Last updated for Quartus Prime Design Suite: 16.0

Contents

Hybrid Memory Cube Controller Design Example Quick Start Guide...1-1

Design Example Directory Structure... 1-2 Design Example Components...1-2 Generating the Design Example... 1-4 Understanding the Testbench...1-6 Simulating the Design Example Testbench...1-6 Setting Up the Board... 1-7 Compiling and Testing the Design Example in Hardware... 1-9

Hybrid Memory Cube Controller Design Example Description... 2-1

Design Example Description...2-1 Features... 2-1 Hardware and Software Requirements... 2-1 Functional Description... 2-1 Interface Signals... 2-2 Design Example Register Map... 2-3

Additional Information...A-1

HMC Controller Design Example User Guide Revision History... A-1 How to Contact Altera... A-1 Typographic Conventions... A-2

TOC-2

Hybrid Memory Cube Controller Design

Example Quick Start Guide 1

2016.05.02

UG-20027 Subscribe Send Feedback

To help you understand how to use the Hybrid Memory Cube Controller IP core, the core features a simulatable testbench and a hardware design example that supports compilation and hardware testing.

When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware. You can download the compiled design to the Arria^® 10 GX FPGA Development Kit.

Figure 1-1: Development Steps for the Design Example

Example Design Generation

Compilation

(Simulator) Functional Simulation

Compilation

(Quartus Prime) Hardware Testing

Related Information

Hybrid Memory Cube Controller IP Core User Guide

© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

ISO 9001:2008 Registered

Design Example Directory Structure

Figure 1-2: Directory Structure for the Generated Design Example

hmcc_mtaps_0_example_design (default name of <example_design_install_dir>)

example_design

src sim

Supporting IP .qsys and other files

Supporting IP and testbench files

hmcc_example.qpf hmcc_example.qsf

<Simulation Script>

.

hmcc_tb.sv

.

<Simulation Script>

par

hmcc_example.sdc sysconsole_testbench.tcl Makefile

hmc_cfg.sv

ip

Hardware design files

The hardware configuration and test files (the hardware design example) are located in <example_

design_install_dir>/example_design/par. The simulation files (testbench for simulation only) are located in <example_design_install_dir>/example_design/sim.

Design Example Components

The HMC Controller hardware design example includes the following components:

• HMC Controller IP core with CDR reference clock set to 125 MHz and with default RX mapping and TX mapping settings.

Note: The design example requires these settings to operate properly on the Arria 10 GX FPGA Development Kit with the HMC daughter card.

• Client logic that coordinates the programming of the IP core, and packet generation and checking.

• JTAG controller that communicates with the Altera System Console. You communicate with the client logic through the System Console.

1-2 Design Example Directory Structure _2016.05.02^UG-20027

Figure 1-3: HMC Controller Design Example Block Diagram

HMC Controller IP Core

TX FIFOTX

MAC

RX MAC

Control and Status Interface

Initialization Initialization State Machine State Machine

Arria 10 Transceiver Reconfiguration

Interface Avalon-MM

TX Lane Swapper

RX Lane Swapper

Avalon-MM

I C Master

Transceiver x16 Data Path

Request Generator

and Response

Monitor

Test Controller

TX PLLs

HMC Device

LEDs

Arria 10 Device Board

2

Clocks & Reset

Table 1-1: HMC Controller IP Core Design Example Testbench File Descriptions Lists the key files that implement the example testbench.

File Names Description

Testbench and Simulation Files

/src/hmcc_example.sv Top-level hardware design example file.

/sim/hmcc_tb.sv Top-level file for simulation.

Testbench Scripts

Note: Use the provided Makefile to generate these scripts.

/sim/run_vsim.do The ModelSim script to run the testbench.

/sim/run_vcs.sh The Synopsys VCS script to run the testbench.

/sim/run_ncsim.sh The Cadence NCSim script to run the testbench.

UG-20027

2016.05.02 Design Example Components 1-3

Table 1-2: HMCC Controller IP Core Hardware Design Example File Descriptions

File Names Description

hmcc_example.qpf Quartus^® Prime project file

hmcc_example.qsf Quartus Prime project settings file

hmcc_example.sdc Quartus Prime project Synopsys Design Constraints file

../src/hmcc_example.sv Top-level Verilog HDL design example file Scripts

sysconsole_testbench.tcl Main file for accessing System Console

Generating the Design Example

Figure 1-4: Procedure

Start Parameter Editor

Specify IP Variation and Select Device

Select Design Parameters

Initiate Design Generation Specify

Example Design

1-4 Generating the Design Example _2016.05.02^UG-20027

Figure 1-5: Example Design Tab in Hybrid Memory Cube Controller Parameter Editor

Follow these steps to generate the Arria 10 hardware design example and testbench:

1. In the IP Catalog (^Tools > ^{IP Catalog}), select the Arria 10 target device family.

2. In the IP Catalog, locate and select Hybrid Memory Cube Controller. The New IP Variation window appears.

3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys.

4. You must select a specific Arria 10 device in the Device field, or keep the default device the Quartus Prime software selects.

5. Click OK. The IP parameter editor appears.

6. On the IP tab, specify the parameters for your IP core variation.

7. On the Example Design tab, choose the following settings for the design example:

a. For Select Design, select the HMCC Daughter Board option.

b. For Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.

c. For Generated HDL Format, only Verilog is available.

d. For Target Development Kit select the Arria 10 GX FPGA Development Kit (Production Silicon).

UG-20027

2016.05.02 Generating the Design Example 1-5

Note: When you choose this kit, the hardware design example overwrites your previous device selection with the device on the target board.

When you generate the design example, the Quartus Prime software creates Quartus Prime project, setting, and pin assignments for the board you selected. If you do not want the software to target a specific board, select None.

8. Click the Generate Example Design button.

Understanding the Testbench

Altera provides an design example with the HMC Controller IP core. The design example is available both for simulation of your IP core and for compilation. The design example in simulation functions as the HMC Controller IP core testbench.

If you click Generate Example Design in the HMC Controller parameter editor, the Quartus Prime software generates a demonstration testbench. The parameter editor prompts you for the desired location of the testbench.

To simulate the testbench, you must provide your own HMC bus functional model (BFM). Altera tests the design example testbench with the Micron Hybrid Memory Cube BFM. The testbench does not include an I²C master module, because the Micron HMC BFM does not support and does not require configuration by an I²C module.

In simulation, the testbench controls a TX PLL and the data path interfaces to perform the following sequence of actions:

1. Configures the HMC BFM with the HMC Controller IP core data rate and channel width, in Response Open Loop Mode.

2. Establishes the link between the BFM and the IP core.

3. Directs each of the IP core's four ports to write four packets of data to the BFM.

4. Directs the IP core to read back the data from the BFM.

5. Checks that the read data matches the write data.

6. If the data matches, displays TEST_PASSED.

Simulating the Design Example Testbench

Figure 1-6: Procedure

Change to Testbench Directory.

Run

<Simulation Script>. Analyze Results.

1-6 Understanding the Testbench _2016.05.02^UG-20027

Follow these steps to simulate the testbench:

1. At the command line, change to the <design example>/sim directory.

2. Type make scripts.

3. Type one of the following commands, depending on your simulator:

Simulator License Command Line

Mentor Graphics QuestaSim

make vsim HMC_MODEL=<HMC BFM directory^>

Synopsys VCS make vcs HMC_MODEL=<HMC BFM directory^>

Cadence NCSIM make ncsim HMC_MODEL=<HMC BFM directory^>

4. To view simulation results:

• When you run the testbench in any of the three supported simulators, the script executes the testbench sequence and logs the simulator activity in <design example directory>/example_design/

sim/<simulator>.log. <simulator> is "vsim", "ncsim", or "vcs".

• When you run the testbench in any of the three supported simulators, the script generates a waveform file. You can run the command ^make <simulator>^_gui to load the waveform in the simulator-specific waveform viewer.

To view the waveform file in your simulator, type one of the following commands:

Simulator License Command Line Waveform File

Mentor Graphics ModelSim

make vsim_gui <design example directory>/example_design/sim/

mentor/hmcc_wf.wlf Synopsys Discovery

Visual Environment

make vcs_gui <design example directory>/example_design/sim/

hmcc_wf.vpd Cadence SimVision

Waveform

make ncsim_gui <design example directory>/example_design/sim/

cadence/hmcc_wf.shm

5. Analyze the results. The successful testbench sends and receives ten packets per port, and displays

Test_PASSED"

Setting Up the Board

Set up the board to run the hardware design example.

Note: Ensure that power is turned off before you change any settings.

1. Set the DIP switches on the daughter card as follows:

Set DIP switch SW1 to indicate cube ID 0:

Switch Function Setting

1 CUB[0] Open

2 CUB[1] Open

UG-20027

2016.05.02 Setting Up the Board 1-7

Switch Function Setting

3 CUB[2] Open

4 — Don't Care

Set DIP switch SW2 to specify clock settings:

Switch Function Setting

1 CLK1_FSEL0 Open (125 MHz)

2 CLK1_FSEL1 Open (125 MHz)

3 CLK1_SEL Open (Crystal)

4 — Don't Care

2. Connect the HMC daughter card to the Arria 10 FPGA Development Kit using the daughter card's J8 and J10 connectors.

3. Set the jumpers on the Arria 10 GX FPGA Development Kit:

• Add shunts to the J8 jumper to select 1.5 V as the V_CCIO setting for FMC connector B.

• Add shunts to the J11 jumper to select 1.8 V as the V_CCIO setting for FMC connector A.

Figure 1-7: Arria 10 GX FPGA Development Kit and HMC Daughter Card

DIP Switches SW1 and SW2

Jumpers J8 and J11

HMC Daughter Card

Arria 10 GX FPGA Development Kit

1-8 Setting Up the Board _2016.05.02^UG-20027

Compiling and Testing the Design Example in Hardware

To compile and run a demonstration test on the hardware design example, follow these steps:

1. Ensure hardware design example generation is complete.

2. In the Quartus Prime software, open the Quartus Prime project <example_design_install_dir>/

example_design/par/hmcc_example.qpf.

3. In the Compilation Dashboard, click Compile Design (Quartus Prime Pro Edition) or choose Processing > Start Compilation (Quartus Prime Standard Edition).

4. After you generate a ^.sof, follow these steps to program the hardware design example on the Arria 10 device:

a. Choose Tools > Programmer.

b. In the Programmer, click Hardware Setup.

c. Select a programming device.

d. Select and add the Arria 10 GX FPGA Development Kit to which your Quartus Prime session can connect.

e. Ensure that Mode is set to JTAG.

f. Click Auto Detect and choose any device.

g. Double-click the Arria 10 device.

h. Open the ^.sof in <example_design_install_dir>/example_design/par/output_files, Note: The Quartus Prime software changes the device to the one in the ^.sof. i. In the row with your ^.sof, check the box in the Program/Configure column.

j. Click Start.

k. After the software configures the device with the hardware design example, observe the board LEDs:

• A blinking red LED signifies the design is running.

• Two green LEDs near the red blinking LED signifies that the HMC link is initialized and the test passed.

• One red LED near the red blinking LED signifies that the test failed.

l. Optional. Use the System Console testbench to observe additional test output.

Note: Use the System Console to monitor status signals in the design example when the board is connected to your computer via the JTAG interface. The System Console shows the board's LED status for remote monitoring, the initialization status for each step, and the status of each port’s request generator and response checker. The System Console also provides an interface to start or re-start the test.

a. Choose Tools > System Debugging Tools > System Console.

b. In the System Console, choose File > Execute Script.

c. Open the file <example_design_install_dir>/example_design/par/sysconsole_testbench.tcl. d. The software loads graphical test output. Choose Re-start to run the test again.

UG-20027

2016.05.02 Compiling and Testing the Design Example in Hardware 1-9

Figure 1-8: System Console Testbench Output

Related Information

• Programming Altera Devices

• Analyzing and Debugging Designs with System Console

1-10 Compiling and Testing the Design Example in Hardware _2016.05.02^UG-20027

Hybrid Memory Cube Controller Design

Example Description 2

2016.05.02

UG-20027 Subscribe Send Feedback

Design Example Description

The design example demonstrates the functionality of the Hybrid Memory Cube Controller IP core. You can generate the design from the Example Design tab of the Hybrid Memory Cube Controller graphical user interface (GUI) in the IP parameter editor.

Features

• I²C master and I²C initialization state machine for HMC daughter card and HMC configuration

• ATX PLL and transceiver recalibration state machine

• Request generator

• Request monitor

• System Console interface

Hardware and Software Requirements

Altera uses the following hardware and software to test the design example:

• Quartus Prime software

• System Console

• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL only), or VCS simulator

• Arria 10 GX FPGA Development Kit

• HMC daughter card

Functional Description

Altera provides a compilation-ready design example with the HMC Controller IP core. This design example targets the Arria 10 GX FPGA Development Kit with an HMC daughter card connected through the FMC connectors.

You can use the design as an example for correct connection of your IP core to your design, or as a starter design you can customize for your own design requirements. The design example includes an I²C master module, a PLL/CDR recalibration module, one external transceiver PLL IP core, and logic to generate and

© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

ISO 9001:2008 Registered

check transactions. The design example assumes a Micron HMC 15G-SR HMC device, which is a four- link device, on the daughter card. The design example includes one instance of the IP core and connects to a single link on the HMC device.

Figure 2-1: HMC Controller Design Example Block Diagram

HMC Controller IP Core

TX FIFOTX

MAC

RX MAC

Control and Status Interface

Initialization Initialization State Machine State Machine

Arria 10 Transceiver Reconfiguration

Interface Avalon-MM

TX Lane Swapper

RX Lane Swapper

Avalon-MM

I C Master

Transceiver x16 Data Path

Request Generator

and Response

Monitor

Test Controller

TX PLLs

HMC Device

LEDs

Arria 10 Device Board

2

Clocks & Reset

After you configure the Arria 10 FPGA with the design example, the I²C controller configures the on- board clock generators and the HMC device. When calibration completes, the design example calibrates the ATX PLL. During operation, the request generator generates read and write commands that the HMC Controller IP core then processes. The request monitor captures the responses from the IP core and checks them for correctness.

Interface Signals

Table 2-1: HMC Controller IP Core Design Example Signals

Signal Name Direction Width (Bits) Description

2-2 Interface Signals _2016.05.02^UG-20027

Signal Name Direction Width (Bits) Description

hmc_lxrx Input Channel Count (16

or 8) FPGA transceiver receive pins.

hmc_lxtx Output Channel Count (16

or 8) FPGA transceiver transmit pins.

hmc_ctrl_lxrxps Input 1 FPGA transceiver power save

control.

hmc_ctrl_lxtxps Output 1 HMC transceiver power save

control.

hmc_ctrl_ferr_n Input 1 HMC ^FERR_N output.

hmc_ctrl_p_rst_n Output 1 HMC ^P_RST_N input.

hmc_ctrl_scl Bi-Directional 1 HMC I²C configuration clock.

hmc_ctrl_sda Bi-Directional 1 HMC I²C configuration data.

fmc0_scl Output 1 Unused. Driven low to protect the

FPGA I/O pins from the 3.3 V pullup on the daughter card.

fmc0_sda Output 1 Unused. Driven low to protect the

FPGA I/O pins from the 3.3 V pullup on the daughter card.

push_button Input 1 Push button input used for reset.

heart_beat_n Output 1 Heartbeat LED output.

link_init_complete_n Output 1 Link initialization complete LED output.

test_passed_n Output 1 Test passed LED output.

test_failed_n Output 1 Test failed LED output.

Design Example Register Map

Table 2-2: HMC Controller IP Core Design Example Register Map

Offset Register

0x00 DESIGN_INFO and ^RESET

0x01 ^BOARD_LEDS

0x02 TEST_INITIALIZATION_STATUS

0x03 PORT_TEST_STATUS

UG-20027

2016.05.02 Design Example Register Map 2-3

Table 2-3: DESIGN_INFO AND RESET Registers Writing to these registers resets the design.

Bits Field Name Type Value on Reset Description

1:0 Port Count RO Varies Number of ports for the IP core

instance.

7:2 Reserved RO 0x00

Table 2-4: BOARD_LEDs Register

This register reflects the status of the board's LEDs.

Bits Field Name Type Value on Reset Description

0 Test Failed RO 0x00 Test failed.

1 Test Passed RO 0x00 Test passed.

2 HMCC Link

Initialization Complete RO 0x00 HMC link initialization complete and ready for traffic.

3 Heartbeat RO 0x00 Toggles when the design is

running.

7:4 Reserved RO 0x00

Table 2-5: TEST_INITIALIZATION_STATUS Register

Bits Field Name Type Value on Reset Description

0 I²C Clock Generator

Set RO 0x00 On- board clock generators

configured.

1 ATX PLL and

Transceiver

Recalibration Complete

RO 0x00 ATX PLL and transceivers re-

calibrated to the input clock.

2 I²C HMC

Configuration Complete

RO 0x00 HMC device configuration over

I²C complete.

3 HMC Link

Initialization Complete RO 0x00 HMC link initialization

complete and ready for traffic.

7:4 Reserved RO 0x00

Table 2-6: PORT_STATUS Register

Bits Field Name Type Value on Reset Description

0 Port 0 Requests OK RO 0x00 Port 0 request generation

complete.

2-4 Design Example Register Map _2016.05.02^UG-20027

Bits Field Name Type Value on Reset Description

4 Port 2 Requests OK RO 0x00 Port 2 request generation

complete.

5 Port 2 Responses OK RO 0x00 Port 2 response checking passed.

6 Port 3 Requests OK RO 0x00 Port 3 request generation

complete.

7 Port 4 Responses OK RO 0x00 Port 3 response checking passed.

UG-20027

2016.05.02 Design Example Register Map 2-5

Additional Information A

2016.05.02

UG-20027 Subscribe Send Feedback

HMC Controller Design Example User Guide Revision History

Table A-1: Document Revision History

Summarizes the new features and changes in the design example user guide for the HMC Controller IP core.

Date ACDS Version Changes

2016.05.02 16.0 Initial release.

How to Contact Altera

Table A-2: How to Contact Altera

To locate the most up-to-date information about Altera products, refer to this table. You can also contact your local Altera sales office or sales representative.

Contact Contact Method Address

Technical support Website www.altera.com/support

Technical training Website www.altera.com/training

Email [email protected]

Product literature Website www.altera.com/literature

Nontechnical support: general Email [email protected]

Nontechnical support: software

licensing Email [email protected]

Related Information

• www.altera.com/support

• www.altera.com/training

• [email protected]

• www.altera.com/literature

• [email protected]

• [email protected]

Typographic Conventions

Table A-3: Typographic Conventions

Lists the typographic conventions this document uses.

Visual Cue Meaning

Bold Type with Initial Capital Letters Indicate command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitaliza‐

tion matches the GUI.

bold type Indicates directory names, project names, disk drive

names, file names, file name extensions, software utility names, and GUI labels. For example, \ qdesigns directory, D: drive, and chiptrip.gdf file.

Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix V Design Guidelines.

italic type Indicates variables. For example, n + 1.

Variable names are enclosed in angle brackets (< >).

For example, <file name> and <project name> . pof file.

Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the Options menu.

“Subheading Title” Quotation marks indicate references to sections in a document and titles of Quartus Prime Help topics.

For example, “Typographic Conventions.”

A-2 Typographic Conventions _2016.05.02^UG-20027

Visual Cue Meaning

Courier type Indicates signal, port, register, bit, block, and primitive names. For example, ^data1, ^tdi, and

input. The suffix ⁿ denotes an active-low signal.

For example, ^resetn.

Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword ^SUBDESIGN), and logic function names (for example, ^TRI).

1., 2., 3., and a., b., c., and so on Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

• Bullets indicate a list of items when the sequence of

the items is not important.

The Subscribe button links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents.

The Feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.

Related Information

Email Subscription Management Center

UG-20027

2016.05.02 Typographic Conventions A-3