Reusable IP core for Forward Error Correcting
Codes
Farhan Aadil, Shahzada Khayyam Nisar, Wajahat Abbas, Asim Shahzad
Department of Software Engineering,
University of Engineering and Technology, Taxila, Pakistan
[farhan.aadil | shahzada.khayyam | wajahat.abbas | asim.shahzad]@uettaxila.edu.pk
Abstract-- Error Correction codes are a mean of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. Forward Error Correcting codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratio. These codes achieve a near-S hannon limit performance. Owing to the computational complexity of these FEC codes they are we ll suited for optimized implementation using custom hardware in FPGA. As; this allows us more parallelism and less latency.
I. INTRODUCTION
The availability of wireless technology has revolutionized the way communication is done in our world today. Cellular and Satellite technologies make it possible for people to be connected to the rest of the world from anywhere. With this increase availability comes increased dependency on the under line systems to transmit information both quickly and accurately. Because the communication channels in wireless systems can be much more hostile than in ―wired‖ systems, voice and data must use forward error correction coding to reduce the possibility of channel affects corrupting the information being transmitted [1]. Our research is based on the field of digital Communications. We used FPGA board
XCS3S1000 to achieve the following
2 Bit Error detection
2 Bit Error Correction
In Case of Convolution codes supports
constraint length K of 3 and in MATLAB supports K=3 to 7
In case of Block codes n=7 and k=3
II. FORWARD ERROR CORRECTION
FEC codes or channel codes have become an inevitable in wireless based digital communication systems. That is, by allowing a system to operate at a lower signal to noise ratio than would otherwise be the case, a desired quality of service over a link can be achieved within a transmit power or antenna gain constraints of the system [1] [3]. This property of error correcting codes is often referred to as ‗Power Efficiency‘. Fig. 1. shows an error correcting code within a digital communication system. The channel encoder adds code bits to the transmission bit stream, based on the data bits at its input. These extra bits are used by the channel decoder at the receiver to correct errors introduced into the transmission stream by a noisy or fading channel.
Fig. 1. A T ypical Digital Communication System
Forward error correction (FEC) is a system of error control for data transmission, whereby the sender adds redundant data to its messages, also known as an error correction code [4]. This allows the receiver to detect and correct errors (within some bound) without the need to ask the sender for additional data.
Fig. 2. Forward Error Correction
Forward Error Correction is a critical component in man y
modern digital communications applications, turning
otherwise unusable communications links into real and practical systems. From DVDs to cell phones, satellite TV to disk drives, error correction technology is a mathematical marvel that effectively makes a silk purse from a sow‘s ear [5].
HOW IT WORKS
FEC is accomplished by adding redundancy to the transmitted information using a predetermined algorithm. Each redundant bit is invariably a complex function of many original information bits. The original information may or may not appear in the encoded output; codes that include the
unmodified input in the output are systematic, while those
that do not are nonsystematic. An extremely simple example
would be an analog to digital converter that samples three bits of signal strength data for every bit of transmitted data. If the
Noise
Sender Encoder Modulator
Channel
User Decoder Demodulator
three samples are mostly all zero, the transmitted bit was probably a zero, and if three samples are all one, the transmitted bit was probably a one. The simplest example of error correction is for the receiver to assume the correct output is given by the most frequently occurring value in each group of three as shown in the table.
TABLE I
ANALOG TO DIGITAL CONVERTER THAT SAMP LES THREE BITS OF SIGNAL TO ONE BIT
Triplet Received Interpreted as
000 0
001 0
010 0
100 0
111 1
110 1
101 1
011 1
FEC could be said to work by "averaging noise"; since each data bit affects many transmitted symbols, the corruption of some symbols by noise usually allows the original user data to be extracted from the other, uncorrupted received symbols that also depend on the same user data.
Most telecommunication systems used a fixed channel code designed to tolerate the expected worst-case bit error rate, and then fail to work at all if the bit error rate is ever worse. However, some systems adapt to the given channel error conditions: hybrid automatic repeat-request uses a fixed FEQ method as long as the FEQ can handle the error rate, then switches to ARQ when the error rate gets to high; adaptive modulation and coding uses a variety of FEQ rates, adding more error-correction bits per packet when there are higher error rates in the channel, or taking them out when they are not needed.
CONVOLUTIONAL CODING
Convolution codes are a popular class of coders with memory, i.e., the coding of an information block is a function of the previous blocks [6]. A Convolutional code is a type of error-correcting code in which
(a) Each m-bit information symbol (each m-bit string) to be
encoded is transformed into an n-bit symbol, where m/n is the code rate (n ≥ m) and
(b) The transformation is a function of the last k information
symbols, where k is the constraint length of the code.
Convolutional codes are often used to improve the performance of digital radio, mobile phones, satellite links, and Bluetooth implementation [7].
Convolution codes involve simple arithmetic op erations and therefore they are easily implemented. If a block code is used for error detection, only simple integer division is needed; however, decoding block codes or convolution codes for error correction is much more tedious [8].
For block codes, an iterative algorithm is often used to correct the errors. Error correction algorithms become quite complex for long codes with large error correction capability; especially, for non-binary codes.
For convolution codes, decoders are often based on the Veterbi algorithm which is known to be an optimal algorithm. Its decoding complexity grows exponentially with code memory length. Therefore it is effective for short memory length codes.
Veterbi Decoding Algorithm
The Veterbi Algorithm (named after Andrew Veterbi) is a dynamic algorithm that uses certain path metrics to compute the 'most likely' path of a transmitted sequence. From this 'most likely' path, certain bit errors can be corrected to decipher the original bit sequence after it has been sent down a communicative line.
An important feature of the Veterbi algorithm is that ties are arbitrarily solved (can be picked randomly) and still yield an original sequence [8]. What the Veterbi algorithm can do is correctly replicate your input string at the outpu t even in the presence of one or more errors. Obviously, with more errors introduced the likelihood of a successful decryption does go down.
Convolution encoding and veterbi decoding are the most popular because of their powerful coding-gain performances. Convolutional encoder and veterbi decoder is extensively used in a wide variety of devices to reduce transmitted power, decrease the degrading effects of noise in the channel. This veterbi decoder is used in devices ranging from the mobile phones people use in the daily life to the more complex satellite receivers and deep space missions. Veterbi decoder is mainly used in the wireless connections where the additive wide Gaussian noise is pre dominanat. FEC suit FPGA because they have efficient parallel architecture, we can reconfigure them without nonrecurring-engineering costs, and their performance is always improving [9].
Fig. 3. Convolutional encoder with Veterbi decoder
VETERBI DECODER TECHNICAL SPECIFICATIONS
Constraint Length, K=7
Code Rate k/n=1/2, Where k=input bit/s and n=no of
output data bits
Parameterizable Constraint Length From 3 to 7
High Speed compact Veterbi Decoder
APPLICATIONS OF VETERBI
Wireless LAN
Digital Cellular Phones
Z
Noise
R Y
X Convolution Encoder
Viterbi Decoder
Communication s Channel or Storage Device
Satellite Communications
Digital Video Broad Casting
Digital wireless Transmitters and receivers
REED SOLOM ON CODES
Reed-Solomon codes are block codes. This means that a fixed block of input data is processed into a fixed block of output data. In the case of the most commonly used R-S code (255, 223) – 223 Reed-Solomon input symbols (each eight bits long) are encoded into 255 output symbols [2].
Most R-S ECC schemes are systematic. This means
that some portion of the output codeword contains the input data in its original form.
A Reed-Solomon symbol size of eight bits was
chosen because the decoders for larger symbol sizes would be difficult to implement with current technology. This design choice forces the longest codeword length to be 255 symbols.
The standard (255, 223) Reed-Solomon code is
capable of correcting up to 16 Reed-Solomon symbol errors in each codeword. Since each symbol is actually eight bits, this means that the code can correct up to 16 short bursts of error due to the inner convolutional decoder.
The Reed-Solomon code, like the convolutional code, is a transparent code. This means that if the channel symbols have been inverted somewhere along the line, the decoders will still operate. The result will be the complement of the original data. However, the Reed-Solomon code loses its transparency if virtual zero fill is used. For this reason it is mandatory that the sense of the data (i.e., true or complemented) be resolved before Reed-Solomon decoding [8].
Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage. Reed-Solomon codes are used to correct errors in many systems including:
Storage devices (including tape, Compact Disk,
DVD, barcodes, etc)
Wireless or mobile communications (including
cellular telephones, microwave links, etc)
Satellite communications
Digital television / DVB
High-speed modems such as ADSL, xDSL, etc.
In addition, the Reed-Solomon codewords can be interleaved on a symbol basis before being convolutionally encoded. Since this separates the symbols in a codeword, it becomes less likely that a burst from the Viterbi decoder disturbs more than one Reed-Solomon symbol in any one codeword [2] [8]. A typical system is shown here
Fig. 4. Reed Solomon Encoder/Decoder
The Reed-Solomon encoder takes a block of digital data and adds extra "redundant" bits. Errors occur during transmission or storage for a number of reasons (for example noise or interference, scratches on a CD, etc). The Reed -Solomon decoder processes each block and attempts to correct errors and recover the original data. The number and type of errors that can be corrected depends on the characteristics of the Reed-Solomon code.
PROPERTIES OF REED-SOLOM ON CODES
The error-correcting ability of any Reed-Solomon code is determined by n − k, the measure of redundancy in the block. If the locations of the errored symbols are not known in advance, then a Reed–Solomon code can correct up to (n − k) / 2 erroneous symbols, i.e., it can correct half as many errors as there are redundant symbols added to the block. Sometimes error locations are known in advance (e.g., ―side information‖ in demodulator signal-to-noise ratios) these are called
erasures [2]. A Reed–Solomon code (like any linear code) is able to correct twice as many erasures as errors, and any combination of errors and erasures can be corrected as long as the inequality 2E + S < n − k is satisfied, where E is the number of errors and S is the number of erasures in the block.Reed Solomon codes are a subset of BCH codes and are linear block codes. A Reed-Solomon code is specified as RS
(n, k) with s-bit symbols. This means that the encoder takes k
data symbols of s bits each and adds parity symbols to make
an n symbol codeword. There are n-k parity symbols of s bits
each. A Reed-Solomon decoder can correct up to t symbols
that contain errors in a codeword, where 2t = n-k.
The following diagram shows a typical Reed-Solomon codeword (this is known as a Systematic code because the data is left unchanged and the parity symbols are appended)
The properties of Reed-Solomon codes make them especially well-suited to applications where errors occur in bursts [10] [11] [12]. This is because it does not matter to the code how many bits in a symbol are in error—if multiple bits in a symbol are corrupted it only counts as a single error. Conversely, if a data stream is not characterized by error
Data Sink
Noi s e/error
Data
Source Reed-Solomon
Encoder
bursts or dropouts but by random single bit errors, a Reed -Solomon code is usually a poor choice.
REED SOLOM ON ENCODER / DECODER TECHNICAL
SPECIFICATIONS
Symbol Length(m)=3 to 24
No of input Symbols to encoder=k symbols
No of encoded symbols of encoder=n symbols
Error detecting capability(d)=n-k
Error correcting capability(t)=(n-k)/2
Use for Burst Error correction
APPLICATIONS OF REED SOLOM ON CODES
The Digital Audio Disc
Deep Space Telecommunication Systems
Error Control for Systems with Feedback
Spread-Spectrum Systems
Computer Memory
III. SIM ULATIONS AND RESULTS
Our research paper consists of two main phases. In the first phase we have implemented these FEC codes (convolution Encoder with Veterbi decoder & Reed Solomon encoder/decoder) in M ATLAB. And in other phase we have implemented these codes on FPGA board by using the software‘s like XILINX &MODELS IM.
CONVOLUTIONAL ENCODER & VETERBI DECODER
USING MATLAB Step 1
In the first step we have made a XLS file named ―data‖ that
provide the input bits 10110100 for the convolutional encoder.
The XLS file look like this
Fig. 5. Data in MS Excel
Step 2
In the second step we call the transceiver function in MATLAB work space window this will open a new dialog
box that ask you to enter the name of fileand the type of the
file like this
Fig. 6. Data in MAT LAB
There are threesteps involve in the transceiver function
1) Transceiver function calls the encoder function that gets the
input bits, upper polynomial and lower polynomial and provides us the convolved data.
2) It introduce error in the data .If 8 bit data is provided it
creates 1 bit error and 2 bit error for higher no of bits.
3) In the end it perform the decoding by calling veterbi
decoder function that removes the redundant bits detect and correct the error and provide us the actual no of bits that we have transmitted.
Here we have given the input data 10110100 asshown from
the file named ―data.xls‖. Encoded data is
1110100111101001 and the decoded data is same as the input data.
Fig. 7. Data in MAT LAB (1)
REED SOLOM ON ENCODER & DECODER USING MATLAB Step1
Fig. 8. Data in MS Excel
Step 2
In the second step we call the RS_Transceiver function in
MATLAB work space window this will open a new dialog
box that ask you to enter the name of fileand the type of the
file like this
Fig. 9. Data in MAT LAB
T here are threesteps involve in the transceiver function
1) T ransceiver function calls the encoder function that gets the input bits symbol,
2) It introduces error in the data. Reed Solomon can correct the burst error therefore error is introduced in two symbols.
3) In the end it perform the decoding by calling RS decoder function that detect and correct the error in the symbols and provide us the actual no of bits that we have transmitted.
Fig. 10. Data in MAT LAB (1)
Here we have given the input data 010110111as shown from
the file named ―RS_Data.xls‖. Encoded data is
100001011101010110111 and the decoded data is same as the input data.
IV. MODELSIM SIMULATION
CONVOLUT IONAL ENCODER
VET ERBI DECODER
Fig. 11. Simulations
SOFTWARE ARCHITECTURE
CONVOLUT IONAL ENCODER & VET ERBI DECODER
Fig. 12. Software Architecture
VETERBI DECODER TECHNICAL SPECIFICATIONS
Constraint Length, K=7
Code Rate k/n=1/2, Where k=input bit/s and n=no of
output data bits
High Speed compact Veterbi Decode
REED SOLOMON ENCODER & DECODER
Fig. 13. Reed Solomon Encoder & decoder
REED SOLOM ON ENCODER / DECODER TECHNICAL
SPECIFICATIONS
Symbol Length(m)=3 to 24
No of input Symbols to encoder=k symbols
No of encoded symbols of encoder=n symbols
Error detecting capability(d)=n-k
Error correcting capability(t)=(n-k)/2
Use for Burst Error correction
ACHIEVED RESULTS AND CONCLUSIONS
In our research we have implemented Convolutional Encoder and Veterbi decoder, Reed Solomon Encoder and Decoder in MATLAB as well as in Verilog and implement them on FPGA, thus achieved the required results.
FUTURE RECOM M ENDATIONS
We would like to recommend the following features to be incorporated in our developed software
Constraint length k can be increased Error Detection capability can be increased Error Correction capability can be increased Interfacing can be implemented
REFERENCES
[1] X. Yu, J. Modestino, and I. Bajic, ―Performance analysis of the efficacy of packet-level FEC in improving video transport over networks,‖ in Proc. IEEE Int. Conf. Image Process. (ICIP ‘05), pp. II-177–II-180.
[2] Reed Solomon Forward Error Correction Codes,
http://en.wikipedia.org/wiki/Reed-Solomon_error_correction [3] Dan Jurca et al, ―Forward Error Correction for Multipath
Media Streaming‖ IEEE Transactions on circuits and syst ems for video technology, vol. 19, no. 9, pp 1315-1326, September 2009
[4] Why Digital Fountain's Raptor Code Is Better Than Reed Solomon Erasure Codes For Streaming Applications, 2005 Digital Fountain, Inc.
[5] Recent Advances in Error/Erasure Correcting and Coding, Vijay Subramanian, Networks Lab - RPI,
http://networks.ecse.rpi.edu/pubs/ecc.ppt
[6] 3GPP T SG-SA4#31 Tdoc S4-040348 May 17-21, 2004, Montreal, Canada, Simulation Guidelines for the Evaluation of FEC Methods for MBMS Download and Streaming Services.
[7] Frenger, P., P. Orten, and T . Ottosson, "Convolution Codes with Optimum Distance Spectrum," IEEE Communications Letters, vol. 3,pp. 317-319, November 1999.
[8] Ufuk DEMIR and Ozlem AKTA$ ―Raptor versus Reed Solomon Forward Error Correction Codes‖ Proceedings of the Seventh IEEE International Symposium on Computer Networks (ISCN'06) pp 264-269, 2006
[9] B. Fong et al. ―Forward Error Correction with Reed-Solomon Codes for Wearable Computers‖ IEEE T ransactions on Consumer Electronics, Vol. 49, No. 4, pp 917 -921, NOVEMBER 2003 [10] L. Yin, J. Lu, K. Ben Letaief and Y. Wu, "Burst -error correcting
algorithm for Reed-Solomon codes", Electronics Letters, Vol. 37 No. 11, May 25, 2001, pp. 695 - 697
[11] T ed H. Szymanski, ―Optical Link Optimization Using Embedded Forward Error Correcting Codes‖ IEEE Journal of selected topics in quantum electronics, vol. 9, no. 2, pp 647 -656, March/April 2003
[12] Peter Klapproth, ―General Architectural Concepts for IP Core Re-Use ―Proceedings of the 15th International Conference on VLSI Design (VLSIDí02), 2002
Mr. Farhan Aadil Malikis student of MS Software
Engineering at University of Engineering & T echnology T axila. He earned his Bachelor‘s degree in Computer Sciences from Allama Iqbal Open University, Islamabad, Pakistan in 2005 with distinction and currently working as Programmer at UET T axila. His current areas of interest are ad hoc Networks and Data Communication Systems & Security.
Mr. Shahzada Khayyam Nisar completed his graduation
in Computer Sciences from Allama Iqbal Open University, Islamabad Pakistan in 2004 with honors. He was awarded Allama Iqbal Award by the University. He is also HEC Scholarship holder. Currently he is student of MS Software Engineering at UET, Taxila. He has more than 5 years of teaching experience, presently working as Programmer at UET , T axila. His areas of interest are Vehicular ad hoc Networks and Data Communication Systems & Security.
Mr. W ajahat Abbas is pursuing his PhD from University
of Engineering & T echnology T axila, Pakistan. He has completed his M.S in Computer Engineering from UET T axila. He is also working as Lecturer in the department of Software Engineering, UET T axila. His areas of interest are Vehicular ad hoc Networks and Parallel & Distributed Computing.
Mr. Asim Shahzad is pursuing his PhD from University of
