ECE 5745 Complex Digital ASIC Design
Course Overview
Christopher Batten
School of Electrical and Computer Engineering
Cornell University
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
RTL
Devices
ISA
PL
Algorithm
Arch
Technology
Application
OS
Gates
Circuits
Complex Digital ASIC Design
I
Course goal, structure, motivation
.
What is the goal of the course?
.
How is the course structured?
.
Why should students want to take this course?
I
Activity 1: Evaluation of Integer Multiplier
I
Case Study: Scalar vs. Vector Processors
.
Example design-space exploration
.
Example real ASIC chips
I
Activity 2: Brainstorming for Sorting Accelerator
I
Course Logistics
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
The Computer Engineering Stack
Technology
Application
Gap too large to bridge in one step
(but there are exceptions e.g., magnetic compass)
In its broadest definition, computer architecture is the
design of the abstraction/implementation layers
that allow us to
execute information processing
applications
efficiently
using available manufacturing
technologies
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
The Computer Engineering Stack
In its broadest definition, computer architecture is the
design of the abstraction/implementation layers that allow us to
execute information processing applications efficiently
using available manufacturing technologies
Circuits
Devices
Programming Language
Algorithm
C
o
m
p
u
te
r
A
rchit
e
ct
u
re
Technology
Application
Register-Transfer Level
Instruction Set Architecture
Microarchitecture
Operating System
Gate Level
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
What is Computer Architecture?
In its broadest definition, computer architecture is the
design of the abstraction/implementation layers
that allow us to
execute information processing
applications
efficiently
using available manufacturing
technologies
Circuits
Devices
Programming Language
Algorithm
C
o
m
p
u
te
r
A
rchit
e
ct
u
re
Technology
Application
Register-Transfer Level
Instruction Set Architecture
Microarchitecture
Operating System
Gate Level
Operating System
Gate Level
Register-Transfer Level
Instruction Set Architecture
Microarchitecture
Application Requirements
• Suggest how to improve architecture
• Provide revenue to fund development
Technology Constraints
• Restrict what can be done efficiently
• New technologies make new arch possible
Architecture provides feedback to guide
application and technology research directions
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
Key Metrics in Computer Architecture
P
I$
D$
Network
Network
Network
P
I$
P
I$
P
I$
D$
D$
D$
I
Primary Metrics
.
Execution time (cycles/task)
.
Energy (Joules/task)
.
Cycle time (ns/cycle)
.
Area (µm
2
)
I
Secondary Metrics
.
Performance (ns/task)
.
Average power (Watts)
.
Peak power (Watts)
.
Cost ($)
.
Design complexity
.
Reliability
.
Flexibility
Discuss qualitative first-order analysis
from ECE 4750 on board
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
Unanswered Questions from ECE 4750
P
I$
D$
Network
Network
Network
Xcel
P
I$
D$
D$
D$
Xcel
Accelerated
Instructions
I
How can we quantitatively evaluate
area, cycle time, and energy?
I
How do we actually implement
processors, memories, and
networks in a real chip?
I
How should we analyze
application-specific accelerators?
.
Very loosely coupled
memory-mapped accelerators
.
More tightly coupled co-processor
accelerators
.
Specialized instructions and
functional units
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
Application-Specific Accelerators
P
I$
D$
Network
Network
Network
Xcel
P
I$
D$
D$
D$
Xcel
Accelerated
Instructions
Performance (Tasks per Second)
Simple
Proc
Processor Power
Constraint
E
ne
rgy
(Jou
le
s
p
e
r
T
as
k)
C
B
A
A
A
A
Superscalar
w/ Deeper
Pipelines
Out-of-Order
Superscalar
Superpipelined
D
E
E
Multicore
F
F
Multicore E
A
A
A
A
Specialized Accelerators
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
Application-Specific Accelerators
P
I$
D$
Network
Network
Network
Xcel
P
I$
D$
D$
D$
Xcel
Accelerated
Instructions
Performance (Tasks per Second)
E
ne
rgy
E
ff
ici
e
ncy
(T
as
ks
p
e
r
J
o
u
le
)
Simple
Processor
Design Power
Constraint
High-Performance
Architectures
Embedded
Architectures
Design
Performance
Constraint
Fl
exibil
ity
vs
. S
peci
al
izat
io
n
Custom
ASIC
Less Flexible
Accelerator
More Flexible
Accelerator
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
Goal for ECE 5745 is to answer these questions!
P
I$
D$
Network
Network
Network
Xcel
P
I$
D$
D$
D$
Xcel
Accelerated
Instructions
I
How can we quantitatively evaluate
area, cycle time, and energy?
I
How do we actually implement
processors, memories, and
networks in a real chip?
I
How should we analyze
application-specific accelerators?
.
Very loosely coupled
memory-mapped accelerators
.
More tightly coupled co-processor
accelerators
.
Specialized instructions and
functional units
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
Full Custom Design vs. Standard-Cell Design
L01 –
Intro
duction 22
6.8
84
–
Sp
rin
g
2
00
5
2 Feb 2005
Full Custom Design
Designer
is
free
to
do
anything,
anywhere
–
though
each
design
team
usually
imposes
some
discipline
Most
time
consuming
design
style
–
Reserved
for
very
high
performance
or
very
high
volume
devices
(Intel
microprocessors,
RF
power
amps
for
cellphones)
Requires
complete
customization
of
all
layers
of
wafer
Piece
of
full-custom
multiplier
array,
1.0
m
2-metal
Full-custom layout
in 1.0µm w/ 2 metal
layers
I
Full-Custom Design
.
Designer is free to do anything, anywhere; though
team usually imposes some design discipline
.
Most time consuming design style; reserved for
very high performance or very high volume chips
(Intel microprocessors, RF power amps for
cellphones)
I
Standard-Cell Design
.
Fixed library of “standard cells” and SRAM
memory generators
.
Register-transfer-level description is automatically
mapped to this library of standard cells, then these
cells are placed and routed automatically
• Complex Digital ASIC Design
•
Activity 1
Case Study: Scalar vs. Vector Processors
Activity 2
Standard-Cell Design Methodology
L01 – Introduction 24 6.884 – Spring 2005 2 Feb 2005
