IRPS 2021 March 21-24, 2021

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IRPS 2021

March 21- 24, 2021

Schedule is in Pacific Daylight Time (PDT)

*Minor changes to the program may occur, please check the live version for the most up-to-date information https://irps2021.exordo.com/programme/preview/at-a-glance

21st March 2021 8:00am

Welcome & IRPS Introduction

8:00am - 8:10am: General Chair Welcome Remarks 8:10am - 8:20am: Overview of Technical Program 8:20am - 8:35am: Awards

Keynote 1 - Seok-Hee Lee, CEO SK Hynix

KN1 (Keynote) - Memory’s journey towards the future information and communications technology (ICT) world

Seok-Hee Lee(United States) - SK Hynix 21st March 2021 9:20am

2A - Intro

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2B - Intro

2C - Intro

Tutorial 1 - Reliability Challenges with 3D Integration of Semiconductor

Packaging

TuT1 (Keynote) - Reliability Challenges with 3D Integration of Semiconductor Packaging Mohammad Kabir(United States) - Intel Corporation

2A - GD

2A.1 (ESREF) - TBD

Mauro Ciappa(Switzerland) - ETH Zürich, Marco Pocaterra(Switzerland) - ETH Zürich 2A.2 - Characterization of slow traps in SiGe MOS interfaces by TiN/Y2O3 gate stacks

Tsung-En Lee(Japan) - The University of Tokyo, Kasidit Toprasertpong(Japan) - The University of Tokyo, Mitsuru Takenaka(Japan) - The University of Tokyo, Shinichi Takagi(Japan) - The University of Tokyo 2A.3 - Off-state TDDB in FinFET Technology and its Implication for Safe Operation Area

Maria Toledano Luque(United States) - GlobalFoundries, Germain Bossu(Germany) - GlobalFoundries, Peter Paliwoda(United States) - GlobalFoundries, Mohamed Nour(United States) - GlobalFoundries, Thomas Kauerauf(United States) - GlobalFoundries, Mahesh Siddabathula(Germany) -

GlobalFoundries, Byoung Min(United States) - GlobalFoundries, Tanya Nigam(United States) - GLOBALFOUNDRIES Inc

2A.4 - Drastic reliability improvement using H2O2 treatment on HfO2 for heterogeneous integration Seung-Mo Kim(Korea, Republic of) - Pohang University of Science and Technology, Thi Mi Hanh

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of) - Gwangju institute of science and technology, Yongsu Lee(Korea, Republic of) - Pohang University of Science and Technology, Soo Cheol Kang(Korea, Republic of) - Electronics and Telecommunications Research Institute, Ho-In Lee(Korea, Republic of) - Pohang University of Science and Technology, Cihyun Kim(Korea, Republic of) - Pohang University of Science and Technology, Surajit Some(Korea, Republic of) - Pohang University of Science and Technology, Hyeon Jun Hwang(Korea, Republic of) - Pohang University of Science and Technology, Byoung Hun Lee(Korea, Republic of) - Pohang University of Science and Technology

2A.5 - Modeling of HKMG Stack Process Impact on Gate Leakage, SILC and PBTI

Dimple Kochar(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay), Tarun Samadder(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay), Subhadeep Mukhopadhyay(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay), Souvik Mahapatra(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay)

2B - GaN

2B.1 (Invited) - TBD

Stephanie Butler(United States) - TI/IFX, Tim McDonald(United States) - Infineon 2B.2 - Failure Mechanisms of Cascode GaN HEMTs Under Surge Energy

Qihao Song(United States) - Virginia Tech, Ruizhe Zhang(United States) - Virginia Tech, Joseph P. Kozak(United States) - Virginia Tech, Jingcun Liu(United States) - Virginia Tech, Qiang Li(United States) - Virginia Tech, Yuhao Zhang(United States) - Virginia Tech

2B.3 - Vertical stack reliability of GaN-on-Si buffers for low-voltage applications

Elena Fabris(Belgium) - imec, Matteo Borga(Belgium) - imec, Niels Posthuma(Belgium) - imec, Ming Zhao(Belgium) - imec, Brice De Jaeger(Belgium) - imec, Shuzhen You(Belgium) - imec, Matteo Meneghini(Italy) - University of Padova, Gaudenzio Meneghesso(Italy) - University of Padova, Enrico Zanoni(Italy) - University of Padova, Stefaan Decoutere(Belgium) - imec

2B.4 - A Generalized Approach to Determine the Switching Reliability of GaN HEMTs on-Wafer Level Nicola Modolo(Italy) - University of Padova, Carlo de Santi(Italy) - University of Padova, Sebastien Sicre(Austria) - Infineon Technologies Austria AG, Gerhard Prechtl(Austria) - Infineon Technologies Austria AG, Gaudenzio Meneghesso(Italy) - University of Padova, Enrico Zanoni(Italy) - University of Padova, Matteo Meneghini(Italy) - University of Padova

2B.5 - Study on the difference between ID(VG) and C(VG) pBTI shifts in GaN-on-Si E-mode MOSc-HEMT Abygaël VIEY(France) - CEA Leti, William VANDENDAELE(France) - CEA Leti, Marie-Anne JAUD(France) - CEA Leti, Jean COIGNUS(France) - CEA Leti, Jacques CLUZEL(France) - CEA Leti, Alexis

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KRAKOVINSKY(France) - CEA Leti, Simon MARTIN(France) - CEA Leti, Jérôme BISCARRAT(France) - CEA Leti, Romain GWOZIECKI(France) - CEA Leti, Veronique SOUSA(France) - CEA Leti, Fred

GAILLARD(France) - CEA Leti, Roberto MODICA(Italy) - STMicroelectronics, Catania, Ferdinando IUCOLANO(Italy) - STMicroelectronics, Catania, Matteo MENEGHINI(Italy) - University of Padova, Gaudenzio Meneghesso(Italy) - University of Padova, Gérard GHIBAUDO(France) - University Grenoble-Alpes 21st March 2021 9:25am

2C - NC

2C.1 (Focus) - TBD

Daniele Ielmini(Italy) - Politecnico di Milano 2C.2 (Focus) - TBD

Yao-feng Chang(United States) - Intel

2C.3 - Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing

Wangxin He(United States) - Arizona State University, Wonbo Shim(United States) - Georgia Institute of Technology, Shihui Yin(United States) - Arizona State University, Xiaoyu Sun(United States) - Georgia Institute of Technology, Deliang Fan(United States) - Arizona State University, Shimeng Yu(United States) - Georgia Institute of Technology, Jae-sun Seo(United States) - Arizona State University 2C.4 - Optimized programming algorithms for multilevel RRAM in hardware neural networks

Valerio Milo(Italy) - Politecnico di Milano, Francesco Anzalone(Italy) - Politecnico di Milano, Cristian Zambelli(Italy) - Università di Ferrara, Eduardo Perez(Germany) - IHP-Leibniz-Institut für innovative Mikroelektronik, Mamathamba Mahadevaiah(Germany) - IHP-Leibniz-Institut für innovative Mikroelektronik, Oscar Ossorio(Spain) - Universidad de Valladolid, Piero Olivo(Italy) - Università di Ferrara, Christian Wenger(Germany) - IHP-Leibniz-Institut für innovative Mikroelektronik, Daniele Ielmini(Italy) - Politecnico di Milano

2C.5 - CMOS-compatible MO-ECRAM Synaptic Cells : Transient Study

Paul Solomon(United States) - Ibm, Douglas Bishop(United States) - IBM Research, Teodor Todorov(United States) - Ibm, Simon Dawes(United States) - IBM Research, Damon Farmer(United States) - IBM Research, Matthew Copel(United States) - IBM Research, Ko-Tao Lee(United States) - IBM Research, John Collins(United States) - IBM Research, Tayfun Gokmen(United States) - IBM Research, John Rozen(United States) - IBM Research

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11:30am

2A - Authors' Corner

21st March 2021 11:30am

2B Authors' Corner

21st March 2021 11:30am

2C - Authors' Corner

21st March 2021 12:00pm

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21st March 2021 3:00pm

2D - Intro

Tutorial 2 - Practical Applications of Bayesian Reliability

TuT2 (Tutorial) - Practical Applications of Bayesian Reliability Yan Liu(United States) - Medtronic

Tutorial 3- Reliability Testing

TuT3 (Tutorial) - Reliability Testing Yi Zhao(China) - Zhejiang University

Tutorial 4 - 5G/mmW/RF

TuT4 (Tutorial) - 5G/mmW/RF

Fernando Guarin(United States) - GlobalFoundries, Don Gajewski(United States) - Wolfspeed

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2D - NC

2D.1 (Focus) - Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?

Runsheng Wang(China) - Peking University, Zuodong Zhang(China) - Peking University, Yawen Zhang(China) - Peking University, Yixuan Hu(China) - Peking University, Yanan Sun(China) - Shanghai Jiao Tong University, Weikang Qian(China) - Shanghai Jiao Tong University, Ru Huang(China) - Peking University

2D.2 - Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses

Ming-Liang Wei(Taiwan) - Macronix, Hussam Amrouch(Germany) - University of Stuttgart, Cheng-Lin Sung(Taiwan) - Macronix, Lue Hang-Ting(Taiwan) - Macronix, Chia-Lin Yang(Taiwan) - National Taiwan University, Keh-Chung Wang(Taiwan) - Macronix, Chih-Yuan Lu(Taiwan) - Macronix

2D.3 - Novel Weight Mapping Method for Reliable NVM based Neural Network

Lixia Han(China) - Institute of Microelectronics, Peking University, Beijing, China, Yachen Xiang(China) - Institute of Microelectronics, Peking University, Beijing, China, Peng Huang(China) - Institute of

Microelectronics, Peking University, Beijing, China, Guihai Yu(China) - Institute of Microelectronics, Peking University, Beijing, China, Runze Han(China) - Institute of Microelectronics, Peking University, Beijing, China, Xiaoyan Liu(China) - Institute of Microelectronics, Peking University, Beijing, China, Jinfeng Kang(China) - Institute of Microelectronics, Peking University, Beijing, China

2D.4 - Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories

Tommaso Zanotti(Italy) - Università di Modena e Reggio Emilia, Francesco Maria Puglisi(Italy) - Università di Modena e Reggio Emilia, Paolo Pavan(Italy) - Dipartimento di Ingegneria "Enzo Ferrari", University of Modena and Reggio Emilia, Via P. Vivarelli 10, 41125 Modena, Italy

Tutorial - Bayesian Stats Q & A

Tutorial - Reliability Testing Q & A

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Tutorial - 5G/mmW/RF Q & A

2D - Authors' Corner

Year-in-Review: Reliability Intro

Reliability Year-in-Review

Transistor - FinFET vs Nanosheet Reliability Testing

Industry Council on ESD Target Levels: Review of Achievements, Activities, and Initiatives

YIR3 (Year-in-Review) - Industry Council on ESD Target Levels: Review of Achievements, Activities, and Initiatives

Charvaka Duvvury(United States) - ESD Consulting, Harald Gossner(Germany) - Intel Corporation

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Year-in-Review: Reliability Q & A

22nd March 2021 8:00am

Keynote 2 - John Palmour, CTO Cree / Wolfspeed

KN2 (Keynote) - TBD

John Palmour(United States) - CREE & Wolfspeed 22nd March 2021 8:45am

3A - Intro

3B - Intro

Tutorial 5 - Neuromorphic Computing

TuT5 (Tutorial) - Neuromorphic Computing Brian Hoskins(United States) - NIST

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Tutorial 6 - Calculation of Terrestrial Cosmic-Ray Displacement Damage

TuT6 (Tutorial) - Calculation of Terrestrial Cosmic-Ray Displacement Damage Melanie Raine(France) - CEA, DAM, DIF, Nicolas Richard(France) - CEA, DAM, DIF

3A - PL

3A.1 - Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration

Tadeu Mota Frutuoso(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France, Jose Lugo-Alvarez(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France, Xavier Garros(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France, Laurent Brunet(France) - Univ. Grenoble Alpes, CEA, Leti, 38000 Grenoble, France, Joris Lacord(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France, Louis Gerrer(France) - Univ. Grenoble Alpes, CEA, Leti, F-F-38000 Grenoble, France, Mikael Casse(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France, Edoardo Catapano(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France, Claire Fenouillet-Beranger(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France, Francois

Andrieu(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France, Philippe Ferrari(France) - Univ. Grenoble Alpes, Grenoble INP, RFIC-Lab, 38000 Grenoble, France, Fred GAILLARD(France) - CEA Leti

3A.2 - Systematic Study of Process Impact on FinFET Reliability

Rakesh Ranjan(United States) - Samsung Austin Semiconductor, LLC, Ki-Don Lee(United States) - Samsung Austin Semiconductor, LLC

3A.3 - TDDB Reliability in Gate-All-Around Nanosheet

Huimei Zhou(United States) - IBM Reseach, Miaomiao Wang(United States) - IBM Reseach, Ruqiang Bao(United States) - IBM Reseach, Tian Shen(United States) - Ib, Ernest Wu(United States) - IBM Reseach, Richard G (Ricki) Southwick(United States) - Ib, Jingyun Zhang(United States) - Ib, Veeraraghavan Basker(United States) - IBM Reseach, Dechao Guo(United States) - IBM Reseach 3A.4 - Process-induced charging damage in IGZO nTFTs

Gaspard Hiblot(Belgium) - imec, Lieve Teugels(Belgium) - imec, Nouredine Rassoul(Belgium) - imec, Katia Devriendt(Belgium) - imec, Adrian Chasin(Belgium) - imec, Michiel van Setten(Belgium) - imec, Attilio Belmonte(Belgium) - imec, Romain Delhougne(Belgium) - imec, Gouri Kar(Belgium) - imec

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3B - 5G

3B.1 (Focus) - TBD

John Cressler(United States) - Georgia Tech 3B.2 (Focus) - TBD

Michael Dammann(Germany) - Fraunhofer Institute IAF

3B.3 - RF Reliability of SOI-based Power Amplifier FETs for mmWave 5G Applications

Purushothaman Srinivasan(United States) - GlobalFoundries, Fernando Guarin(United States) - GLOBALFOUNDRIES Inc, Shafi Syed(United States) - GLOBALFOUNDRIES Inc, Joris Angelo Sundaram Jerome(United States) - GLOBALFOUNDRIES Inc, Wen Liu(United States) - GLOBALFOUNDRIES Inc., Sameer Jain(United States) - GLOBALFOUNDRIES Inc, Dimitri Lederer(United States) -

GLOBALFOUNDRIES Inc, Stephen Moss(United States) - GLOBALFOUNDRIES Inc, Paul

Colestock(United States) - GlobalFoundries, Anirban Bandyopadhyay(United States) - GlobalFoundries, Ned Cahoon(United States) - GLOBALFOUNDRIES Inc, Byoung Min(United States) - GlobalFoundries, Martin Gall(United States) - GLOBALFOUNDRIES Inc.

3B.4 - Large Signal RF Reliability of 45-nm RFSOI Power Amplifier Cell for Wi-Fi6 Applications Aarti Rathi(India) - Indian Institute of Technology Delhi, Purushothaman Srinivasan(United States) - GlobalFoundries, Fernando Guarin(United States) - GlobalFoundries, Abhisek Dixit(India) - Indian Institute of Technology Delhi

22nd March 2021 10:30am

Tutorial 7 - Understanding and Challenges of MOL/BEOL TDDB Reliability

TuT7 (Tutorial) - Understanding and Challenges of MOL/BEOL TDDB Reliability Andrew Kim(United States) - Intel

22nd March 2021 10:30am

Tutorial 8 - GaN Reliability

TuT8 (Tutorial) - GaN Reliability

Enrico Zanoni(Italy) - University of Padova, Department of Information Engineering, Padova

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11:45am

3A - Authors' Corner

22nd March 2021 11:45am

3B - Authors' Corner

22nd March 2021 12:05pm

Break

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22nd March 2021 3:00pm

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3D Intro

3E Intro

3F - Intro

Tutorial 9 - High-k Dielectrics on Non Silicon Semiconductors

TuT9 (Tutorial) - High-k dielectrics on Non Silicon Semiconductors Chadwin Young(United States) - UT Dallas

3D-SY/SE

3D.1 (Invited) - Single Event Hard Error Due to Terrestrial Radiation

Jin-Woo Han(United States) - NASA Ames Research Center, M. Meyyappan(United States) - NASA Ames Research Center, Jungsik Kim(Korea, Republic of) - Gyeongsang National University

3D.2 - Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5 nm FinFET

Balaji Narasimham(United States) - Broadcom, Vikas Chaudhary(United States) - Broadcom, Mike Smith(United States) - Broadcom, Liming Tsau(United States) - Broadcom, Dennis Ball(United States) - Department of Electrical Engineering and Computer Science, Vanderbilt University, Bharat

Bhuva(United States) - Department of Electrical Engineering and Computer Science, Vanderbilt University

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3D.3 - Soft-Error Suseptability in Flip-Flop in EUV 7 nm Bulk-FinFET Technology

Taiki Uemura(Korea, Republic of) - Samsung Electronic, Byungjin Chung(Korea, Republic of) - Samsung Electronics, Jeongmmin Jo(Korea, Republic of) - Samsung Electronics, Seungbae Lee(Korea, Republic of) - Samsung Electronics, Hwasung Rhee(Korea, Republic of) - Samsung Electronics, Brandon Lee(Korea, Republic of) - Samsung Electronics

3D.4 - A Study on System Level UFS M-PHY Reliability Assessment Method Using RDVS NAMHYUK YANG(Korea, Republic of) - Samsung Electronic, JINHWAN KIM(Korea, Republic of) - Samsung Electronic, GEONGU PARK(Korea, Republic of) - Samsung Electronic, CHULHYUK KWON(Korea, Republic of) - Samsung Electronic, SEUNGTAEK LEE(Korea, Republic of) - Samsung Electronic, SANGWOO PAE(Korea, Republic of) - Samsung Electronic, SANGWON HWANG(Korea, Republic of) - Samsung Electronic

3D.5 - Reliability Characterization of a Flexible Interconnect for Cryogenic and Quantum Applications Emma SCHMIDGALL(United States) - Microsoft, Flavio Griggio(United States) - Microsoft, David Tuckerman(United States) - Tuckerman & Associates

3E - 5G

3E.1 (Focus) - TBD

Purushothaman Srinivasan(United States) - GlobalFoundries 3E.2 (Focus) - TBD

John R. Scarpulla(United States) - The Aerospace Corporation

3E.3 - On the impact of buffer and GaN-channel thickness on current dispersion for GaN-on-Si RF/mmWave devices

Vamsi Putcha(Belgium) - imec, Liang Cheng(China) - Nanjing University, AliReza Alian(Belgium) - imec, Ming Zhao(Belgium) - imec, Hai Lu(China) - Nanjing University, Bertrand Parvais(Belgium) - imec / Vrije Universiteit Brussel, Niamh Waldron(Belgium) - imec, Dimitri Linten(Belgium) - imec, Nadine

Collaert(Belgium) - imec

3E.4 - Role of the AlGaN Cap Layer on the Trapping Behaviour of N-Polar GaN MISHEMTs

Francesca Chiocchetta(Italy) - University of Padova, Department of Information Engineering, Padova, Claudia Calascione(Italy) - University of Padova, Department of Information Engineering, Padova, Carlo de Santi(Italy) - University of Padova, Chandan Sharma(Italy) - University of Padova, Fabiana

Rampazzo(Italy) - University of Padova, Xun Zheng(United States) - University of California Santa Barbara, Brian Romanczyk(United States) - University of California Santa Barbara, Matt Guidry(United States) - University of California Santa Barbara, Haoran Li(United States) - University of California Santa Barbara, Stacia Keller(United States) - University of California Santa Barbara, Umesh Mishra(United

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States) - University of California Santa Barbara, Gaudenzio Meneghesso(Italy) - University of Padova, Matteo Meneghini(Italy) - University of Padova, Department of Information Engineering, Padova, Enrico Zanoni(Italy) - University of Padova, Department of Information Engineering, Padova

3F - MB

3F.1 (Invited) - Back End Of Line Opportunities and Reliability Challenges for Future Technology Nodes Mauro Kobrinsky(United States) - Intel Corporation

3F.2 - Reliability of DME Ru Semidamascene with 16 nm wide Airgaps

Alicja Lesniewska(Belgium) - imec, Olalla Varela Pedreira(Belgium) - imec, Melina Lofrano(Belgium) - imec, Gayle Murdoch(Belgium) - imec, Marleen van der Veen(Belgium) - imec, Anish Dangol(Belgium) - imec, Naoto Horiguchi(Belgium) - imec, Zsolt Tokei(Belgium) - imec, Kristof Croes(Belgium) - imec 3F.3 - Electromigration Limits of Copper Nano-Interconnects

Houman Zahedmanesh(Belgium) - imec, Olalla Varela Pedreira(Belgium) - imec, Zsolt Tokei(Belgium) - imec, Kristof Croes(Belgium) - imec

3F.4 - Intrinsic Reliability of BEOL Interlayer Dielectric

James Palmer(United States) - Intel Corporation, Galor Zhang(United States) - Intel Corporation, Justin Weber(United States) - Intel Corporation, Che-yun Lin(United States) - Intel Corporation, Christopher Perini(United States) - Intel Corporation, Rahim Kasim(United States) - Intel Corporation

3F.5 - Strategy to Characterize Electromigration Short Length Effects in Cu/low-k Interconnects Zhenjun Zhang(United States) - GlobalFoundries, Matthias Kraatz(Germany) - Fraunhofer IKTS, Meike Hauschildt(United States) - GLOBALFOUNDRIES Inc., Seungman Choi(United States) -

GLOBALFOUNDRIES Inc., Andre Clausner(United States) - Fraunhofer IKTS, Ehrenfried Zschech(Germany) - Fraunhofer IKTS, Martin Gall(United States) - GLOBALFOUNDRIES Inc.

Tutorial 10 - Advanced 3D Flash Memory Architectures

TuT10 (Tutorial) - Advanced 3D Flash Memory Architectures Lue Hang-Ting(Taiwan) - Macronix

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3D - Authors' Corner

3E - Authors' Corner

3F - Authors' Corner

3G Intro

3H - Intro

3I - Intro

22nd March 2021

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5:35pm

3G - PR/ESD

3G.1 - Product Lifetime Estimation in 7nm with Large data of Failure Rate and Si-Based Thermal Coupling Model

Jae-Gyung Ahn(United States) - Xilinx, Inc., Rhesa Nathanael(United States) - Xilinx, Inc., I-Ru Chen(United States) - Xilinx, Inc., Ping-Chin Yeh(United States) - Xilinx, Inc., Jonathan Chang(United States) - Xilinx, Inc.

3G.2 - Considerations in High Voltage Lateral ESD PNP Design

Milan Shah(United States) - University of Illinois at Urbana-Champaign, Yujie Zhou(United States) - University of Illinois at Urbana-Champaign, David LaFonteese(United States) - Texas Instruments, Elyse Rosenbaum(United States) - University of Illinois at Urbana-Champaign

3G.3 - Compact Model of ESD Diode Suitable for Sub-nanosecond Switching Transients

Shudong Huang(United States) - University of Illinois at Urbana-Champaign, Elyse Rosenbaum(United States) - University of Illinois at Urbana-Champaign

3H - MY

3H.1 (Invited) - TBD

Kazunari Ishimaru(Japan) - Kioxia

3H.2 - Reliability of Mo as Word Line Metal in 3D NAND

Davide Tierno(Belgium) - imec, Kristof Croes(Belgium) - imec, Arjun Ajaykumar(Belgium) - imec, Siva Ramesh(Belgium) - imec, Geert Van den Bosch(Belgium) - imec, Maarten Rosmeulen(Belgium) - imec 3H.3 - Effect of High Temperature on Recovery of Hot Carrier Degradation of scaled nMOSFETs in DRAM Donghee Son(Korea, Republic of) - Samsung Electronic, Gang-jun Kim(Korea, Republic of) - Samsung Electronic, Jongkyun kim(Korea, Republic of) - Samsung Electronic, Nam-Hyun Lee(Korea, Republic of) - Samsung Electronic, Kijin Kim(Korea, Republic of) - Samsung Electronic, SANGWOO PAE(Korea,

Republic of) - Samsung Electronic

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3I - MB

3I.1 - Moisture diffusion rate in an ultra-low-k dielectric and its effect on the dielectric reliability Ning Duan(Netherlands) - NXP Semiconductors, Vignesh Subramanian(Netherlands) - NXP

Semiconductors, Edgar Olthof(Netherlands) - NXP Semiconductors, Paul Eggenkamp(Netherlands) - NXP Semiconductors, Richard Braspenning(Netherlands) - NXP Semiconductors

Tutorial 11 - Magnetic Resonance Techniques for Electronic Materials

TuT11 (Tutorial) - Magnetic Resonance Techniques for Electronic Materials Mark Anders(United States) - NIST

3G - Authors' Corner

3H - Authors' Corner

3I - Authors' Corner

23rd March 2021 8:00am

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Keynote 3 - Peter Gammel, CTO MWI at Global Foundries

KN3 (Keynote) - Laying the Groundwork for 6G communications Peter Gammel(United States) - GlobalFoundries

4A - Intro

4B - Session Intro

Tutorial 12 - DRAM Reliability Overview

TuT12 (Tutorial) - DRAM Reliability Overview

Hokyung Park(Korea, Republic of) - SK Hynix, Seongwan Ryu(Korea, Republic of) - SK Hynix

Tutorial 13 - Hot Carrier Degradation in Si Devices – From Experimental

Observations to Accurate Physical Modeling

TuT13 (Tutorial) - Hot-carrier Degradation in Si Devices – from Experimental Observations to Accurate Physical Modeling

Stanislav Tyaginov(Belgium) - imec / TU Wien / Ioffe Institute

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8:50am

4A - CR

4A.1 (Invited) - Silicon Lifecycle Management with On-chip Monitoring Rajesh Kashyap(United States) - Synopsys

4A.2 - Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies

Gerhard Rzepa(Austria) - Global TCAD Solutions, Markus Karner(Austria) - Global TCAD Solutions, Oskar Baumgartner(Austria) - Global TCAD Solutions, Georg Strof(Austria) - Global TCAD Solutions, Franz Schanovsky(Austria) - Global TCAD Solutions, Ferdinand Mitterbauer(Austria) - Global TCAD Solutions, Christian Kernstock(Austria) - Global TCAD Solutions, Hui-Wen Karner(Austria) - Global TCAD Solutions, Pieter Weckx(Belgium) - imec, Geert Hellings(Belgium) - im, Dieter Claes(Belgium) - imec, Zhicheng Wu(Belgium) - imec / KU Leuven, Yang Xiang(Belgium) - imec / KU Leuven, Thomas Chiarella(Belgium) - imec, Bertrand Parvais(Belgium) - imec / Vrije Universiteit Brussel, Jerome Mitard(Belgium) - imec, Jacopo Franco(Belgium) - imec, Ben Kaczer(Belgium) - imec, Dimitri Linten(Belgium) - imec, Zlatan Stanojevic(Austria) - Global TCAD Solutions

4A.3 - An All BTI (N-PBTI, N-NBTI, P-PBTI, P-NBTI) Odometer based on a Dual Power Rail Ring Oscillator Array

Gyusung Park(United States) - University of Minnesota, Twin Cities, Hanzhao Yu(United States) - University of Minnesota, Twin Cities, Minsu Kim(United States) - University of Minnesota, Twin Cities, Chris H. Kim(United States) - University of Minnesota, Twin Cities

4A.4 - A BSIM-Based Predictive Hot-Carrier Aging Compact Model

Yang Xiang(Belgium) - imec / KU Leuven, Stanislav Tyaginov(Belgium) - imec / TU Wien / Ioffe Institute, Michiel Vandemaele(Belgium) - imec / KU Leuven, Zhicheng Wu(Belgium) - imec / KU Leuven, Jacopo Franco(Belgium) - imec, Erik Bury(Belgium) - imec, Brecht Truijen(Belgium) - imec, Bertrand

Parvais(Belgium) - imec / Vrije Universiteit Brussel, Dimitri Linten(Belgium) - imec, Ben Kaczer(Belgium) - imec

4A.5 - Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm Subrat Mishra(Belgium) - imec, Pieter Weckx(Belgium) - imec, Odysseas Zografos(Belgium) - imec, Ji-Yung Lin(Belgium) - imec / KU Leuven, Alessio Spessot(Belgium) - imec, Francky Catthoor(Belgium) - imec

4A.6 - Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65~nm Fully Depleted Silicon-On-Insulator Process

Ryo Kishida(Japan) - Tokyo University of Science, Ikuo Suda(Japan) - Kyoto Institute of Technology, Kazutoshi Kobayashi(Japan) - Kyoto Institute of Technology

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8:50am

4B - RT

4B.1 - Dielectric Relaxation, Aging and Recovery in HiK MIM Capacitors

Konner Holden(United States) - Oregon State University, Gavin Hall(United States) - ON Semiconductor, Michael Cook(United States) - ON Semiconductor, Chris Kendrick(United States) - ON Semiconductor, Kaitlyn Pabst(United States) - ON Semiconductor, Bruce Greenwood(United States) - ON

Semiconductor, Robin Daugherty(United States) - ON Semiconductor, Jeff Gambino(United States) - ON Semiconductor, Derryl Allman(United States) - ON Semiconductor

4B.2 - A Fast DCIV Technique for Characterizing the Generation and Repassivation of Interface Traps Under DC/AC NBTI Stress/Recovery Condition in Si p-FinFETs

Longda Zhou(China) - Institute of Microelectronics, Chinese Academy of Science, Zhaohao

Zhang(China) - Institute of Microelectronics, Chinese Academy of Science, Hong Yang(China) - Institute of Microelectronics, Chinese Academy of Science, Zhigang Ji(China) - Shanghai Jiaotong University, Qianqian Liu(China) - Institute of Microelectronics, Chinese Academy of Science, Qingzhu Zhang(China) - Institute of Microelectronics, Chinese Academy of Science, Eddy Simoen(Belgium) - imec / TU Wien /, Huaxiang Yin(China) - Institute of Microelectronics, Chinese Academy of Science, Jun Luo(China) - Institute of Microelectronics, Chinese Academy of Science, Anyan Du(China) - Institute of

Microelectronics, Chinese Academy of Science, Chao Zhao(China) - Institute of Microelectronics, Chinese Academy of Science, Wenwu Wang(China) - Institute of Microelectronics, Chinese Academy of Science

4B.3 - Time-Efficient Characterization of Time-Dependent Gate Oxide Breakdwon Using Tunable Ramp Voltage Stress (TRVS) Method for Automotive Applications

Shih-che Hung(Taiwan) - Technology Quality and Reliability Department, Taiwan Semiconductor Manufacturing Company (TSMC), Shih-Chang Chen(Taiwan) - Technology Quality and Reliability Department, Taiwan Semiconductor Manufacturing Company (TSMC), Pei-Shan Chien(Taiwan) - Technology Quality and Reliability Department, Taiwan Semiconductor Manufacturing Company (TSMC), Yu-Sheng Cho(Taiwan) - Technology Quality and Reliability Department, Taiwan Semiconductor Manufacturing Company (TSMC), Y.-H. Lee(United States) - Technology Quality and Reliability

Department, Taiwan Semiconductor Manufacturing Company (TSMC), Wei-Shuo Hung(Taiwan) -

Technology Quality and Reliability Department, Taiwan Semiconductor Manufacturing Company (TSMC) 4B.4 - Evaluation methodology for assessment of dielectric degradation and breakdown dynamics using time-dependent impedance spectroscopy (TDIS)

Tomohiro Kuyama(Japan) - Kyoto University, Keiichiro Urabe(Japan) - Kyoto University, Koji Eriguchi(Japan) - Kyoto University

23rd March 2021 10:30am

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Tutorial 14 - Metal Reliability for Advanced Interconnects

TuT14 (Tutorial) - Metal reliability for advanced interconnects Olalla Varela Pedreira(Belgium) - imec

23rd March 2021 10:30am

Tutorial 15 - Application and Characterization of CMOS Cryogenic Electronics

TuT15 (Tutorial) - Application and characterization of CMOS cryogenic electronics Pragya Shrestha(United States) - NIST

23rd March 2021 11:45am

4A - Authors' Corner

23rd March 2021 11:45am

4B - Authors' Corner

23rd March 2021 12:05pm

Break

23rd March 2021 12:05pm

Break

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23rd March 2021 12:05pm

Break

23rd March 2021 3:00pm

4D - Intro

4E - Intro

Tutorial 16 - Reliability and Performance Limiting Defects in 4H SiC Metal

Oxide Semiconductor Field Effect Transistors

TuT16 (Tutorial) - Reliability and Performance Limiting Defects in 4H SiC Metal Oxide Semiconductor Field Effect Transistors

Pat Lenahan(United States) - Penn State

Tutorial 17 - Automotive

TuT17 (Tutorial) - Automotive

Andreas Aal(Germany) - Volkswagen, Oliver Aubel(United States) - GlobalFoundries

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3:05pm

4D - PK

4D.1 (Invited) - Reliability of Optoelectronic Module: An overview John Osenbach(United States) - Infinera

4D.2 - Excellent Reliability of XtackingTM Bonding Interface

Alex Yang(China) - Yangtze Memory Technologies Co., Ltd., Yan Ouyang(China) - Yangtze Memory Technologies Co., Ltd.

4D.3 - Reliability of Wafer-Level Ultra-Thinning down to 3 μm using 20 nm-Node DRAMs Zhiwen Chen(Japan) - Tokyo Institute of Technology, Youngsuk Kim(Japan) - Tokyo Institute of

Technology, Tadashi Fukuda(Japan) - Tokyo Institute of Technology, Koji Sakui(Japan) - Tokyo Institute of Technology, Tatsuji Kobayashi(Japan) - Micron Memory Japan, Takashi Obara(Japan) - Micron Memory Japan, Takayuki Ohba(Japan) - Tokyo Institute of Technology

4D.4 - Chip to Package Interaction Risk Assessment of FCBGA Devices using FEA Simulation, Meta-modeling and Genetic Algorithm Optimization Technique

Moon Soo Lee(Korea, Republic of) - Samsung Electronic, In-hak Baick(Korea, Republic of) - Samsung Electronic, Min Kim(Korea, Republic of) - Samsung Electronic, So Hyun Kwon(Korea, Republic of) - Samsung Electronic, Myeong Soo Yeo(Korea, Republic of) - Samsung Electronic, Hwasung Rhee(Korea, Republic of) - Samsung Electronics, Euncheol Lee(Korea, Republic of) - Samsung Electronics

4E - RT

4E.1 - Charge pumping source-drain current for gate oxide interface trap density in MOSFETs

Jifa Hao(United States) - ON Semiconductor, Yuhang Sun(United States) - ON Semiconductor, Amartya Ghosh(United States) - ON Semiconductor

4E.2 - A Novel Charge Pumping Technique to Quantify Region-Specific Interface Defects leading to Hot Carrier Degradation in LDMOS

Bikram Mahajan(United States) - Purdue University, Yen-Pu Chen(United States) - Purdue University, Dhanoop Varghese(United States) - Texas Instruments, Vijay Reddy(United States) - Texas Instruments, Srikanth Krishnan(United States) - Texas Instruments, Muhammad Ashraful Alam(United States) - Purdue University

4E.3 - Nanosecond scale transistor characterization using signal reflection

Wei Liu(China) - Zhejiang University, Yaru Ding(China) - Zhejiang University, Yi Zhao(China) - Zhejiang University

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4E.4 - Machine Learning On Transistor Aging Data: Test Time Reduction and Modeling for Novel Devices Neel Chatterjee(United States) - Electrical and Computer Engineering, University of Minnesota, John Ortega(United States) - Intel Corporation, Inanc Meric(United States) - Intel Corporation, Peng Xiao(United States) - Intel Corporation, Ilan Tsameret(United States) - Intel Corporation 23rd March 2021 4:45pm

4d - Authors' Corner

4E - Authors' Corner

WS - Device Reliability

Xavier Federspiel (France) - STmicroe

Souvik Mahapatra (India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay)

Workshop on BTI and HCD

Bias Temperature Instability (BTI) continues to remain as a crucial reliability concern in CMOS devices. Although it comes in two variants – Negative BTI (NBTI) in PMOS and Positive BTI (PBTI) in NMOS, modern devices with Replacement Metal Gate (RMG) based High-K Metal Gate (HKMG) processes primarily suffers from NBTI while PBTI is negligible.

The physics of NBTI has remained debated, although any model should be able to explain different experiments (as follows) in order to qualify as something meaningful:

• Time kinetics of NBTI during (stress) and after (recovery) DC and AC stress at multiple gate bias (VG) and temperature (T) – preferably T range covering space to automotive applications, and AC stress at multiple duty cycle and frequency.

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• Impact of different processes, such as Nitrogen in gate stack, Germanium in channel, device dimension (e.g. fin length/width), layout, etc., on the time kinetics, Vg and T dependence.

However, from a qualification viewpoint, simple empirical models are sufficient to benchmark foundries or process recipes, although care should be taken that the stress and use conditions are not much different to project to operating conditions. Physical models can provide better estimation of end-of-life NBTI.

Hot Carrier Degradation (HCD) depends on channel length (LCH), drain bias (VD) and ratio of drain to gate bias (VD/VG). Classical worst-case projections approaches, such as mid VG (I/O devices or nodes >90nm) or VG=VD (node <90nm) might be sufficient for foundries or process benchmark. However, accurate aging model dedicated to circuit simulation might require refined models taking into account complex VG dependencies, HCD-BTI interaction as well as self-heating effects. As a matter of fact, the BTI-HCD interaction can become a crucial issue especially for PMOS devices, if qualification is done at VG=VD condition, and the situation can get exacerbated due to self-heating effect in modern devices (FDSOI, FinFET, GAA NSFET) with confined channels.

This workshop would focus on the following: • Overview of BTI mechanism (~15 mins)

• Overview of HCD mechanism in high and low voltage devices (~20 mins) • Qualification / test methodologies for HCD and BTI (~ 25 mins)

• Choice of stress bias (VG/VD condition) and AC-DC factor • Decoupling of BTI and HCD

• Impact of self-heating effect (DC vs. AC stress)

WS - SSD Memory

Nikolaos Papandreou - Ibm

Jay Sarkar (United States) - Miicron Technologies

Brief Summary: Advances in 3D NAND enable endurance gains, capacity increase, lower power consumption and cost reduction, thus making SSD technology attractive for new applications such as AI and cloud computing. At the same time, 3D NAND exhibits new reliability challenges that affect both the resiliency and performance at the system level, e.g., increased number of bit errors, threshold voltage instabilities, frequent read retries, higher read latency, etc. To cope with these issues, modern NAND controller architectures become complex. Resilient FW/HW co-design is critical to ensure the reliability and performance requirements of modern SSDs. Machine learning can aid by offering a valuable tool for prediction and anomaly detection. Analytics together with domain knowledge can

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provide valuable insights of failure modes and error events relevant to system reliability. On the other hand, blind application of machine learning algorithms can lead to pitfalls. Representative datasets for training, models that provide interpretability and repeatability of the results are key enablers in this quest.

This workshop will discuss the reliability challenges of modern SSDs and the requirements for new applications such as AI, cloud or edge computing. Another intent is to discuss the role of machine learning and analytics in improving the resiliency of modern SSDs through accurate prognostics and prediction.

WS - BEOL

Ki-Don Lee (United States) - Samsung Austin Semiconductor, LLC Gavin Hall (United States) - ON Semiconductor

Background

Since the introduction of dual-damascene Cu and low-k dielectric materials, there has been continuous device scaling from 130nm down to 7nm (and beyond) during the last two decades. Numerous

innovations in materials, processes, and models have enabled the new technology node successful and reliable, thanks to the efforts of our fellow scientists and engineers. In this year’s IRPS, more

innovations are happening, as we have seen papers on Ru interconnects and 7nm EUV Co-liner Cu interconnects.

Today, BEOL reliability evaluation includes electromigration (EM), stress-induced voiding (SV/SIV/SM) and time-dependent dielectric breakdown (TDDB). Looking forward, we must also include

environmental factors and more extreme use cases of current and thermally induced inelastic behavior of interconnects under various loadings. How do we incorporate these into an accelerated test

framework, in both modeling and verification?

Regarding materials, it is key to understand intrinsic and extrinsic size effects – e.g. linewidths, networks, grain boundaries, twins, and texture - and how these relate to stress and the inelastic response. How do we measure and understand these effects and what technological impact do they have? What are the impacts of mechanical response of next generation materials - Ru, Co, alloys, and barrier integrations, etc. – on the reliability, and how do we measure these?

Attendants are invited to discuss their experiences and experiments in metallization, as well as diagnostic and physical/electrical failure analysis techniques that have helped develop their

understanding. Additionally, we would like to discuss the pros and cons of fast test methods available, like wafer-level EM, TVS, isothermal EM, and others for rapid learning cycles in development.

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Discussion Topics

• Ru Interconnect / 7nm EUV Co-liner Cu interconnects.

• BEOL challenges for 5nm and beyond (Roadmap for RC delay) • EM Short Length effect (Blech) in 7nm and below.

• Model selection for BEOL TDDB.

• BEOL reliability of power devices, and heterogeneously integrated solutions • Metal fatigue in microelectronics

• Physical and electrical evaluations • Reliability methodology & test

WS - Wide Band Gap GaN

Shireen Warnock - MIT

Matteo Meneghini (Italy) - University of Padova

Brief summary: GaN is an excellent material for the fabrication of power transistors. These devices are now rapidly finding applications in next‐generation power conversion systems with 600‐

650V transistors already commercially available. Higher voltages are currently targeted (up to 1.2 kV). The success of GaN depends on the understanding of key failure modes and mechanisms. A

market transformation is now underway, and the next step is to demonstrate and qualify high reliability. This workshop focuses on the hot topics in the field of GaN reliability:

1. What are the largest remaining barriers to widespread commercial adoption?

2. Soft vs. Hard switching: What's new? How do you qualify devices in a dynamic regime? 3. GaN devices do not have avalanche capability—Is this a problem or an opportunity? 4. Extrinsic vs. Intrinsic reliability: What are the biggest challenges?

This workshop will address these questions by stimulating discussion on the issues that presently limit the reliability and performance of GaN‐based HEMTs. It will be a natural lead‐in for the subsequent workshop on SiC reliability.

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WS - Neuromorphic

Gennadi Bersuker (United States) - The Aerospace Corporation Marinella Matthew

Kin Leong Pey (Singapore) - Singapore University of Technology and Design

WS: HV Transient IEC ESD Design Challenges

Raj Sankaralingam - Texas Instruments Alan Righter (United States) - Analog Devices 23rd March 2021 5:55pm

Break

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Break

WS - Circuit Reliability and Aging: Measurements and Simulations

Valeriy Sukharev - Mentor Georgios Konstadinidis - Google

Brief summary: In order to determine the chip performance for a given set of design rules, operating voltage and switching speeds, the reliability must be accounted for specific operating conditions. The question is how to account it in right and most effective way. Should we employ the formal approach treating the circuitry as a sequence of elements characterized by

known rates of failures, which are traditionally based on the lab data? Or, should we employ more physics-based description of the failure mechanism of the circuitry as a system in the specific environment?

This workshop focuses on the hot topics in the field of circuit reliability:

1. What has been accomplished so far and what should be the path moving forward? 2. ML based approaches are being explored to establish that. Is this the right approach? 3. Are in situ measurements more appropriate to calibrate the models and close the loop?

4. What is the best approach in addressing the extra challenges coming with 3D integration like thermal and mechanical CPI issues to the whole complexity?

5. How to design a chip with a required functionality and performance while satisfying the intended lifetime of the product?

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WS - Emerging Memory

Joe McCrate - Micron Technology

Tetsuo Endoh (Japan) - Tohoku University

WS - Automotive for In-car Safety and Security

Riccardo Mariani - Nvidia

Udeerna Doppalapudi - Qualcomm

WS - Wide Band Gap SiC

Aivars Lelis - J CIV USARMY

Thomas Aichinger (Austria) - Infineon Technologies Austria AG

Brief summary: The strong push to maximize performance to demonstrate the superiority of SiC technology vis-à-vis Si has in some cases increased the significance of potential reliability issues. One particular case where this has occurred is in the short-circuit rating of SiC power

MOSFETs. Continual decreases in on-state resistance by varying design parameters such as channel length make these devices more susceptible to failure during a short-circuit event since the

saturation current, along with the bus voltage, determines the power dissipation that occurs, which in turn determines how quickly the internal temperature rises to a critical value at which Al begins to melt, or other failure mechanisms begin to engage. This workshop will focus on short-circuit reliability in SiC MOSFETs. A list of topics includes failure mechanisms, test methods, trade-offs

between performance and reliability, and where the burden for short-circuit protection should lie. Discussion topics include:

• Brief overview of failure mechanisms.

• Difference in short-circuit behavior between silicon and SiC power devices. • Brief overview of test methods used.

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• Proposals on how to improve device design to reduce susceptibility to short-circuit fault conditions. • What is an appropriate short-circuit withstand time for industry acceptance?

• Should the burden be on the device designer or the circuit designer?

• Is short-circuit withstand capability required by the circuit designer; or are device designers trying to match the inherent short-circuit performance of Si devices?

• Need for different trade-off points between performance and reliability, depending on the application.

WS - RF/mmW/5G

Fernando Guarin (United States) - GlobalFoundries Farid Medjdoub (France)

Background

Given the power, cost structure and integration required for mmW 5G deployment, what gaps remain for Silicon and SiGe to be viable solutions? The market for cellphones, Base Stations and IoT solutions is predicted to explode in the near future. Many companies are in the process of designing their mmW solutions for 5G. In this session we will review the most likely technologies that will dominate the sizable 5G market. Most key players in the industry realize that there is a sizable opportunity for Si and SiGe technology solutions as we transition from the few antennas required in 4G to the multi element antenna array solutions, hence the power requirements have been reduced to a range that is well suited for Silicon and Silicon Germanium technology offerings. Will this be sufficient to displace the proven and well-entrenched RF mmW solutions offered by III-V?

Which solution will win in the market from the perspective of? • Power

• Cost / Integration • Reliability

• Operating lifetime requirements

– EOL, should it be 10 years, 3 years, X years? • Duty cycle 100%?

• Power requirements for 5G (Linearity/Efficiency) (Handsets and Basestations)

• Translating reliability behavior from device to circuit level – what matters to the end users? – Reliability simulator requirements

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• Appropriate methods for testing and characterizing RF reliability? – Circuit benchmarks, PA, LNA, and Switches

• Scaled DC measurements

• o Setting up device level tests to accurately reflect circuit level benchmarks – Associated impact for various classes of circuits/IP blocks. • Thermal

– TCAD modeling • Self-heating

• simulation vs. practical usage Discussion Topics

• Operating lifetime requirements

– EOL, should it be 10 years, 3 years, X years? • Duty cycle 100%?

• Power requirements for 5G (Linearity/Efficiency) (Handsets and Basestations)

• Translating reliability behavior from device to circuit level – what matters to the end users? – Reliability simulator requirements

• Appropriate methods for testing and characterizing RF reliability? – Circuit benchmarks, PA, LNA, and Switches

• Scaled DC measurements

• o Setting up device level tests to accurately reflect circuit level benchmarks – Associated impact for various classes of circuits/IP blocks. • Thermal

– TCAD modeling • Self-heating

• simulation vs. practical usage

24th March 2021 8:00am

Keynote 4 - Allessandro Piovaccari, Silicon Labs

KN4 (Keynote) - IoT End-node Device: Built to Last Alessandro Piovaccari(United States) - Silicon Labs

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5A - Intro

5B - Intro

5C - Intro

Tutorial 18 - Electronic Design Automation (EDA) Solutions for Latch-up

Verification in CMOS and HV Technologies

TuT18 (Tutorial) - Electronic Design Automation (EDA) Solutions for Latch-up Verification in CMOS and HV Technologies

Michael Khazhinsky(United States) - Silicon Labs

5A - TX

5A.2 - CV Stretch-Out Correction after Bias Temperature Stress: Workfunction Dependence of Donor-/Acceptor-like Traps, Fixed Charges, and Fast States

Tibor Grasser(Austria) - TU Wien, Barry O'Sullivan(Belgium) - imec, Ben Kaczer(Belgium) - imec, Jacopo Franco(Belgium) - imec, Bernhard Stampfer(Austria) - TU Wien, Michael Waltl(Austria) - TU Wien 5A.3 - Physics-based device aging modelling framework for accurate circuit reliability assessment Zhicheng Wu(Belgium) - imec / KU Leuven, Jacopo Franco(Belgium) - imec, Brecht Truijen(Belgium) - imec, Philippe Roussel(Belgium) - imec, Stanislav Tyaginov(Belgium) - imec / TU Wien / Ioffe Institute,

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Michiel Vandemaele(Belgium) - imec / KU Leuven, Erik Bury(Belgium) - imec, Guido

Groeseneken(Belgium) - imec / KU Leuven, Dimitri Linten(Belgium) - imec, Ben Kaczer(Belgium) - imec 5A.4 - Variability sources and reliability of 3D - FeFETs

Milan Pesic(United States) - Applied Materials, Bastien Beltrando(Italy) - Applied Materials, Andrea Padovani(Italy) - Applied Materials, Shruba Gangopadhyay(United States) - Applied Materials, Muthukumar Kaliappan(United States) - applied, Michael Haverty(United States) - Applied Materials, Jack Strand(United Kingdom) - University College London, Alexander Shluger(United Kingdom) - University College London, Marco Villena(Italy) - Applied Materials, Enrico Piccinini(Italy) - Applied Materials, Matteo Bertocchi(Italy) - Applied Materials, Tony Chiang(Italy) - Applied Materials, Luca Larcher(Italy) - Applied Materials

5A.5 - Time Dependent Variability in Advanced FinFET Technology for End-of-lifetime Reliability Prediction

Hai Jiang(Korea, Republic of) - Samsung Electronics, Jinju Kim(Korea, Republic of) - Samsung

Electronics, Kihyun Choi(Korea, Republic of) - Samsung Electronics, Hyewon Shim(Korea, Republic of) - Samsung Electronics, Hyunchul Sagong(Korea, Republic of) - Samsung Electronics, Junekyun

Park(Korea, Republic of) - Samsung Electronics, Hwasung Rhee(Korea, Republic of) - Samsung Electronics, Euncheol Lee(Korea, Republic of) - Samsung Electronics

5A.6 - Analysis of Sheet Dimension (W, L) Dependence of NBTI in GAA-SNS FETs

Nilotpal Choudhury(India) - Department of Electrical Engineering, Indian Institute of Technology

Bombay (IIT Bombay), Tarun Samadder(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay), Ravi Tiwari(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay), Huimei Zhou(United States) - IBM Research, Richard G (Ricki) Southwick(United States) - IBM Research, Miaomiao Wang(United States) - IBM Research, Souvik Mahapatra(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay)

5A.7 - The properties, effect and extraction of localized defect profiles from degraded FET characteristics

Michiel Vandemaele(Belgium) - imec / KU Leuven, Ben Kaczer(Belgium) - imec, Stanislav Tyaginov(Belgium) - imec / TU Wien / Ioffe Institute, Jacopo Franco(Belgium) - imec, Robin

Degraeve(Belgium) - imec, Adrian Chasin(Belgium) - imec, Zhicheng Wu(Belgium) - imec / KU Leuven, Erik Bury(Belgium) - imec, Yang Xiang(Belgium) - imec / KU Leuven, Hans Mertens(Belgium) - imec, Guido Groeseneken(Belgium) - imec / KU Leuven

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5B - EM

5B.1 (Focus) - Reliability of STT-MRAM for Various Embedded Applications Shinhee Han(Korea, Republic of) - Samsung Electronic

5B.2 (Focus) - TBD

Shy-Jay Lin(Taiwan) - TSMC 5B.3 (Focus) - TBD

Seung H. Kang(United States) - Qualcomm

5B.4 - BEOL-compatible scaled STT-MRAM pillar edge-induced reliability & performance degradation: an etch engineering solution

Simon Van Beek(Belgium) - imec, Siddharth Rao(Belgium) - imec, Woojin Kim(Belgium) - imec, Shreya Kundu(Belgium) - imec, Barry O'Sullivan(Belgium) - imec, Stefan Cosemans(Belgium) - imec, Farrukh Yasin(Belgium) - imec, Robert Carpenter(Belgium) - imec, Sebastien Couet(Belgium) - imec, Shamin Sharifi(Belgium) - imec, Nico Jossart(Belgium) - imec, Davide Crotti(Belgium) - imec, Gouri

Kar(Belgium) - imec 24th March 2021 8:50am

5C - SiC

5C.1 (Invited) - TBD

Jean-Marie Lauenstein(United States) - nasa 5C.2 (Invited) - TBD

Neyer Neyer(Germany) - ON Semiconductor

5C.2 - Correlation between 4H-SiC epitaxial defects and MOSFETs breakdown

Patrick Fiorenza(Italy) - CNR-IMM, Salvatore Adamo(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Mario Santo Alessandrino(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Cettina Bottari(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Beatrice Carbone(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Clarice Di Martino(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Alfio Russo(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Mario Saggio(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Carlo Venuto(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Elisa Vitanza(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Edoardo Zanetti(Italy) - STMicroelectronics, Stradale Primosole 50, 95121 Catania,, Filippo Giannazzo(Italy) - CNR-IMM, Fabrizio Roccaforte(Italy) - CNR-IMM

5C.3 - A straightforward electrical method to determine screening capability of GOX extrinsics in arbitrary, commercially available SiC MOSFETs

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Judith Berens(Austria) - Infineon Technologies Austria AG, Thomas Aichinger(Austria) - Infineon Technologies Austria AG

5C.4 - Early Breakdown of SiC MOSFET Gate Oxide Characterized by Voltage Ramp Tests

Yongju Zheng(United States) - SemiQ Inc, Rahul Potera(United States) - SemiQ Inc, Tony Witt(United States) - SemiQ Inc

5C.6 - A new test procedure to realistically estimate end-of-life electrical parameter stability of SiC MOSFETs in switching operation

Paul Salmen(Germany) - Infineon Technologies AG, Maximilian W. Feil(Germany) - Infineon

Technologies AG, Katja Waschneck(Germany) - Infineon Technologies AG, Hans Reisinger(Germany) - Infineon Technologies AG, Gerald Rescher(Austria) - Infineon Technologies Austria AG, Thomas Aichinger(Austria) - Infineon Technologies Austria AG

5C.7 - Investigation of Gate Leakage Current Behavior for Commercial 1.2 kV 4H-SiC Power MOSFETs Shengnan Zhu(United States) - The Ohio State University, Tianshi Liu(United States) - The Ohio State University, Marvin White(United States) - The Ohio State University, Arash Salemi(United States) - Alpha and Omega Semiconductor, David Sheridan(United States) - Alpha and Omega Semiconductor, Anant Agarwal(United States) - The Ohio State University

24th March 2021 10:30am

Tutorial 19 - EOS, ESD, Transient, AMR, EIPD, Robustness, Aging - Do All of

These Pieces go to the Same Puzzle?

TuT19 (Tutorial) - EOS, ESD, Transient, AMR, EIPD, Robustness, Aging - Do All of These Pieces go to the Same Puzzle?

Hans Kunz(United States) - Texas Instruments 24th March 2021 11:45am

5A - Authors' Corner

24th March 2021 11:45am

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5B - Authors' Corner

24th March 2021 11:45am

5C - Authors' Corner

24th March 2021 12:05pm

Break

24th March 2021 12:05pm

Break

24th March 2021 3:00pm

5D - Intro

Tutorial 20 - Exploring Relation of ESD and EMC: Tests, Events to Damage,

Failure Types, and Co-Design Approaches

TuT20 (Tutorial) - Exploring Relation of ESD and EMC: Tests, Events to Damage, Failure Types, and Co-Design Approaches

Alan Righter(United States) - Analog Devices

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Tutorial 21 - FinFET Self-heating: Measurements, Concerns and Applications

TuT21 (Tutorial) - FinFET Self-heating: Measurements, Concerns and Applications Zakariae Chbili(United States) - Intel

5D - EM

5D.1 (Focus) - Reliability aspects of ferroelectric hafnium oxide for application in non-volatile memories

Thomas Mikolajick(Germany) - NamLab and IHM, TU Dresden, Halid Mulaosmanovic(Germany) - NaMLab, Patrick Lomenzo(Germany) - NaMLab, Uwe Schroeder(Germany) - NaMLab, Stefan Slesazeck(Germany) - NaMLab, Benjamin Max(Germany) - IHM, TU Dresden

5D.2 (Focus) - TBD

Sayeef Salahuddin(United States) - UC Berkeley

5D.3 - Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization

Joel MINGUET LOPEZ(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Lucas HUDELEY(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Laurent GRENOUILLET(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Diego ALFARO ROBAYO(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Jury SANDRINI(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Gabriele NAVARRO(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Mathieu BERNARD(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Catherine CARABASSE(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Damien

DELERUYELLE(France) - INL CNRS, INSA Lyon, Niccolo CASTELLANI(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Marc BOCQUET(France) - Aix Marseille Univ, Université de Toulon, CNRS, IM2NP, Marseille, Jean-Michel PORTAL(France) - Aix Marseille Univ, Université de Toulon, CNRS, IM2NP, Marseille, Etienne NOWAK(France) - CEA, LETI, MINATEC Campus, GRENOBLE, Gabriel MOLAS(France) - CEA, LETI, MINATEC Campus, GRENOBLE

5D.4 - Composition Segregation of Ge-Rich GST and Its Effect on Reliability

Y.-H. Lee(United States) - TSMC, P.J. LIAO(Taiwan) - TSMC, V. Hou(United States) - TSMC, D.

Heh(Taiwan) - TSMC, C.H. Nien(Taiwan) - TSMC, Wen-Hsien Kuo(Taiwan) - TSMC, T.C. Chen(Taiwan) - TSMC, S.M. Yu(Taiwan) - TSMC, Y.S. Chen(Taiwan) - TSMC, J.Y. Wu(Taiwan) - TSMC, C.H. Diaz(United States) - TSMC

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5D.5 - A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path

W. Y. Yang(Taiwan) - National Chiao tung university, E. R. Hsieh(Taiwan) - NCU, C. H. Cheng(Taiwan) - NCTU, B. Y. Chen(Taiwan) - NCTU, K. S. Li(Taiwan) - TSRI, Steve Chung(Taiwan) - National Chiao tung university

Tutorial 22 - Full Chip ESD Verification

TuT22 (Tutorial) - Full Chip CDM ESD Verification Melanie Etherton(United States) - NXP Semicon 24th March 2021 5:10pm

5D - Authors' Corner

Poster Session

P1 - Monitoring Setup and Hold Timing Limits

Florian Cacho(France) - STMicroelectronics, Lorena Anghel(France) - Univ. Grenoble Alpes, CEA, CNRS, Grenoble INP, INAC-Spintec

P2 - Aging of Current DACs and its Impact in Equalizer Circuits

Tonmoy Dhar(United States) - University of Minnesota, Twin Cities, Jitesh Poojary(United States) - University of Minnesota, Twin Cities, Ramesh Harjani(United States) - University of Minnesota, Twin Cities, Sachin Sapatnekar(United States) - University of Minnesota, Twin Cities

P3 - BTI Arbitrary Stress Patterns Characterization & Machine-Learning optimized CET Maps Simulations

Louis Gerrer(France) - CEA, Leti, F-38000 Grenoble, France, Xavier Federspiel(France) -

STMicroelectronics, Florian Cacho(France) - STMI, David Roy(France) - STMicroelectronics SA, 850 rue Jean Monnet, 38920 Crolles, Fred GAILLARD(France) - CEA Leti, Xavier Garros(France) - Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France

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P4 - Mushroom-type Phase Change Memory with Projection Liner: An Array-Level Demonstration of Conductance Drift and Noise Mitigation

Robert Bruce(United States) - IBM T. J. Watson Research Center Yorktown Heights, Syed Ghazi Sarwat(Switzerland) - IBM Research Europe, Irem Boybat(Switzerland) - IBM Research Europe, Cheng-Wei Cheng(United States) - IBM Research, Wanki Kim(United States) - IBM Research, S. R.

Nandakumar(Switzerland) - IBM Research Europe, Charles Mackin(United States) - IBM Research - Almaden, Timothy Philip(United States) - IBM Research - Albany, Zuoguang Liu(United States) - IBM Research - Albany, Kevin Brew(United States) - IBM Research - Albany, Nanbo Gong(United States) - IBM Research, Injo Ok(United States) - IBM Research - Albany, Praneet Adusumilli(United States) - IBM Research, Katie Spoon(United States) - IBM Research - Almaden, Stefano Ambrogio(United States) - IBM Research - Almaden, Benedikt Kersting(Switzerland) - IBM Research Europe, Thomas

Bohnstingl(Switzerland) - IBM Research Europe, Manuel Le Gallo(Switzerland) - IBM Research Europe, Andrew Simon(United States) - IBM Research - Albany, Ning Li(United States) - IBM Research, Iqbal Saraf(United States) - IBM Research - Albany, Jin-Ping Han(United States) - IBM Research, Lynne Gignac(United States) - IBM Research, John Papalia(United States) - IBM Research, Tenko

Yamashita(United States) - IBM Research - Albany, Nicole Saulnier(United States) - IBM Research - Albany, Geoffrey Burr(United States) - IBM Research - Almaden, Hsinyu Tsai(United States) - IBM Research - Almaden, Abu Sebastian(Switzerland) - IBM Research Europe, Vijay Narayanan(United States) - IBM Research, Matthew BrightSky(United States) - IBM Research

P5 - Modeling and spectroscopy of ovonic threshold switching defects

Robin Degraeve(Belgium) - IMEC, Kapeldreef 75, B-3001 Leuven, Taras Ravsher(Belgium) - imec / KU Leuven, Shoichi Kabuyanagi(Japan) - Kioxia, Andrea Fantini(Belgium) - IMEC, Kapeldreef 75, B-3001 Leuven, Sergiu Clima(Belgium) - imec, Daniele Garbin(Belgium) - IMEC, Kapeldreef 75, B-3001 Leuven, Gouri Kar(Belgium) - imec

P6 - Impact of mechanical strain on wakeup of HfO2 ferroelectric memory

Anastasiia Kruv(Belgium) - imec / KU Leuven, Sean R. C. McMitchell(Belgium) - imec, Sergiu

Clima(Belgium) - imec, Oguzhan O. Okudur(Belgium) - imec, Nicolo Ronchi(Belgium) - imec, Geert Van den Bosch(Belgium) - imec, Mario Gonzalez(Belgium) - imec, Ingrid De Wolf(Belgium) - imec/KU Leuven, Jan Van Houdt(Belgium) - imec/KU Leuven

P7 - Multilevel Programming Reliability in Si-doped GeSbTe for Storage Class Memory

Giusy Lama(France) - CEA-Leti, Université Grenoble Alpes, F-38000 Grenoble, France, Mathieu BERNARD(France) - CEA Leti, Nicolas Bernier(France) - CEA Leti, Guillaume Bourgeois(France) - CEA Leti, Emmanuel Nolot(France) - CEA Leti, Niccolo CASTELLANI(France) - CEA Leti, Julien

Garrione(France) - CEA Leti, Marie Claire Cyrille(France) - CEA Leti, Gabriele NAVARRO(France) - CEA Leti, Etienne NOWAK(France) - CEA Leti

P8 - Impact of Multilevel Retention Characteristics on RRAM based DNN Inference Engine

Wonbo Shim(United States) - Georgia Institute of Technology, Jian Meng(United States) - Arizona State University, Xiaochen Peng(United States) - Georgia Institute of Technology, Jae-sun Seo(United States) - Arizona State University, Shimeng Yu(United States) - Georgia Institute of Technology

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P9 - Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process

Chao-Yang Chen(Taiwan) - Institute of Electronics, National Chiao Tung University, Jian-Hsing Lee(Taiwan) - Vanguard International Semiconductor Corporation, Karuna Nidhi(Taiwan) - Vanguard International Semiconductor Corporation, Tzer-Yaa Bin(Taiwan) - Vanguard International

Semiconductor Corporation, Geeng-Lih Lin(Taiwan) - Vanguard International Semiconductor Corporation, Ming-Dou Ker(Taiwan) - Institute of Electronics, National Chiao Tung University

P10 - Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp

Sagar Karalkar(Singapore) - GlobalFoundries, VISHAL GANESAN(Germany) - GlobalFoundries, Milova Paul(Singapore) - GlobalFoundries, Kyong Jin Hwang(Singapore) - GlobalFoundries, Robert Gauthier Jr(United States) - GlobalFoundries

P11 - A Novel High Voltage Drain Extended FinFET SCR for SoC Applications

Monishmurali M(India) - Department of Electronic Systems Engineering, IISc, Mayank Shrivastava(India) - Department of Electronic Systems Engineering, IISc

P12 - Peculiar Current Instabilities & Failure Mechanism in Vertically Stacked Nanosheet ggN-FET Monishmurali M(India) - Department of Electronic Systems Engineering, IISc, Mayank

Shrivastava(India) - Department of Electronic Systems Engineering, IISc

P13 - Characterization of NMOS-based ESD Protection for Wide-range Pulse Immunity Yasuyuki Morishita(Japan) - Renesas Electronics Corporation

P14 - Estimation of Oxide Breakdown Voltage During a CDM Event Using Very Fast Transmission Line Pulse and Transmission Line Pulse Measurements

Chloé Troussier(France) - STMicroelectronics SA, Johan Bourgeat(France) - STMicroelectronics SA, 850 rue Jean Monnet, 38920 Crolles, Emmanuel Simeu(France) - Univ. Grenoble Alpes, CNRS, Grenoble INP*, TIMA, 38000 Grenoble, Jean-Daniel Arnould(France) - Univ. Grenoble Alpes, Grenoble INP, RFIC-Lab, 38000 Grenoble, Blaise Jacquier(France) - STMicroelectronics SA, 850 rue Jean Monnet, 38920 Crolles

P15 - Investigation of the Failure Mechanism of InGaAs-pHEMT under High Temperature Operating Life Tests

Yasunori Tateno(Japan) - Sumitomo Electric Industries, Ltd., Akio Oya(Japan) - Sumitomo Electric Device Innovations, Inc., Keita Matsuda(Japan) - Sumitomo Electric Device Innovations, Inc., Yoshihide Komatsu(Japan) - Sumitomo Electric Device Innovations, Inc., Shinichi Osada(Japan) - Sumitomo Electric Device Innovations, Inc., Masafumi Hirata(Japan) - Sumitomo Electric Device Innovations, Inc., Shigeyuki Ishiyama(Japan) - Sumitomo Electric Device Innovations, Inc., Toshiki Yoda(Japan) -

Sumitomo Electric Device Innovations, Inc., Ken Nakata(Japan) - Sumitomo Electric Industries, Ltd., Atsushi Nitta(Japan) - Sumitomo Electric Device Innovations, Inc., Tomio Sato(Japan) - Sumitomo Electric Device Innovations, Inc.

P16 - Time series modeling of the cycle-to-cycle variability in h BN based memristors

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Granada., David Maldonado(Spain) - Electrónica y Tecnología de Computadores. Universidad de Granada., Francisco Alonso(Spain) - Dep. Estadística e Investigación Operativa. Universidad de Granada., Andres Roldán(Spain) - Electrónica y Tecnología de Computadores. Universidad de

Granada., Fei Hui(Israel) - Faculty of Materials Science and Engineering, Technion – Israel Institute of Technology, Haifa 3200003, Yuanyuan Shi(Belgium) - IMEC, Kapeldreef 75, B-3001 Leuven, Francisco Jiménez-Molinos(Spain) - Electrónica y Tecnología de Computadores. Universidad de Granada., Ana Aguilera(Spain) - Dep. Estadística e Investigación Operativa. Universidad de Granada., Mario

Lanza(Saudi Arabia) - Physical Sciences and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal 23955-6900

P17 - Runtime Variability Monitor for Data Retention Characteristics of Commercial NAND Flash Memory

Matchima Buddhanoy(United States) - Department of Electrical and Computer Engineering, The University of Alabama in Huntsville, Sadman Sakib(United States) - Department of Electrical and Computer Engineering, The University of Alabama in Huntsville, Biswajit Ray(United States) - Department of Electrical and Computer Engineering, The University of Alabama in Huntsville

P18 - The Characterization of Degradation on various SiON pMOSFET transistors under AC/DC NBTI stress

Gang-Jun Kim(Korea, Republic of) - Sama, Moonjee Yoon(Korea, Republic of) - Samsung Electronic, Sungwhan Kim(Korea, Republic of) - Samsung Electronic, Myeongkyu Eo(Korea, Republic of) - Samsung Electronic, Shinhyung Kim(Korea, Republic of) - Samsung Electronic, Taehun You(Korea, Republic of) - Samsung Electronic, Nam-Hyun Lee(Korea, Republic of) - Samsung Electronic, Kijin Kim(Korea, Republic of) - Samsung Electronic, SANGWOO PAE(Korea, Republic of) - Samsung Electronic

P19 - A Theoretical Framework for Trap Generation and Passivation in NAND Flash Tunnel Oxide During Distributed Cycling and Retention Bake

Tarun Samadder(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay), Satyam Kumar(India) - IIT Bombay, Karansingh Thakor(India) - Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay), Souvik Mahapatra(India) -

Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay)

P20 - Efficient Data Recovery Technique for 3D TLC NAND Flash Memory based on WL Interference Liu Yang(China) - Institute of Microelectronics of Chinese Academy of Sciences, Qi Wang(China) - Institute of Microelectronics of Chinese Academy of Sciences, Qianhui Li(China) - Institute of Microelectronics of Chinese Academy of Sciences, xiaolei yu(China) - Institute of Microelectronics of Chinese Academy of Sciences, jing he(China) - Institute of Microelectronics of Chinese Academy of Sciences, zongliang huo(China) - Institute of Microelectronics of Chinese Academy of Sciences P21 - An efficient methodology to evaluate BEOL and MOL TDDB in advanced nodes

Sumy Jose(Netherlands) - NXP Semiconductors, Xiaoling Zhao(Singapore) - GlobalFoundries, Chunshan Yin(Netherlands) - Nxp, Zhang Fan(Singapore) - GlobalFoundries, Chen Yu(Netherlands) - NXP

Semiconductors, Cheong Min Hong(Netherlands) - NXP Semiconductors, Mehul Shroff(Netherlands) - NXP Semiconductors