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High Fill Factor Imagers for Neuromorphic Processing Enabled by Floating Gate Circuits

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Figure

Figure 2: Layout, cross-section, and circuit diagram of the floating-floating-gate is our symbol for a tunneling junction capacitor withgate pFET in a standard double-poly, n-well MOSIS process
Figure 3: Computation and programming in floating-gate analog computing arrays. (a) Illustration of our computing in floating-gate mem-ory arrays

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