JEDEC/IPC-9702

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IPC/JEDEC-9702

Monotonic Bend Characterization

of Board-Level Interconnects

ELECTRONICS INDUSTRIES®

2215 Sanders Road, Northbrook, IL 60062-6135 2500 Wilson Blvd. Suite 220, Arlington, VA 22201 Tel. 847.509.9700 Fax 847.509.9798 Tel. 703.907.7559 Fax 703.907.7583

IPC/JEDEC-9702

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The Principles of Standardization

In May 1995 the IPC’s Technical Activities Executive Committee adopted Principles of Standardization as a guiding principle of IPC’s standardization efforts.

Standards Should:

• Show relationship to Design for Manufacturability (DFM) and Design for the Environment (DFE) • Minimize time to market

• Contain simple (simplified) language • Just include spec information • Focus on end product performance • Include a feedback system on use and

problems for future improvement

Standards Should Not: • Inhibit innovation • Increase time-to-market • Keep people out • Increase cycle time

• Tell you how to make something • Contain anything that cannot

be defended with data

Notice IPC Standards and Publications are designed to serve the public interest through eliminating mis-understandings between manufacturers and purchasers, facilitating interchangeability and improve-ment of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of IPC from manufacturing or selling products not conforming to such Standards and Publication, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than IPC members, whether the standard is to be used either domestically or internationally.

Recommended Standards and Publications are adopted by IPC without regard to whether their adop-tion may involve patents on articles, materials, or processes. By such acadop-tion, IPC does not assume any liability to any patent owner, nor do they assume any obligation whatever to parties adopting the Recommended Standard or Publication. Users are also wholly responsible for protecting them-selves against all claims of liabilities for patent infringement.

IPC Position Statement on Specification Revision Change

It is the position of IPC’s Technical Activities Executive Committee (TAEC) that the use and implementation of IPC publications is voluntary and is part of a relationship entered into by customer and supplier. When an IPC publication is updated and a new revision is published, it is the opinion of the TAEC that the use of the new revision as part of an existing relationship is not automatic unless required by the contract. The TAEC recommends the use of the latest

revision. Adopted October 6. 1998

Why is there a charge for this document?

Your purchase of this document contributes to the ongoing development of new and updated industry standards and publications. Standards allow manufacturers, customers, and suppliers to understand one another better. Standards allow manufacturers greater efficiencies when they can set up their processes to meet industry standards, allowing them to offer their customers lower costs.

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©Copyright 2004. JEDEC, Arlington, Virginia, and IPC, Northbrook, Illinois. All rights reserved under both international and Pan-American copyright conventions.Any copying, scanning or other reproduction of these materials without the prior written consent of the copyright holder is strictly prohibited and constitutes infringement under the Copyright Law of the United States.

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Monotonic Bend

Characterization

of Board-Level

Interconnects

Developed by the SMT Attachment Reliability Test Methods Task Group (6-10d) of the Product Reliability Committee (6-10) of IPC and the JEDEC Reliability Test Methods for Packaged Devices Committee (JC-14.1)

Users of this publication are encouraged to participate in the development of future revisions.

Contact: IPC 2215 Sanders Road Northbrook, Illinois 60062-6135 Tel 847 509.9700 JEDEC

Solid State Technology Association 2500 Wilson Boulevard

Arlington, VA 22201-3834 Tel 703 907.7559 ASSOCIATION CONNECTING

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Acknowledgment

Members of the JEDEC Reliability Test Methods for Packaged Devices Committee (JC-14.1) and the SMT Attachment Reliability Test Methods Task Group (6-10d) of the Product Reliability Committee (6-10) have worked together to develop this document. We would like to thank them for their dedication to this effort. Any document involving a complex technol-ogy draws material from a vast number of sources. While the principal members of the SMT Attachment Reliability Test Methods Task Group are shown below, it is not possible to include all of those who assisted in the evolution of this stan-dard. To each of them, the members of the JEDEC and IPC extend their gratitude.

Product Reliability Committee

JEDEC Reliability Test Methods for Packaged Devices Committee

SMT Attachment Reliability Test Methods Task Group

Chair

Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory

Chair

Jack McCullen Intel Corporation

Chair

Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Vice-Chair

Werner Engelmaier

Engelmaier Associates, L.C.

Technical Liaisons of the IPC Board of Directors

Peter Bigelow IMI Inc. Sammy Yi

Flextronics International

SMT Attachment Reliability Test Methods Task Group

Mudasir Ahmad, Cisco Systems, Inc. Patricia J. Amick, Boeing Aircraft &

Missiles

Pierre Audette, Nortel Networks Jean Bobgan, Guidant Corporation Dr. John Kirk Bonner, Jet Propulsion

Laboratory

Mark Brillhart, Cisco Systems Inc. Nicole Butel, Agilent Technologies Srinivas Chada, Ph.D., Jabil Circuit,

Inc.

Phillip Chen, Northrop Grumman Canada Corporation

Beverley Christian, Ph.D., Research In Motion Limited

Thomas Clifford, Lockheed Martin Space Systems Company Yves Desrochers, Nortel Networks Howard S. Feldmesser, Johns

Hopkins University

Jean-Yves Gagne, Nortel Networks Mahendra S. Gandhi, Northrop

Grumman

Phil Geng, Intel Corporation

Denis Gignac, Nortel Networks Lavanya Gopalakrishnan, Ciena

Corporation

Michael R. Green, Lockheed Martin Space Systems Company

Samy Hanna, AT&S Austria Technologie & Systemtechnik Hana Hsu, Mitac International

Corporation

Kim Hyland, Solectron Corp. Thomas E. Kemp, Rockwell Collins Vincent B. Kinol, Umicore America

Inc.

Gregg Klawson, General Dynamics -C4 Systems

Dennis Krizman, Celestica Kuan-Shaur Lei, Hewlett-Packard

Company

James F. Maguire, Intel Corporation Wesley R. Malewicz, Draeger

Medical Systems, Inc.

John Manock, Lucent Technologies, Inc.

Susan S. Mansilla, Robisan Laboratory Inc.

Lei L. Mercado, Ph.D., P.E., Intel Corporation

Frank Mortan, Texas Instruments Keith G. Newman, Sun Microsystems

Inc.

Bob Ogden, Raytheon Systems Company

Deepak K. Pai, C.I.D.+, General Dynamics-Advanced Information Mel Parrish, Soldering Technology

International

Kumar Pavuluri, Texas Instruments Inc.

Mike Pfeifer, Motorola Inc. Sundar Sethuraman, Solectron

Corporation

Rocky Shih, Hewlett-Packard Company

Vern Solberg, Tessera Technologies, Inc.

Vish Sundararaman, Ph.D., Texas Instruments Inc.

Vasu S. Vasudevan, Intel Corporation Dewey Whittaker, Honeywell Inc. Greg Wood, ACI/EMPF

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Monotonic Bend Characterization

of Board-Level Interconnects

1 FOREWORD

This publication on monotonic bend testing is intended to characterize the fracture strength of a component’s board-level interconnects. The document is applicable to surface mount components attached to printed wiring boards using conventional solder reflow technologies. The monotonic bend characterization results provide a measure of fracture resistance to flexural loading that may occur during con-ventional non-cyclic board assembly and test operations, and supplements existing standards that address mechani-cal shock or impact during shipping, handling or field operation.

2 INTRODUCTION

Semiconductor devices are assembled in a variety of pack-age configurations, and are used in a multitude of applica-tions. Given the diversity of package constructions and end-use conditions, it is not feasible to establish a single qualification requirement relating to bend testing; however, definition of a uniform test methodology and a standard reliability characterization reporting process are increas-ingly necessary to ensure adequate product quality.

3 SCOPE

This publication specifies a common method of establish-ing the fracture resistance of board-level device intercon-nects to flexural loading during non-cyclic board assembly and test operations. Monotonic bend test qualification pass/ fail requirements are typically specific to each device appli-cation and are outside the scope of this document.

4 TERMS AND DEFINITIONS

For the purposes of this standard, the selected terms and definitions listed below apply.

General Terms

Component: Packaged semiconductor device

Interconnect: Conductive element used for electrical interconnection, e.g., solder ball, lead, etc.

Monotonic Test: Non-reversing, test to fail Strain Related Terms

Global PWB Strain: Four-point bending strain of uniform printed wiring board, ignoring any effects due to the pack-age(s)

Microstrain: Dimensionless unit, 106_{x (change in length)} ÷(original length)

Strain: Dimensionless unit, (change in length)÷ (original length)

Strain-Rate: Change in strain divided by the time interval during which this change is measured

Strain Gage: Planar copper foil pattern that is adhered to an underlying surface and exhibits a change in resistance when subjected to a strain

Strain Gage Element: Sensing area of strain gage defined by the serpentine copper grid pattern

Uniaxial Strain Gage: Strain gage incorporating a single strain gage element, i.e., capable of detecting strain along a single axis

Mechanical Test Equipment Terms

Anvil: Four-point assembly fixture support with a rounded contact surface

Crosshead Assembly: Clamping/attachment assembly of universal tester that moves relative to the base of the test equipment, and creates the forces necessary for specimen testing

Four-Point Bending Fixture: Test assembly that supports a specimen on two anvils or rollers, and symmetrically loads the specimen on the opposite surface with two anvils or rollers

Load Span: Distance between the two anvils or rollers that load the test specimen

Roller: Four-point assembly fixture support that incorpo-rates a cylindrical bar as the contact surface

Support Span: Distance between the two anvils or rollers that support the test specimen

Universal Tester: Test equipment capable of tensile/ compressive loading using controlled linear motion of a crosshead assembly

Electrical Test Terms

Daisy-Chain: A conductive link that can be connected in series with other conductive links (like a chain of daisies) to form a continuous electrical net

In-Situ Measurement: Measurement conducted during a test, i.e., in place, rather than during an interruption of the test condition

Failure Analysis Term

Dye-and-Pry: Dye exposure of package/board assembly followed by mechanical removal of the package

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5 SYMBOLS AND ABBREVIATED TERMS

Unit Symbol

board thickness t

crosshead travel distance δ

crosshead speed δ˙ degree Celsius °C degree Fahrenheit °F Hertz Hz load span L_L microstrain µεor µStrain second (time) s strain ε strain-rate ε˙ support span L_S Term Abbreviation

ball grid array BGA

chip scale (size) package CSP intermetallic compound IMC organic solderability preservative OSP

printed wiring board PWB

surface mount SMT

small outline package SOP

6 SAMPLING

A statistically relevant sample size is required. It is recom-mended that several manufacturing lots be sampled to evaluate lot-to-lot variability. Depending on failure distri-bution, desired sensitivity, confidence limits, etc., sample quantities such as 23, 30, 45, etc., may be appropriate.

7 APPARATUS

7.1 Universal Tester A universal tensile tester incorpo-rating a deflection measuring device shall be used to gen-erate a controlled board deflection rate. The tester shall include a four-point bending fixture (see Figure 7-1) to apply a theoretically uniform bending moment across the load span.

Table 7-1 lists dimensional and operational requirements for the universal tester.

Non-standardized bend test methods in practice today often specify an applied load, span and/or crosshead travel dis-tance to characterize mechanical resisdis-tance to failure of board-level device interconnects. Unfortunately, these parameters are not readily transferable to differing board thicknesses, package configurations or board layouts. The dimensionless unit of strain, ε, however, can be applied more broadly to differing board/package geometries and relates more directly to analytical and computational failure models.

IPC/JEDEC-9702-7-1

Figure 7-1 Universal Tester

Table 7-1 Universal Tester Requirements

Description Requirement

Anvil/roller radius 3 mm

[0.12 in.], min.

Anvil/roller length > board width

Ambient temperature 23 °C ± 2 °C

[73 °F ± 4 °F]

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The crosshead travel distance (δ) and crosshead speed (˙δ) of a universal tester are approximately proportional to the test board assembly strain (ε) and strain-rate (˙ε), respec-tively. The relationship between these variables can be determined empirically by testing a mechanically represen-tative package/board assembly (set-up test board); how-ever, these relationships may prove constant or non-determinant, depending on universal tester capability and board/ package configuration.

This test method specifies use of the following simplified analytical relationships (see Equations 1 & 2) to establish the universal tester control settings for crosshead travel distance and crosshead speed, based upon global PWB strain and strain-rate input variables, respectively. These equations are derived from classic beam theory and ignore any effects due to the package(s), or to the Poisson’s ratio effect of a plate in bending.

Equation 1

δ =ε (LS−LL) (LS+2LL) 6t

where

δ = crosshead travel distance ε = global PWB strain L_S = support span

L_L = load span (centered within support span) t = PWB thickness Equation 2 ˙ ˙ δ =ε (LS−LL) (LS+2LL) 6t where ˙ δ = crosshead speed ˙ ε = global PWB strain-rate L_S = support span

L_L = load span (centered within support span) t = PWB thickness

7.2 Strain Measurement Equipment A strain measure-ment equipmeasure-ment scan frequency of 500 Hz (min.), and a data signal resolution of 16 bits (min.) are preferred for the short duration (<5 seconds, typ.) monotonic bend test.

7.3 Continuity Monitoring Equipment Continuity moni-toring is preferably performed by the same high scan fre-quency equipment used for strain measurements, allowing simultaneous recording of net resistance and strain.

8 PROCEDURE

8.1 Component Sample This standard assumes a surface mount device; BGA, SOP and CSP are typical device

examples. Discrete SMT devices, e.g., capacitors, resistors, etc., are outside the scope of this test method. The test component must contain daisy-chain connections to allow in-situ continuity monitoring of the device board-level interconnects during the bend test. It is likely that the same daisy-chain package construction may be used for both bend testing and thermal cycle testing. For bend testing of array-based packages; however, only the outermost pack-age daisy-chain links need to be connected to a correspond-ing PWB daisy-chain link and electrically monitored. The daisy-chain package materials, dimensions, and con-struction must be representative of a typical production device. The layout of solder balls or leads for the daisy-chain package should represent a typical leadcount con-figuration expected for a production device of that package body size. As indicated previously, the monitored daisy-chain links on the package consist of the outer component interconnects. Each package daisy-chain link should con-sist of a pair of adjacent solder joints or leads.

Functional devices may be used in lieu of a daisy-chain package if the electrical continuity monitoring require-ments defined in this publication can be met.

8.2 Test Board Material The test board material should match the composition of the actual end-use PWB, typi-cally FR4 epoxy/glass laminate.

8.3 Test Board Thickness and Metal Layer Count The test board thickness and metal layer count should match the actual end-use PWB. Definition of a ‘‘typical’’ printed wir-ing board is problematic given the expandwir-ing usage of alternative board constructions and materials, and the wid-ening form-factor gap between handheld electronic devices and other application types. Table 8-1 provides a minimum recommended test board thickness and metal layer count if the device will be used in a variety of end-use applications, or if the actual PWB configuration is unknown. Finite ele-ment modelling suggests that the ratio between package/ solder interfacial strain and global PWB strain increases with increased board thickness and copper layer count. Consequently, use of a thicker test board or higher metal layer count than listed in Table 8-1 will typically lead to more conservative bend test results.

Table 8-1 Recommended Test Board Thickness & Layer Count

Max. Package Body Dimension, X (mm) [in.] PWB Thickness, min. (mm) [in.] Copper Layers, min. Small: X≤15 [0.59] 1.00 [0.039] 4 Medium: 15 [0.59] < X <40 [1.58] 1.55 [0.062] 6 Large: X≥40 [1.58] 2.35 [0.093] 8

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8.4 Test Board Surface Finish The test board surface finish should match the actual end-use PWB surface finish. If the device will be used in a variety of applications, mul-tiple surface finishes may need to be evaluated.

8.5 Test Board Land Pads The test board land pads should match the configuration of the actual end-use PWB, typically non-solder mask defined (NSMD). If the end-use configuration is unknown, NSMD land pads should be used with exposed PWB land pad diameters that are 80-100% of the package solder-wetted pad diameters.

8.6 Test Board Layout Finite element simulations sup-port the testing of multiple packages on a test board (see Figure 8-1) given the specific test board layout require-ments detailed in Table 8-2; however, variations in PWB and solder strain are typically greater for test boards with multiple components.

The lengthwise direction of rectangular packages should be aligned with the longitudinal direction of the test board as illustrated in Figure 8-2.

8.7 Test Board Daisy-Chain Links The combination of daisy-chain links on the package and those on the test board should result in completed daisy-chain nets after board assembly. 100% daisy-chain coverage of the outer package interconnects parallel to the anvils/rollers is required, but the coverage may extend to the entire pack-age interconnect footprint. Each packpack-age must have at least

a single separately monitored daisy-chain net. See Figure 8-3 for an illustration of a test board daisy-chain configu-ration (single package).

Test boards using functional devices may require a modi-fied configuration to satisfy the electrical continuity moni-toring requirements.

IPC/JEDEC-9702-8-1

Figure 8-1 Test Board Layout

Table 8-2 Test Board Layout Requirements

Description Requirement

Package quantity per board

15 (3 row x 5 col.), max. - small* pkg 4 (2 row x 2 col), max. - medium* pkg 4 (2 row x 2 col), max. - large* pkg * Note: see Table 8-1 for package body size classifications

Distribution Package sites must be uniformly distributed

Symmetry Package sites must be symmetrical

about both mid-span axis and PWB longitudinal centerline

Package-to-package separation (x-y directions)

5 mm [0.20 in.], min. (package edge to package edge)

Package-to-anvil separation

10 mm [0.39 in.], min. (package edge to inner anvil/roller centerline) Package-to-board

separation

8 mm [0.32 in.], min. (outermost package edge to board edge) Package orientation Package orthogonal to PWB &

four-point bend fixture

Connector location Outside support span anvils/rollers, including when PWB is bent in its max. condition

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IPC/JEDEC-9702-8-2

Figure 8-2 Rectangular Package Orientation

IPC/JEDEC-9702-8-3

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For array-based SMT packages, the solder connections at the package corner typically fail sooner during monotonic bend testing than the connections on the middle of the package edge. Consequently, separate daisy-chain nets for the package corners are recommended. Finite element analysis indicates that the package/solder interfacial strain at the package corner is most severe for the largest pack-age body sizes, and for the largest array of test packpack-ages on a single test board.

Electrical monitoring traces should be routed on internal PWB layers to reduce the likelihood of external trace tact damage during testing. Further, test board vias con-necting internal electrical monitoring traces may fail prior to the monitored package interconnections. Consequently, it is recommended that any circuitry associated with conti-nuity monitoring have redundant trace and via routing wherever possible. Outer layer traces required by PWB routing constraints should avoid anticipated strain gage locations.

Probe pads are recommended for each component daisy-chain link, wherever possible, to facilitate fault isolation and failure analysis.

8.8 Board Assembly The solder paste printing process and thermal reflow profile should be optimized prior to mass reflow or rework assembly of the test boards. Optimi-zation of solder paste volume and paste registration typi-cally requires evaluation of printing speed, squeegee pres-sure, stencil separation speed, stencil thickness, stencil aperture geometries, etc. Similarily, optimization of solder wetting, solder ball/fillet shape and solder surface finish often involves evaluation of preheat temperature, peak solder/package/board temperatures, duration above solder liquidus temperature, cooling/heating ramp rates, etc.

8.9 Storage The measured fracture resistance of the board-level interconnects can be affected by storage condi-tions (temperature, humidity, atmosphere) and storage duration of the package/PWB assemblies prior to bend test-ing. A recommended duration between board assembly and bend test is eight hours, minimum, and 168 hours, maxi-mum.

8.10 Strain Gages For the test configuration defined in this standard, finite element modelling indicates that the PWB principal strain angle is essentially coincident with the longitudinal board axis at all board locations. There-fore, the use of uniaxial strain gages for monitoring board strain and strain-rate is acceptable. A nominal strain gage element size of 1.5 mm x 1.5 mm [0.059 in. x 0.059 in.] is recommended.

The sensing direction of the uniaxial strain gage must be aligned with the longitudinal board direction. For test con-figurations meeting the specific requirements of this test

method, analysis indicates that the PWB strain values are generally uniform from one package location to another, allowing for the requirement of only three strain gages per test board (see Figure 8-4). Additional strain gages at the opposite PWB diagonal can be used to verify symmetrical loading.

Although PWB strain measurements from any single loca-tion in Figure 8-4 may prove more relevant to a particular end-use PWB assembly condition or application, all three strain gage locations relate to package interconnect strain and fracture resistance. Cumulatively, the PWB strain read-ings at these locations provide enhanced characterization of a device’s interconnect fracture resistance. Measurements using the strain gage mounted on the top of the test board as shown in Figure 8-4 approximate global PWB strain. PWB strain readings using the gage placed at the package center as shown in Figure 8-4 approximate minimum PWB strain and help quantify the localized stiffening effect of the test package. Finally, measurements using the strain gage coincident with the cornermost solder joint, or lead, approximate maximum PWB strain.

The strain gages should be mounted to the test board using materials and procedures specified by the gage manufac-turer, e.g., surface preparation, adhesive application, gage attachment, adhesive cure, leadwire attachment, etc. Although it is not preferred practice, strain gages may not be necessary on every test board if a documented database of past test results (using near-identical configurations) has established minimal statistical strain variation between one test board assembly and another, and the crosshead travel distance at interconnect failure can be accurately recorded.

8.11 Set-Up Test Board A set-up test board is recom-mended for verification of test parameter settings. Strain gage monitoring of the set-up board beyond the minimal requirements shown in Figure 8-4 is recommended to pro-vide more complete characterization of the PWB strain dis-tribution.

8.12 Four-Point Bend Test The test assembly should be oriented as shown in Figure 7-1 such that the component leads or solder joints are placed in tension during the four-point bend test. Empirical testing, supported by finite ele-ment analysis, indicates that board-level package solder connections are typically more susceptible to fracture with increased strain-rate (at comparable PWB strain levels). Testing conducted at crosshead speeds less than specified in Table 8-3 will tend to overstate fracture strength of a component’s board-level interconnects; hence, test equip-ment and test board configurations should be selected that meet the minimum crosshead speed shown below, wher-ever possible, to insure consistent, conservative reporting of interconnect strength.

A PWB pre-load is specified to ‘‘seat’’ the test board against all four anvils/rollers prior to start of the test. The

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actual monotonic bend test occurs at a constant crosshead speed corresponding to the nominal global PWB strain rate value specified in Table 8-3, terminating when all of the monitored daisy-chain nets have electrically failed. Although it should be avoided wherever possible, equip-ment and test configuration limitations may sometimes results in test termination before failure.

Annex A provides example universal tester configurations that satisfy the four-point bend test requirements of Table 8-3, using the crosshead speed as calculated by Equation 2, and the PWB test board thicknesses referenced in Table 8-1.

Strain gage readings should be calibrated and set to zero in the initial undeflected condition, prior to the specified pre-load. The test board strain gages should be continuously monitored at a recommended scan frequency of no less than 500 Hz, and recorded during the entire board deflec-tion procedure.

Depending on board configuration and warpage, the pre-load level shown in Table 8-3 may not always result in proper seating of the PWB against the anvils/rollers. The test board assembly should be returned to an unloaded con-dition immediately upon conclusion of the test.

In-situ monitoring of the daisy-chain nets is preferably con-ducted using the same equipment used to measure strain, with strain and net resistance recorded simultaneously.

9 FAILURE CRITERIA AND ANALYSIS

A recommended definition of electrical failure is a 20% increase in daisy-chain net resistance; however, a lower or higher threshold may be more appropriate, depending upon test equipment capability and specific daisy-chain design scheme.

The clear goal of failure analysis is the ability to detect the location, mode and mechanism for the observed electrical failure. Failure analysis should verify that detected failures or resistance increases are not due to associated cabling, connectors, testboard or test apparatus. For bend tests stopped without electrical failure, failure analysis should be performed to insure that failures were not missed due to errors in daisy-chain design or test hardware.

Non-destructive failure analysis tools that may be used include x-ray, coupled scanning acoustic microscopy (CSAM), and side view optical microscopy. Common methods and tools during destructive failure analysis include cross section, dye-and-pry, x-ray, CSAM, scanning IPC/JEDEC-9702-8-4

Figure 8-4 Strain Gage Placement

Table 8-3 Monotonic Bend Test Requirements

Parameter Value

PWB pre-load,ε 100 µStrain, max.*

* Note: pre-load is measured using strain gage mounted on the top of the test board as specified in Figure 8-4

Minimum crosshead speed, ˙δ

Calculated value (see Equation 2), using nominal global PWB strain-rate, ˙ε, of 5,000 µStrain/s Maximum crosshead

travel distance,δ

Electrical failure of all daisy-chain nets

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electron microscope (SEM) and energy dispersive x-ray (EDX).

The mechanical failure mode(s) of each component should be identified. Each observed failure mode shall be docu-mented using cross-section (or other suitable analysis

tech-nique) of one representative solder joint or lead, at a min-mum. Example failure modes for solder ball array style packages are illustrated in Figure 9-1. Failure modes for leaded style packages include lead cracking, package body cracking, and cracking between the various lead, IMC, sol-der and PWB metal pad interfaces.

IPC/JEDEC-9702-9-1

Figure 9-1 Interconnect Fracture Modes (Solder Ball Array Devices)

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ANNEX A (Informative) - Example Universal Tester Configurations

This annex provides example universal tester configurations that satisfy the four-point bend test requirements of Table 8-3, using Equation 2. The example configurations shown in Figures A.1 - A.3 represent a non-exhaustive summary of the pos-sible options that satisfy this guideline’s requirements.

IPC/JEDEC-9702-a1

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IPC/JEDEC-9702-a2

Figure A.2 Example Configuration (PWB Thickness = 1.55 mm)

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IPC/JEDEC-9702-a3

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ANNEX B (Informative)

-Test Report Recommendations

A test report including comprehensive documentation of the bend test is recommended (see Tables B.1 - B.3). Disclosure of the test report contents will depend on specific customer/supplier agreements.

Table B.1 Test Report Recommendations (Equipment & Materials)

Category Description

Equipment Manufacturer, model number and operational conditions for the following: • universal tester

• strain measurement equipment • continuity monitoring equipment Four-point bend test fixture • load span • support span • anvil/roller radius • anvil/roller length

Component • package outline drawing or reference to JEDEC outline

• die dimensions (width, length and thickness) and orientation (rectangular die) • daisy-chain connection map and/or net list

• measured solder ball or lead coplanarity

• solder ball shear values or lead pull strength, and associated failure modes (parts from same production lot as tested devices)

• solder-wetted pad dimensions, if applicable

• solder ball land pad type, if applicable (solder mask defined, etc.)

• lead finish/pad metallization, including thicknesses of all layers and composition of solder, if applicable Test board • width, length and thickness

• dielectric material • surface finish

• external trace, pad and solder resist opening dimensions • measured board coplanarity

Strain gage • manufacturer and part number • resistance

• strain gage element size

Table B.2 Test Report Recommendations (Board Assembly)

Board assembly • preheat temperature, ramp rate, critical peak temperatures (solder, package surface, board, etc.) duration above solder liquidus temperature and cooling rate

• solder composition

• solder paste metal percentage, particle mesh size type and flux type • reflow atmosphere

• nominal solder paste volume • nominal solder joint geometry

• component/PWB storage and/or bake-out conditions prior to board assembly • storage conditions and duration following board assembly

Table B.3 Test Report Recommendations (Test Results)

Set-up data • strain rate vs. crosshead speed* • strain vs. crosshead travel distance* • force vs. crosshead travel distance Strain data (each

test board) • strain vs. time* • strain-rate vs. time* • strain vs. strain-rate* • force vs. time Resistance data

(each test board)

• resistance vs. time

Failure distribution • cumulative failure percentage vs. strain (2-parameter Weibull ) Failure mode • failure mode histogram (all test packages)

• time-zero cross-section of a single pkg/board test assembly

• failure analysis of representative sample of each observed failure mode * Note: Measurements at each strain gage location should be reported.

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Standard Improvement Form

IPC/JEDEC-9702

The purpose of this form is to provide the Technical Committee of IPC with input from the industry regarding usage of the subject standard.

Individuals or companies are invited to submit comments to IPC. All comments will be collected and dispersed to the appropriate committee(s).

If you can provide input, please complete this form and return to:

IPC

2215 Sanders Road Northbrook, IL 60062-6135 Fax 847 509.9798

E-mail: [email protected]

1. I recommend changes to the following: Requirement, paragraph number

Test Method number , paragraph number The referenced paragraph number has proven to be:

Unclear Too Rigid In Error Other

2. Recommendations for correction:

3. Other suggestions for document improvement:

Submitted by:

Name Telephone

Company E-mail

JEDEC/IPC-9702

IPC/JEDEC-9702

Monotonic Bend Characterization

of Board-Level Interconnects

IPC/JEDEC-9702

Monotonic Bend

Characterization

of Board-Level

Interconnects

Acknowledgment

Table of Contents

Monotonic Bend Characterization

of Board-Level Interconnects

ANNEX A (Informative) - Example Universal Tester Configurations

ANNEX B (Informative)

-Test Report Recommendations

Standard Improvement Form

IPC/JEDEC-9702