L2 V4 06 C264 PSL & Interlock Configuration E 01

(1)

MiCOM C264 PSL &

INTERLOCKINGS

CONFIGURATION

PCL

PACiS

PACiS Technical

Technical

Technical Training

Training

Training Level

Level

Level 2

2

2 CS&P

CS&P

(2)

• Content

General Features

PSL Creation

(3)

Schneider Electric- CS&P – C264 PSL 1 Interlock Configuration – E01

• Content

General Features

PSL Creation

(4)

• Technical Data (1)

1) Number max of PSL / INTERLOCK per MiCOM C264 =>

768 2) PSL Inputs :

- SPS, DPS, MPS

(Boolean value per status defined in profile)

- MV

(Thresholds, Boolean values defined in profile)

- SPC, DPC

(Boolean value per control defined in profile)

3) PSL Outputs :

- SPS

(advised, advantage => follow execution)

- SET when PSL TRUE

- RESET when PSL FALSE

- SELF-CHECK-FAULTY when PSL INVALID

-

SPC, DPC

(FORBIDDEN)

- SET/CLOSED when PSL TRUE

- RESET/OPEN when PSL FALSE

- NOTHING when PSL INVALID

4) PSL Timers :

- Settable timer through MiCOM S1 PACiS

(5)

Schneider Electric- CS&P – C264 PSL & Interlock Configuration – E01

• Technical Data (2)

1)

Since PACiS V4.6 version, it is possible to

filter the transient 00

position

in PSL evaluation for DPS (jammed). This allow to see in FBD the last

position during jammed position.

Ex: if

from Open state, it goes to jammed

, so

Open state is considered

in

the FBD till Closed state appears.

2)

To configure this possibility, in the “

Interlocking

” tab of

DPS profile

,

choose “

Ignored

” for “

Motion

” parameter, as follow:

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• Logic Function AND

TRUE

FALSE

INV

TRUE

FALSE

INV

FALSE

INV

FALSE

INV

AND

(7)

• Logic Function OR

TRUE

FALSE

INV

TRUE

FALSE

TRUE

FALSE

INV

TRUE

INV

OR

(8)

• Logic Function NOT

TRUE

FALSE

INV

FALSE

TRUE

INV

NOT

(9)

• Logic Function XOR

TRUE

FALSE

INV

TRUE

FALSE

TRUE

INV

FALSE

TRUE

FALSE

INV

XOR

(10)

• Logic Function BISTABLE (RS)

Properties :

-

Transition detection

- Q is SET when SET input goes from 0 to 1

- Q is RESET when RESET input goes from 0 to 1

-

Reset has priority on Set

This function is working like this up to PACiS V4.5.0

(11)

• Logic Function BISTABLE (RS)

Properties :

-

State detection

- Q is SET when SET input 1

- Q is RESET when RESET input 1

-

Reset has priority on Set

!

This function is working like this since PACiS V4.5.1

-

Q-1 is the previous value or the value before C264 Init

(after DB change only = 0)

Set

Reset

Q

1

0

1

0

1

0 Q-1

INV

(12)

• Logic Function TON

Output delayed

Pick-up Timer

Input

Output

INV

Timer stops

INV

1

0

1

0

(13)

• Logic Function TOFF

Drop-off output

Drop-off timer

INV

Timer stops

INV

Input

Output

1

0

1

0

(14)

• Logic Function nMPS

nMPS MASK is used for Fast Load Shedding. It reads an MPS status and

according on boolean values of the gate will output 1 or 0 depending on

MPS status

(15)

• Timer & Boolean Settings

1) Possibility to dynamically change TON/TOFF timer value

using a settable

input.

2) Possibility to create a fixed Boolean value

that can be dynamically

changed

by setting.

3) These parameters are configured in SCE then appears in C264 setting file

which can be readable using MiCOM S1 PACiS.

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• Content

General Features

PSL Creation

(17)

• Add / Configure a PSL (1)

1) PSL =

FBD Automation

can be added at

Substation

,

Voltage Level

,

Bay

,

Module

level in

Electric

hierarchy.

FBD Automation :

browse “User Function” in “Objects Entry”

2) Define PSL Inputs and Outputs under FBD Automation and link to

datapoint

(18)

• Add / Configure a PSL (2)

3) FBD with Inputs and outputs linked to datapoints :

FBD Inputs :

using SPS, DPS, …

FBD Output :

producing SPS

Runs on PLC :

for substation, voltage level PSL, define on

which C264 PSL is executed

4) FBD Edition

(19)

• PSL Edition (1)

1) FBD Editor :

FBD Inputs

FBD Output

Logic Functions

(20)

• PSL Edition (2)

2) FBD Construction (1):

1) Select by clicking on

left mouse button,

2) click again to put it

on the desired place

1) Select point to link by

clicking to the left

mouse button,

2) Keep the left mouse

pressed to link two

points

3) when “white” stroke,

release mouse

(21)

• PSL Edition (3)

2) FBD Construction (2):

to invert input click on

the right button and

choice

“toggle negation”

to create connection

click on the right

button and choice

“insert H/VC”

to create new input

click on the right

button and choice

(22)

• Save PSL

1) PSL Saving :

Coherence check done at FBD saving

FBD Status :

computed by SCE

-

correct

= no conception error inside editor

-

failure / modified

= conception error inside

(23)

• Add Timer setting

1)

To create a settable timer value, add an

FBD timer

object in your

automation.

2)

Set the

default, min, max and step

values.

3)

Set if this parameter is

visible & editable

or

visible & not editable

in

MiCOM S1

4)

Edit your FBD and link your FBD Timer to the PT input of TON/TOFF

gate

(24)

• Add Boolean setting

1)

To create a settable boolean value, add an

FBD Boolean

object in

your automation.

2)

Set the

default

value

, true

and

false

labels.

3)

Set if this parameter is

visible & editable

or

visible & not editable

in

MiCOM S1.

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• Modify Timer & Boolean Values

1)

Start MiCOM S1 PACiS

and open C264 setting file from zip

package generated by SCE.

2)

Start WFTPD

software (ftp server)

3)

FBD Timers and FBD Boolean will appears as following :

4)

You can so modify values according to SCE configuration.

5)

Send new values

(26)

• Multi-C264 automation

1) as PSL Inputs :

-

SPS, DPS, MPS coming from another C264

2) C264 exchanges :

-

GOOSE transmission

C264 executing PSL

“has for IEC Server”

the C264 sending

information to it, with property

“Goose only”

(27)

Schneider Electric- CS&P – C264 PSL 1 Interlock Configuration – E01

• Content

General Features

PSL Creation

(28)

• Add an Interlocking equation

1) Interlocks are added at

SPC DPC

level

Close Intlk SPS :

typed information, result of a FBD

when SET => control is allowed

2) SPC Interlocking

Close / Open Intlk SPS :

typed information, result of a FBD

when SET => control is allowed

3) DPC Interlocking

Intlk viol. SPS :

typed information which is SET if a control is

refused due to interlock equation.

This is used for some SCADA which have no

possibility to know the reason of a NACK

(ex: Modbus protocol).

(29)

• Configure an Interlocking equation (1)

1) Interlocks are Mini PSL, define inputs (no output, output is the interlock

SPS) and link to datapoints

Close Intlk SPS :

typed information, result of a FBD

FBD Interlock :

runs on PLC

FBD Inputs :

(30)

• Configure an Interlocking equation (2)