• No results found

HIGH LEVEL MODELLING OF REAL TIME TRAFFIC LIGHT CONTROLLER ADITYA MANDLOI

N/A
N/A
Protected

Academic year: 2020

Share "HIGH LEVEL MODELLING OF REAL TIME TRAFFIC LIGHT CONTROLLER ADITYA MANDLOI"

Copied!
7
0
0

Loading.... (view fulltext now)

Full text

(1)

HIGH LEVEL MODELLING OF REAL

TIME TRAFFIC LIGHT CONTROLLER

ADITYA MANDLOI

Medicaps Institute of Technology and Management, Indore, Madhya Pradesh, India

[email protected]

RAJNIKANT

Medicaps Institute of Technology and Management, Indore, Madhya Pradesh, India

[email protected]

Abstract:

The objective of this paper is to design and implement traffic control system. The system developed is able to sense the presence of vehicles within certain range by setting the appropriate duration for the traffic signals to react accordingly. By employing logical functions to calculate the appropriate timing for the signals to illuminate, the system can help to solve the problem of traffic congestion. The use of FPGAs (Field Programmable Gate Arrays) is an interesting new phenomenon in VLSI development. FPGAs offer all of the features needed to implement most complex designs. Hardware simulation tests were successfully performed on the algorithm implemented into a FPGA (Field Programmable Gate Arrays). The main object of the paper is to design a Real Time Traffic Light Controller (RTTLC) using VHDL and implement the RTTLC in XILINX SPARTAN - 3 FPGA.

Keywords: State Machine; FPGA; Road traffic; VHDL; Register transfer level.

1. Introduction

Today’s Traffic Light Controllers (TLC) are based on microcontroller and microprocessor. These TLC have limitations because it uses the pre-defined hardware, which is functioning according to the program that does not have the flexibility of modification on real time basis. Due to the fixed timing of Green, Yellow and Red signals the waiting time is more and vehicles uses more fuel [1]. To make traffic light controlling more efficient, this work presents a new technique called as "Real time traffic light controller". This makes the use of Sensor Networks along with FSM. The traffic light control is state machines with two synchronous input signals (DETECT and RESET) and six synchronous output signals (NSG, NSY, NSR, EWG, EWY, EWR) that control the traffic signal lights. The timings of Red, Green lights at each crossing of road will be intelligently decided based on the total traffic on all adjacent roads.

Consider the intersection of a busy highway with load sensors and traffic lights as shown in fig 1. The sensor detects the traffic on the highway and accordingly it generates output signal for the controller. Controller controls the traffic signals according to inputs given by the sensors Thus; optimization of traffic light switching increases road capacity and traffic flow, and can prevent traffic congestions. The performance of the real time Traffic Light Controller is compared with the Fixed Mode Traffic Light Controller. It is observed that the proposed Traffic Light Controller is more efficient than the conventional controller in respect of less waiting time and more distance travelled by average vehicles. Moreover, the designed system has simple architecture, fast response time, user friendliness and scope for further expansion.

(2)

2. Theory

The traffic in road crossings/junctions is controlled by switching ON/OFF Red, Green & Yellow lights in a particular sequence. The Traffic Light Controller is designed to generate a sequence of digital data called switching sequences that can be used to control the traffic lights of a typical four roads junction in a fixed sequence [2].

Fig. 1. Intersection – Placement of lights and sensors.

(3)

2.1. Finite State Machine (FSM)

The FSM is the main part of traffic light controller. It responds to the input signals provided by the input handling module and provides the output and control signals needed to make the system function [5]. in this design, RTTLC uses a standard two process finite state machine where one process is used to change states on every clock cycle while the other process is used to combinatorial calculate what the next state should be based on the current inputs and the current state.

2.2. State diagram of RT-TLC

3. Overview of FPGA Based RTTLC

The main objective of this paper is to build and verify the design and understand the concept. The main theme is to build a hardware device that has:

(1)The ability to collect the information of the busy tracks by sensors and providing the output to FPGA. (2)The ability to take decision against the information and change the time according to the priorities [3]. 3.1. Advantages of FPGA

In FPGA implementation the following extra features can be provided. (1) The switching sequences can be varied.

(2) The timings of switching sequence can be controlled in software

Fig. 3. State diagram of Real Time Traffic Light Controller

(4)

4. System Block Diagram

5. SOFTWARE

The design and simulation of the Traffic Light Controller can be performed using Modelsim. Also the timings of various signals can be verified. Then the controller can be implemented in XILINX Spartan-3. Figure 5 shows simulation results.

Fig. 4. Block diagram of Real time Traffic Light Controller

(5)

6. Simulation results

(a)

(b)

(c)

7. Hardware Implementation

The Hardware of traffic light controller consists of Xilinx FPGA BOARD as traffic light controller, clock generator, buffer and LED’S.

a) Synthesis report:

Synthesizing Unit <traffic>. Related source file is "asd.v".

(6)

Found finite state machine <FSM_0> for signal <state>. --- States : 6 Transitions : 16 Inputs : 4 Outputs : 9

4-bit adder : 1

25-bit up counter : 1 4-bit register : 1 6-bit register : 1 4-bit comparator l : 2 b) RTL schematic:

This figure 6 shows RTL schematic of the design. This RTL show the gate level simulation of the proposed design.

(7)

8. Conclusions

In this paper, we have used Mealy based Finite state machine to design an efficient and intelligent traffic light controller. Mealy machines are used to implement the system because outputs signal are controlled by the inputs signals. The language used for the implementation is VHDL with mixed modeling style. The design is tested on Spartan-3 xc3s200 FPGA development kit. Total memory usage is 105456 kilobytes.

References

[1] Z. Yuye and Y. Weisheng,( 2009) “Research of Traffic Signal Light Intelligent Control System Based On Microcontroller,” First International Workshop on Education Technology and Computer Science.

[2] W. M. E. Medany and Mr Hussain, (2007)“FPGA-based Advanced Real Traffic Light Controller System Design,” IEEE International workshop on Intelligent Data Acquisition Computing Systems: Technology and Applications, 6-8 September, Dortmund, Germany. [3] FPGA Design Tutorial, Copyright © 1-CORE Technologies,(2004-2009). [Online]. Available:

http://www.1 core.com/library/digital/fpga-design-tutorial/quick-startguide.

[4] P. P. Chu,( 2008) “FPGA Prototyping by VHDL Examples-Xilinx Spartan-3 Version,” John Wiley and Sons,

[5] Programmable Logic Design (Quick Start Handbook), Xilinx Copyright 2002-2006, Online]. Available: http://www.xilinx.com/ publications/products/ cpld/logic_handbook.pdf

[6] W. Bolton, (2000), “Programmable Logic Controllers”. Second edition.

[7] Alan J Crispin,(1997),”Programmable Logic Controller and their Engineering applications”, second edition

Figure

Fig. 1.   Intersection – Placement of lights and sensors.
Fig. 3.  State diagram of Real Time Traffic Light Controller
Fig. 4.   Block diagram of Real time Traffic Light Controller
Fig. 6.   Register transfer schematic of  Real time Traffic Light Controller

References

Related documents

citratus did not cause significant positive differences in the markers of renal function and damage at structural level such as GFR, sodium and potassium

within an individual drops very fast, as the number of diseases increase. That is the reason why the term expo- nential nature for chronic disease count is being used. Due to

“Some, like migrating birds, can survive long periods without sleeping without sleeping?.

Based on the references, the design of database table related with the process and the study result generally has similarity, that is using 4 main tables which are related

The paper presents the case of a software development team forced by circumstances to use two bug tracking systems in parallel in a pre-release phase; the consequences of

dummy would do a good job of capturing the part of educational attainment that is unrelated to innate parental characteristics, or changes in these characteristics over time. Such

Purpose: We examined risk of myocardial infarction and all-cause death associated with the extent of coronary artery disease ascertained by coronary angiography in patients

TES(%) = ⅀ X100 , avec TES : taux d’émergence du striga à un temps donné en pourcent, SEv : le nombre de plants du striga émergés d’une variété et NSE : total de plants