Protocol Driven Interface Validation Based On
Processor Emulation Test
Presenter: Jan Heiber ([email protected])
1 2 3
Status of Bus Interface Testing Intro - µP Assisted Procedures Available System Solutions
Presentation Contents
4 Summary and Outlook
Facts on Interface Testing using BScan
Boundary Scan is well proven for testing digital edge connector signals Boundary Scan resources are required on both ends, directly or buffered
Mature ATPG and Pin-Level diagnostic tools are available
AC coupled and serial high speed interfaces are testable by IEEE1149.6 Boundary Scan must be implemented on chip and board level
Static/slow speed testing only, limited coverage for dynamic faults
Background Information
TAP
I/F Signals BScan
IC
IEEE1149.1/.6 Signals
Edge connector
Paradigm change for I/F technologies …
Rapid growing GBit bus applications for high speed Communication Bus speed is doubling every 36 months average
On-Chip Bus I/F with limited low level protocol access and no dot6 External PHY typically doesn’t support dot6
2000 - 2015
Bus speed [GBit]
0,1
1
10
100
#GBit applications
PCIe 4.0 Thunderbolt 10GigE USB3.0 PCIe1.0 1GigE USB2.0
Fault Coverage trends via IEEE 1149.1/.6
Fault coverage for Bus I/F test on modern boards via IEEE1149.1/.6 is declining continuously.
This is caused by growing use of GBit I/F
199x 200x 201x
Average real world BScan Fault coverage quality for digital bus I/F
Critical Trend
Situation
Fault coverage
Searching for answers…
Current Test Problems
Substitution of parallel bus I/F by serial wire architectures
Continuously growing speed in the domain of GBit transfers
Routing and testing of GBit signals becomes critical like RF signals Digital failure models getting non
effective due to analogue failure nature Boundary Scan via dot6 is typically not available
New IEEE standards could solve the problem but they are not available yet
Some Thoughts …
Conclusions
Testing of modern I/F with serial GBit architecture via BScan is typically impossible Key challenges are the high speed and the analogue
nature of signal connections
Features like predictive fault
coverage, ATPG and precise
diagnostics are needed
2 Intro - µP Assisted Procedures
Boundary Scan vs. Processor Emulation
µP Emulation I/F Boundary Scan I/F
• Static pin electronics
• BScan cells define vectors
• Serially controlled pin interface
• Scalable number of pins
• Arbitrary static signal timing
• Dynamic pin electronics
• µP defines vectors
• Parallel controlled pin interface
• Fixed number of pins
• Rigid dynamic signal timing
Interconnection of µP Core and Bus I/F
Test Access ready by design
No special DfT rules necessary
Real Time functional Test via protocol
Advanced diagnostics tests possible
External Loop back or dedicated H/W
Pro‘s
On-Chip Resources JTAG TAP
µP Core
Embedded Flash H/S Bus I/F Legacy Bus I/F Legacy I/O Ports
System Bus I/F
External Bus Devices
Flash Components SRAM / DRAM Peripheral I/O Ports H/S Bus I/F
Aux Resources
Control Hardware
External Loop back
Bus I/F
Test
Hardware
Method by emerging standard IEEEP1687
IEEE1149.1 / IEEE1687 Access
IEEE 1687 controlled Bit Error Rate Tester (BERT) as a
embedded Instument
Signal validation and Interconnection Test of
Interface by embedded Test Instrumentation compliant to IEEE1687
TAPI/F Signals
Edge connector
External Loop back
Progress with handicaps …
Conclusions
Emulation Test offers the
needed test speed but need
handling of protocol layers
Potential fault coverage is
higher than BScan Test but
diagnostics quality is lower
Need for System solutions to
support advanced Emulation
Test and emerging standards
3 Available System Solutions
Solution #1: Special coded Test Routine
JTAG Emulator
Executable
Test Routine Development with native s/w Tool chain
Debugging of s/w and h/w via Emulator
Download into Flash and Program Execution
On-Chip Resources JTAG TAP
µP Core
Embedded Flash H/S Bus I/F Legacy Bus I/F Legacy I/O Ports
System Bus I/F
External Bus Devices
Flash Components SRAM / DRAM Peripheral I/O Ports H/S Bus I/F
Aux Resources
External Loop back
O/S and
PC with O/S and
Bus I/F
Solution #2: Use of native Firmware + HIL
JTAG Emulator
Executable
Firmware Development with native s/w Tool chain
Hardware In the Loop Test via external ATE Download into Flash and
Program Execution
On-Chip Resources JTAG TAP
µP Core
Embedded Flash H/S Bus I/F Legacy Bus I/F Legacy I/O Ports
System Bus I/F
External Bus Devices
Flash Components SRAM / DRAM Peripheral I/O Ports H/S Bus I/F
ATE for
HIL test
Solution #3: Advanced I/F test with ATPG
On-Chip Resources JTAG TAP
µP Core
Embedded Flash H/S Bus I/F Legacy Bus I/F Legacy I/O Ports
System Bus I/F
External Bus Devices
Flash Components SRAM / DRAM Peripheral I/O Ports H/S Bus I/F
Aux Resources
protocol External protocol
test H/W
Test Program
ATPG for protocol Test Generation
Failure diagnostics on Pin group level by system
software
Program Execution using the µP Core and external
H/W in interaction Advanced JTAG/BScan
Hardware
Comparison of System Solutions
Features
Unified BScan/Emulation test commands True Interlaced BScan/Emulation operations Predictive Fault coverage calculation Automated Test Program Generation Use of native MCU tool chain
Manually s/w Source coding
Automated Pin group level Diagnostics
Unified hardware for BScan and Emulation Total Programming and Test execution time Flash firmware programming needed
System class
Special coded
Test Routine Native Firm- ATPG ware + HIL
no no yes yes
no no
no no High
yes
yes yes no no
possible possible
yes yes low no possible for
HIL Tests no yes yes
no no
no no High
yes
4 Summary and Outlook
Higher Test Quality …
Boundary Scan + Emulation Test
Project Development Time
Test Coverage
Digital Interconnections Functional Real Time test of
Gbit interconnections
Processor Emulation enables higher fault coverage and pin group level diagnostics
Boundary Scan
