In this example the length of the vector is determined by D length and used for the index variable.

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Technische Fachhochschule Berlin / University of Applied Sciences Prof. Detlef Heinemann

EDA4c - VHDL Loops

Loops

Loop statements are a catagory of control structures that allow you to specify repeating sequences of behavior in a circuit. There are three primary types of loops in VHDL: for loops, while loops, and infinite loops.

For Loop

The for loop is a sequential statement that allows you to specify a fixed number of iterations in a behavioral design description. The following architecture demonstrates how a simple 8-bit parity generator can be described using the for loop:

library ieee;

use ieee.std_logic_1164.all; entity parity10 is

port(D: in std_logic_vector(0 to 9); ODD: out std_logic);

constant WIDTH: integer := 10;

end parity10;

architecture behavior of parity10 is begin

process(D)

variable otmp: Boolean; begin

otmp := false;

for i in 0 to D'length - 1 loop if D(i) = '1' then

otmp := not otmp; end if; end loop; if otmp then ODD <= '1'; else ODD <= '0'; end if; end process; end behavior;

In this example the length of the vector is determined by “D’length” and used for the index variable.

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EDA4c - VHDL Loops

separately declare the index variable.

The index variable and values specified for the loop do not have to be numeric types and values. In fact, the index range specification does not even have to be represented by a range. Instead, it can be represented by a type or sub-type indicator. The following example shows how an enumerated type can be used in a loop statement:

architecture looper2 of my_entity is

type stateval is Init, Clear, Send, Receive, Error; -- States of a machine

begin

. . . process(a) begin

for state in stateval loop case state is when Init => ... when Clear => ... when Send => ... when Receive => ... when Error => ... end case; end loop; end process; . . . end looper2;

For loops can be given an optional name, as shown in the following example:

loop1: for state in stateval loop

if current_state = state then

valid_state <= true; end if;

end loop loop1;

The loop name can be used to help distinguish between the loop index variable and other similarly-named objects, and to specify which of the multiple nested loops is to be terminated (see Loop

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EDA4c - VHDL Loops While Loop

A while loop is another form of sequential loop statement that specifies the conditions under which the loop should continue, rather than specifying a discrete number of iterations. The general form of the while loop is shown below:

architecture while_loop of my_entity is begin

. . .

process(. . .) begin . . .

loop_name: while (condition) loop -- repeated statements go here end loop loop_name;

. . . end process; . . .

end while_loop;

Like the for loop, a while loop can only be entered and used in sequential VHDL statements (i.e., in a process, function or procedure). The loop name is optional.

The following example uses a while loop to describe a constantly running clock that might be used in a test bench. The loop causes the clock signal to toggle with each loop iteration, and the loop condition will cause the loop to terminate if either of two flags (error_flag or done) are asserted. process

begin

while error_flag /= ‘1’ and done /= '1’ loop Clock <= not Clock;

wait for CLK_PERIOD/2; end loop;

end process;

Note: Although while loops are quite useful in test benches and simulation models, you may have trouble if you attempt to synthesize them. Synthesis tools may be unable to generate a hardware representation for a while loop, particularly if the loop expression depends on non-static elements such as signals and variables. Because support for while loops varies widely among synthesis tools, I recommend that you not use them in synthesizable design descriptions.

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EDA4c - VHDL Loops Infinite Loop

An infinite loop is a loop statement that does not include a for or while iteration keyword (or

iteration scheme). An infinite loop will usually include an exit condition, as shown in the template

below:

architecture inifinite_loop of my_entity is begin . . . process(. . .) . . . loop_name: loop . . .

exit when (condition); end loop loop_name; end process;

. . .

end infinite_loop;

An infinite loop using a wait statement is shown in the example below. This example exhibits exactly the same behaviour as the while loop shown previously:

process begin

loop

Clock <= not Clock; wait for CLK_PERIOD/2;

if done = '1' or error_flag = '1' then exit;

end if; end loop;

end process;

As with a while loop, an infinite loop probably has no equivalent in hardware and is therefore not synthesizable.

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EDA4c - VHDL Loops

condition has been reached. The three types of loops previously described all have the ability to be terminated prematurely. Loop termination is performed through the use of an exit statement. When an exit statement is encountered, its condition is tested and, if the condition is true, the simulator skips the remaining statements in the loop and all remaining loop iterations, and continues execution at the statement immediately following the end loop statement.

The following example demonstrates how loop termination can be used to halt a sequence of test vectors that are being executed when an error is detected:

for i in 0 to VectorCount loop

ApplyVector(InputVec(i), ResultVec);

exit when CheckOutput(OutputVec(i), ResultVec) = FatalError;

end loop;

The exit condition is optional; an exit statement without an exit condition will unconditionally terminate when the exit statement is encountered. The following example shows an unconditional exit termination specified in combination with an if-then statement to achieve the same results as in the previous example:

for i in 0 to VectorCount loop

if CheckOutput(OutputVec(i), ResultVec) = FatalError then exit;

end loop;

When multiple loops are nested, the exit statement will terminate only the innermost loop. If you need to terminate a loop that is not the innermost loop, you can make use of loop labels to specify which loop is being terminated. The following example shows how loop labels are specified in exit statements:

LOOP1: while (StatusFlag = STATUS_OK) loop

GenerateSequence(InputVec,OutputVec,VectorCount,Seed);

LOOP2: for i in 0 to VectorCount loop

ErrStatus := CheckOutput(OutputVec(i), ResultVec) = TestError; if ErrStatus = ERR_COMPARE then

ReportError(); exit LOOP2;

elsif ErrStatus = ERR_FATAL then ReportFatal();

exit LOOP1; end if;

end loop LOOP2;