Reliability Test plan development for electronic components

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Reliability Test plan

development for

electronic components

Kees Revenberg

Co-founder/MD

Reliability Seminar @ Electronics & Automation

May 30

th

₂₀₁₃

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Outline



Introduction



Test plan development



Environments and applications



Test methods and standards



Execution and data processing



Examples

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Introduction



Independent Test & Diagnostics of Microelectronics



Services cover component to module & small system level



Large IDM, Fabless Semi, Design Centers, OEM and R&D



Founded in 1993, ISO-9001 certified by Lloyds Register



First RvA ISO-17025 accreditation on electronics test (L388)



1750m² central lab & offices at Kennispark Enschede



41 employees with gen/Tech/BSc*/MSc*/PhD* (*=>60%)

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Introduction



Electronic component penetration ongoing



Highly complex product to manufacture



Millions/week of devices at sub 100nm precision



100+ devices per system at 100k+/week



Strict manufacturing process control

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Big impact of application environment



Unknown customer handling activity



Good pro-active test planning

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Test plan development



Product description



Manufacturing Flow and Supply Chain



Application Environments and Mission



FME(C)A and design robustness analysis



Design for tests implementation



Test program preparation



Organization and Responsibilities



Test plan description



Customer feedback / approval

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Test plan development



Product description



Detailed functional description



DC/AC parametric specification



Package Outline Drawing + pin list

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Manufacturing Flow and Supply Chain



Detailed description of manufacturing process

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Detailed description of materials and suppliers



SPC program definition for process control

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Test plan development



Application Environments and Mission



Definition of worse case End User environment



Definition of product mission and expected life



FME(C)A and design robustness analysis



Product split in all essential blocks and assembly steps



List of potential hazards and/or failure modes



Consequences of malfunction with grade



Prime test methods to show or stress the hazards



List of necessary tools and techniques

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Test plan development



Design for tests implementation



On chip / On board features for with JTAG/SPI test



Support electronics for stress test status monitoring



Health monitoring during stress test and operation



Test program preparation

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Organization and Responsibilities



Test plan description



Standard vs. Custom stress tests

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Customer feedback / approval

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Environments and applications



Application environments has big impact



User skills can destroy a product



Certain applications may result in life

threatening situations



Health: pacemaker / narcosis equipment



Automotive: airbag / steering control



Aerospace: motor control / fly-by-wire



There is an uncertainty in the final product

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Test methods and standards



ISO



IEC



MILSTD883/750/202



JEDEC / J-STD



JIS – EN – NEN



AEC-Q100/101/200



IPC600/610

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Customer based



Application based

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Other

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Detailed description of method and tools



Intra lab exchange of results

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Joint Electron Devices Engineering Council

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Founded in 1958



Part of Electronic Industries Alliance



1999



independent organization

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JEDEC Solid State Technology Association

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

Detailed test method description

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Better focus on micro-electronics

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World Wide acceptance in industry

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Good correlation with accredited labs

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Methods and programs defined

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Joint standards with ESDA and IPC

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www.jedec.org

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Stress test driven qualification of IC’s

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Required stress test

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Pass/Fail criteria acc. LTPD table

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Qualification and Re-qualification after change

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Device specific tests

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ESD

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Latch Up

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Parametric

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Device qualification requirements

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Hermetic package requirement

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AEC test standards

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AEC-Q100-Q101-Q200

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Automotive Industry driven

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1995 Q100 version A issued



Free on www.aeccouncil.com



J1879



Handbook for Robustness Validation of Semiconductor Devices

in Automotive Applications



Joint SAE-ZVEI-JSAE-AEC plan



Info on www.sae.org

AEC-Q100 founders, left to right:

Earl Fisher (FORD)

Gerald Servais (Delco/GM) Jerry Jennings (Chrysler) Robert Knoell (FORD)

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AEC Q100 test standards



Test Group A: Chip + Package related stress

 THB  HAST; PC  UHAST; PreConditioning stress prior to GpA tests

 Power Temperature Cycling for multiple hot/cold starts, linear K-ramp



Test Group B: Chip accelerated life test + Safe Launch

 Functional reliability in an accelerated test environment

 Due to new operational temperatures temperatures go up to +175°C

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Test Group C: Assembly related tests

 Lot by Lot selection for destructive mechanical properties

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Test Group D: Wafer process related tests

 Metal and Via structure  EM stress

 Gate Oxide stability  TDDB

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AEC Q100 test standards

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Test Group E1: Electrical parametric tests

 Statistical review of DC and AC parameters

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Test Group E2: Electrical parametric tests

 ESD/LU phenomena protection circuitry, strong relation to JEDEC/ESDA

 Dedicated test for CMOS under lightning strike effects  FIGL test

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Test Group F: Design process related tests

 Review of statistical device data

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Test Group G: Hermetic package tests

 Drop, Shock and Vibration stress tests

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J1879 Robustness Validation

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J1879 Matrix

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Subsystem



Material

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Failure Mechanism

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Failure Cause

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Failure Mode

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Detection Mode

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Char. of Degradation

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Affecting Ops Cond.

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Required Test structure

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Mitigation Technique

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Stress Method



Stress Method standard

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Acceleration Model

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Acc. Model standard ref. The vertical axis is a list of wide range of potential defects

Reliability Test plan development for electronic components