IA-32 Intel Architecture Software Developer s Manual

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IA-32 Intel® Architecture Software Developer’s Manual

Volume 1:

Basic Architecture

NOTE: The IA-32 Intel Architecture Software Developer’s Manual consists of three volumes: Basic Architecture, Order Number 245470-007;

Instruction Set Reference, Order Number 245471-007; and the System Programming Guide, Order Number 245472-007.

Please refer to all three volumes when evaluating your design needs.

2002

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or

“undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel’s IA-32 Intel® Architecture processors (e.g., Pentium® 4 and Pentium® III processors) may contain design defects or errors known as errata. Current characterized errata are available on request.

Intel, Intel386, Intel486, Pentium, Intel Xeon, Intel NetBurst, MMX, Intel Celeron, and Itanium are trademarks or registered trademarks of Intel Corporation and its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation P.O. Box 7641

Mt. Prospect IL 60056-7641 or call 1-800-879-4683

or visit Intel’s website at http://www.intel.com

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DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE . . . 1-4 1.5. NOTATIONAL CONVENTIONS . . . 1-6 1.5.1. Bit and Byte Order . . . .1-6 1.5.2. Reserved Bits and Software Compatibility . . . 1-7 1.5.3. Instruction Operands . . . 1-8 1.5.4. Hexadecimal and Binary Numbers . . . 1-8 1.5.5. Segmented Addressing . . . .1-8 1.5.6. Exceptions . . . .1-9 1.6. RELATED LITERATURE . . . 1-9

CHAPTER 2

INTRODUCTION TO THE IA-32 INTEL ARCHITECTURE

2.1. BRIEF HISTORY OF THE IA-32 ARCHITECTURE. . . 2-1 2.2. THE INTEL PENTIUM^® 4 PROCESSOR . . . 2-5 2.3. THE INTEL XEON™ PROCESSOR . . . 2-6 2.3.1. Streaming SIMD Extensions 2 (SSE2) Technology . . . .2-6 2.4. MOORE’S LAW AND IA-32 PROCESSOR GENERATIONS . . . 2-7 2.5. THE P6 FAMILY MICRO-ARCHITECTURE . . . 2-9 2.6. THE INTEL NETBURST™ MICRO-ARCHITECTURE . . . 2-11 2.6.1. The Front End Pipeline . . . .2-13 2.6.2. The Out-of-order Core . . . .2-14 2.6.3. Retirement . . . .2-14 2.7. HYPER-THREADING TECHNOLOGY . . . 2-15 2.7.1. Hyper-Threading Technology Implementations. . . .2-17

CHAPTER 3

BASIC EXECUTION ENVIRONMENT

3.1. MODES OF OPERATION . . . 3-1 3.2. OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT . . . 3-2 3.3. MEMORY ORGANIZATION. . . 3-5 3.3.1. Modes of Operation vs. Memory Model. . . 3-7 3.3.2. 32-Bit vs. 16-Bit Address and Operand Sizes . . . 3-7 3.3.3. Extended Physical Addressing . . . .3-8 3.4. BASIC PROGRAM EXECUTION REGISTERS . . . 3-8 3.4.1. General-Purpose Registers . . . 3-8 3.4.2. Segment Registers . . . .3-10 3.4.3. EFLAGS Register . . . .3-12 3.4.3.1. Status Flags . . . .3-13 3.4.3.2. DF Flag . . . .3-14

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PAGE 3.4.4. System Flags and IOPL Field . . . .3-15 3.5. INSTRUCTION POINTER . . . 3-16 3.6. OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES. . . 3-16 3.7. OPERAND ADDRESSING. . . 3-17 3.7.1. Immediate Operands . . . 3-17 3.7.2. Register Operands . . . .3-18 3.7.3. Memory Operands. . . .3-18 3.7.3.1. Specifying a Segment Selector. . . .3-19 3.7.3.2. Specifying an Offset . . . .3-20 3.7.3.3. Assembler and Compiler Addressing Modes . . . .3-22 3.7.4. I/O Port Addressing . . . .3-22

CHAPTER 4 DATA TYPES

4.1. FUNDAMENTAL DATA TYPES . . . 4-1 4.1.1. Alignment of Words, Doublewords, Quadwords, and Double Quadwords . . . .4-2 4.2. NUMERIC DATA TYPES . . . 4-3 4.2.1. Integers . . . .4-4 4.2.1.1. Unsigned Integers. . . 4-4 4.2.1.2. Signed Integers. . . .4-4 4.2.2. Floating-Point Data Types . . . .4-5 4.3. POINTER DATA TYPES . . . 4-7 4.4. BIT FIELD DATA TYPE . . . 4-7 4.5. STRING DATA TYPES . . . 4-8 4.6. PACKED SIMD DATA TYPES . . . 4-8 4.6.1. 64-Bit SIMD Packed Data Types. . . .4-8 4.6.2. 128-Bit Packed SIMD Data Types. . . .4-9 4.7. BCD AND PACKED BCD INTEGERS . . . 4-10 4.8. REAL NUMBERS AND FLOATING-POINT FORMATS. . . 4-11 4.8.1. Real Number System . . . .4-12 4.8.2. Floating-Point Format . . . .4-12 4.8.2.1. Normalized Numbers . . . 4-14 4.8.2.2. Biased Exponent. . . .4-14 4.8.3. Real Number and Non-number Encodings . . . 4-14 4.8.3.1. Signed Zeros . . . 4-16 4.8.3.2. Normalized and Denormalized Finite Numbers . . . 4-16 4.8.3.3. Signed Infinities . . . .4-17 4.8.3.4. NaNs. . . .4-17 4.8.3.5. Operating on SNaNs and QNaNs. . . .4-17 4.8.3.6. Using SNaNs and QNaNs in Applications . . . .4-18 4.8.3.7. QNaN Floating-Point Indefinite . . . .4-19 4.8.4. Rounding . . . 4-19 4.8.4.1. Rounding Control (RC) Fields. . . .4-21 4.8.4.2. Truncation with SSE and SSE2 Conversion Instructions . . . .4-21 4.9. OVERVIEW OF FLOATING-POINT EXCEPTIONS. . . 4-21 4.9.1. Floating-Point Exception Conditions . . . .4-23 4.9.1.1. Invalid Operation Exception (#I) . . . 4-23 4.9.1.2. Denormal Operand Exception (#D) . . . 4-23 4.9.1.3. Divide-By-Zero Exception (#Z) . . . .4-24 4.9.1.4. Numeric Overflow Exception (#O) . . . .4-24

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PAGE 4.9.1.5. Numeric Underflow Exception (#U). . . 4-25 4.9.1.6. Inexact-Result (Precision) Exception (#P) . . . 4-26 4.9.2. Floating-Point Exception Priority . . . 4-27 4.9.3. Typical Actions of a Floating-Point Exception Handler . . . 4-28

CHAPTER 5

INSTRUCTION SET SUMMARY

5.1. GENERAL-PURPOSE INSTRUCTIONS . . . 5-2 5.1.1. Data Transfer Instructions . . . 5-2 5.1.2. Binary Arithmetic Instructions . . . 5-3 5.1.3. Decimal Arithmetic . . . 5-4 5.1.4. Logical Instructions . . . 5-4 5.1.5. Shift and Rotate Instructions . . . 5-4 5.1.6. Bit and Byte Instructions . . . 5-5 5.1.7. Control Transfer Instructions . . . 5-6 5.1.8. String Instructions . . . 5-7 5.1.9. Flag Control Instructions . . . 5-8 5.1.10. Segment Register Instructions. . . 5-8 5.1.11. Miscellaneous Instructions. . . 5-9 5.2. X87 FPU INSTRUCTIONS . . . 5-9 5.2.1. Data Transfer . . . 5-9 5.2.2. Basic Arithmetic . . . 5-10 5.2.3. Comparison . . . 5-11 5.2.4. Transcendental . . . 5-11 5.2.5. Load Constants . . . 5-12 5.2.6. x87 FPU Control . . . 5-12 5.3. X87 FPU AND SIMD STATE MANAGEMENT . . . 5-13 5.4. SIMD INSTRUCTIONS. . . 5-13 5.5. MMX INSTRUCTIONS . . . 5-15 5.5.1. Data Transfer Instructions . . . 5-15 5.5.2. Conversion Instructions . . . 5-16 5.5.3. Packed Arithmetic Instructions . . . 5-16 5.5.4. Comparison Instructions . . . 5-17 5.5.5. Logical Instructions . . . 5-17 5.5.6. Shift and Rotate Instructions . . . 5-17 5.5.7. State Management . . . 5-18 5.6. SSE INSTRUCTIONS . . . 5-18 5.6.1. SSE SIMD Single-Precision Floating-Point Instructions . . . 5-18 5.6.1.1. SSE Data Transfer Instructions . . . 5-18 5.6.1.2. SSE Packed Arithmetic Instructions . . . 5-19 5.6.1.3. SSE Comparison Instructions . . . 5-20 5.6.1.4. SSE Logical Instructions . . . 5-20 5.6.1.5. SSE Shuffle and Unpack Instructions . . . 5-20 5.6.1.6. SSE Conversion Instructions . . . 5-21 5.6.2. MXCSR State Management Instructions . . . 5-21 5.6.3. SSE 64-Bit SIMD Integer Instructions . . . 5-21 5.6.4. SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions . . . . 5-22 5.7. SSE2 INSTRUCTIONS . . . 5-22 5.7.1. SSE2 Packed and Scalar Double-Precision Floating-Point Instructions . . . 5-23 5.7.1.1. SSE2 Data Movement Instructions . . . 5-23 5.7.1.2. SSE2 Packed Arithmetic Instructions . . . 5-23 5.7.1.3. SSE2 Logical Instructions . . . 5-24

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PAGE 5.7.1.4. SSE2 Compare Instructions . . . 5-24 5.7.1.5. SSE2 Shuffle and Unpack Instructions. . . .5-25 5.7.1.6. SSE2 Conversion Instructions . . . .5-25 5.7.2. SSE2 Packed Single-Precision Floating-Point Instructions. . . .5-26 5.7.3. SSE2 128-Bit SIMD Integer Instructions . . . .5-26 5.7.4. SSE2 Cacheability Control and Instruction Ordering Instructions . . . .5-27 5.8. SYSTEM INSTRUCTIONS. . . 5-27

CHAPTER 6

PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS

6.1. PROCEDURE CALL TYPES . . . 6-1 6.2. STACK . . . 6-1 6.2.1. Setting Up a Stack. . . .6-2 6.2.2. Stack Alignment. . . .6-3 6.2.3. Address-Size Attributes for Stack Accesses . . . .6-3 6.2.4. Procedure Linking Information. . . .6-4 6.2.4.1. Stack-Frame Base Pointer . . . .6-4 6.2.4.2. Return Instruction Pointer . . . .6-4 6.3. CALLING PROCEDURES USING CALL AND RET . . . 6-4 6.3.1. Near CALL and RET Operation. . . 6-5 6.3.2. Far CALL and RET Operation . . . .6-5 6.3.3. Parameter Passing . . . .6-6 6.3.3.1. Passing Parameters Through the General-Purpose Registers . . . .6-6 6.3.3.2. Passing Parameters on the Stack . . . .6-7 6.3.3.3. Passing Parameters in an Argument List . . . .6-7 6.3.4. Saving Procedure State Information . . . .6-7 6.3.5. Calls to Other Privilege Levels . . . .6-7 6.3.6. CALL and RET Operation Between Privilege Levels . . . 6-9 6.4. INTERRUPTS AND EXCEPTIONS . . . 6-10 6.4.1. Call and Return Operation for Interrupt or Exception Handling Procedures . . . . 6-11 6.4.2. Calls to Interrupt or Exception Handler Tasks . . . 6-15 6.4.3. Interrupt and Exception Handling in Real-Address Mode . . . 6-15 6.4.4. INT n, INTO, INT 3, and BOUND Instructions . . . 6-15 6.4.5. Handling Floating-Point Exceptions. . . 6-16 6.5. PROCEDURE CALLS FOR BLOCK-STRUCTURED LANGUAGES. . . 6-16 6.5.1. ENTER Instruction. . . .6-17 6.5.2. LEAVE Instruction . . . .6-22

CHAPTER 7

PROGRAMMING WITH THE

GENERAL-PURPOSE INSTRUCTIONS

7.1. PROGRAMMING ENVIRONMENT FOR THE GENERAL-PURPOSE

INSTRUCTIONS 7-1 7.2. SUMMARY OF THE GENERAL-PURPOSE INSTRUCTIONS . . . 7-2 7.2.1. Data Movement Instructions . . . 7-3 7.2.1.1. General Data Movement Instructions . . . .7-3 7.2.1.2. Exchange Instructions . . . .7-4 7.2.1.3. Stack Manipulation Instructions . . . 7-6 7.2.1.4. Type Conversion Instructions . . . .7-8 7.2.2. Binary Arithmetic Instructions . . . .7-9 7.2.2.1. Addition and Subtraction Instructions . . . .7-9 7.2.2.2. Increment and Decrement Instructions. . . .7-9

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PAGE 7.2.2.3. Comparison and Sign Change Instruction . . . 7-10 7.2.2.4. Multiplication and Divide Instructions . . . 7-10 7.2.3. Decimal Arithmetic Instructions . . . 7-10 7.2.3.1. Packed BCD Adjustment Instructions . . . 7-11 7.2.3.2. Unpacked BCD Adjustment Instructions . . . 7-11 7.2.4. Logical Instructions . . . 7-12 7.2.5. Shift and Rotate Instructions . . . 7-12 7.2.5.1. Shift Instructions . . . 7-12 7.2.5.2. Double-Shift Instructions . . . 7-14 7.2.5.3. Rotate Instructions . . . 7-14 7.2.6. Bit and Byte Instructions . . . 7-16 7.2.6.1. Bit Test and Modify Instructions . . . 7-16 7.2.6.2. Bit Scan Instructions . . . 7-16 7.2.6.3. Byte Set on Condition Instructions . . . 7-16 7.2.6.4. Test Instruction . . . 7-17 7.2.7. Control Transfer Instructions . . . 7-17 7.2.7.1. Unconditional Transfer Instructions . . . 7-17 7.2.7.2. Conditional Transfer Instructions . . . 7-18 7.2.7.3. Software Interrupts . . . 7-21 7.2.8. String Operations . . . 7-22 7.2.8.1. Repeating String Operations. . . 7-23 7.2.9. I/O Instructions. . . 7-23 7.2.10. Enter and Leave Instructions . . . 7-24 7.2.11. EFLAGS Instructions . . . 7-24 7.2.11.1. Carry and Direction Flag Instructions . . . 7-24 7.2.11.2. Interrupt Flag Instructions . . . 7-25 7.2.11.3. EFLAGS Transfer Instructions . . . 7-25 7.2.11.4. Interrupt Flag Instructions . . . 7-26 7.2.12. segment Register Instructions . . . 7-26 7.2.12.1. Segment-Register Load and Store Instructions . . . 7-26 7.2.12.2. Far Control Transfer Instructions . . . 7-26 7.2.12.3. Software Interrupt Instructions . . . 7-26 7.2.12.4. Load Far Pointer Instructions . . . 7-27 7.2.13. Miscellaneous Instructions. . . 7-27 7.2.13.1. Address Computation Instruction . . . 7-27 7.2.13.2. Table Lookup Instructions . . . 7-27 7.2.13.3. Processor Identification Instruction . . . 7-27 7.2.13.4. No-Operation and Undefined Instructions. . . 7-27

CHAPTER 8

PROGRAMMING WITH THE X87 FPU

8.1. X87 FPU EXECUTION ENVIRONMENT . . . 8-1 8.1.1. x87 FPU Data Registers . . . 8-2 8.1.1.1. Parameter Passing With the x87 FPU Register Stack . . . 8-4 8.1.2. x87 FPU Status Register . . . 8-5 8.1.2.1. Top of Stack (TOP) Pointer. . . 8-5 8.1.2.2. Condition Code Flags . . . 8-5 8.1.2.3. x87 FPU Floating-Point Exception Flags . . . 8-6 8.1.2.4. Stack Fault Flag . . . 8-7 8.1.3. Branching and Conditional Moves on Condition Codes . . . 8-8 8.1.4. x87 FPU Control Word. . . 8-9 8.1.4.1. x87 FPU Floating-Point Exception Mask Bits . . . 8-10

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PAGE 8.1.4.2. Precision Control Field . . . .8-10 8.1.4.3. Rounding Control Field . . . .8-10 8.1.5. Infinity Control Flag . . . .8-11 8.1.6. x87 FPU Tag Word . . . .8-11 8.1.7. x87 FPU Instruction and Data (Operand) Pointers . . . 8-12 8.1.8. Last Instruction Opcode. . . .8-12 8.1.8.1. Fopcode Compatibility Mode . . . 8-12 8.1.9. Saving the x87 FPU’s State with the FSTENV/FNSTENV and

FSAVE/FNSAVE Instructions . . . .8-13 8.1.10. Saving the x87 FPU’s State with the FXSAVE Instruction . . . .8-15 8.2. X87 FPU DATA TYPES . . . 8-15 8.2.1. Indefinites . . . 8-17 8.2.2. Unsupported Double Extended-Precision Floating-Point Encodings and

Pseudo-Denormals . . . .8-17 8.3. X86 FPU INSTRUCTION SET . . . 8-19 8.3.1. Escape (ESC) Instructions . . . .8-19 8.3.2. x87 FPU Instruction Operands . . . .8-19 8.3.3. Data Transfer Instructions . . . .8-19 8.3.4. Load Constant Instructions . . . .8-21 8.3.5. Basic Arithmetic Instructions . . . .8-22 8.3.6. Comparison and Classification Instructions. . . .8-23 8.3.6.1. Branching on the x87 FPU Condition Codes . . . .8-25 8.3.7. Trigonometric Instructions . . . .8-26 8.3.8. Pi . . . .8-26 8.3.9. Logarithmic, Exponential, and Scale . . . .8-27 8.3.10. Transcendental Instruction Accuracy . . . .8-28 8.3.11. x87 FPU Control Instructions. . . .8-28 8.3.12. Waiting Vs. Non-waiting Instructions . . . .8-29 8.3.13. Unsupported x87 FPU Instructions . . . 8-30 8.4. X87 FPU FLOATING-POINT EXCEPTION HANDLING . . . 8-30 8.4.1. Arithmetic vs. Non-arithmetic Instructions . . . .8-31 8.5. X87 FPU FLOATING-POINT EXCEPTION CONDITIONS . . . 8-32 8.5.1. Invalid Operation Exception. . . 8-32 8.5.1.1. Stack Overflow or Underflow Exception (#IS). . . .8-33 8.5.1.2. Invalid Arithmetic Operand Exception (#IA) . . . 8-34 8.5.2. Denormal Operand Exception (#D) . . . 8-35 8.5.3. Divide-By-Zero Exception (#Z) . . . .8-35 8.5.4. Numeric Overflow Exception (#O) . . . .8-36 8.5.5. Numeric Underflow Exception (#U) . . . 8-37 8.5.6. Inexact-Result (Precision) Exception (#P). . . .8-38 8.6. X87 FPU EXCEPTION SYNCHRONIZATION . . . 8-39 8.7. HANDLING X87 FPU EXCEPTIONS IN SOFTWARE . . . 8-40 8.7.1. Native Mode . . . .8-40 8.7.2. MS-DOS* Compatibility Mode . . . .8-41 8.7.3. Handling x87 FPU Exceptions in software . . . 8-42

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PAGE CHAPTER 9

PROGRAMMING WITH THE INTEL MMX TECHNOLOGY

9.1. OVERVIEW OF THE MMX TECHNOLOGY. . . 9-1 9.2. THE MMX TECHNOLOGY PROGRAMMING ENVIRONMENT . . . 9-2 9.2.1. MMX Registers . . . 9-2 9.2.2. MMX Data Types . . . 9-3 9.2.3. Memory Data Formats . . . 9-4 9.2.4. Single Instruction, Multiple Data (SIMD) Execution Model . . . 9-4 9.3. SATURATION AND WRAPAROUND MODES . . . 9-5 9.4. MMX INSTRUCTIONS . . . 9-6 9.4.1. Data Transfer Instructions . . . 9-7 9.4.2. Arithmetic Instructions . . . 9-8 9.4.3. Comparison Instructions . . . 9-8 9.4.4. Conversion Instructions . . . 9-9 9.4.5. Unpack Instructions . . . 9-9 9.4.6. Logical Instructions . . . 9-9 9.4.7. Shift Instructions . . . 9-9 9.4.8. EMMS Instruction . . . 9-9 9.5. COMPATIBILITY WITH X87 FPU ARCHITECTURE . . . 9-10 9.5.1. MMX Instructions and the x87 FPU Tag Word . . . 9-10 9.6. WRITING APPLICATIONS WITH MMX CODE . . . 9-10 9.6.1. Checking for MMX Technology Support . . . 9-10 9.6.2. Transitions Between x87 FPU and MMX Code . . . 9-11 9.6.3. Using the EMMS Instruction . . . 9-12 9.6.4. Mixing MMX and x87 FPU Instructions . . . 9-12 9.6.5. Interfacing with MMX Code . . . 9-13 9.6.6. Using MMX Code in a Multitasking Operating System Environment . . . 9-13 9.6.7. Exception Handling in MMX Code . . . 9-14 9.6.8. Register Mapping. . . 9-14 9.6.9. Effect of Instruction Prefixes on MMX Instructions . . . 9-14

CHAPTER 10

STREAMING SIMD EXTENSIONS (SSE)

10.1. OVERVIEW OF THE SSE EXTENSIONS . . . 10-1 10.2. SSE PROGRAMMING ENVIRONMENT . . . 10-2 10.2.1. XMM Registers . . . 10-4 10.2.2. MXCSR Control and Status Register. . . 10-4 10.2.2.1. SIMD Floating-Point Mask and Flag Bits . . . 10-5 10.2.2.2. SIMD Floating-Point Rounding Control Field . . . 10-6 10.2.2.3. Flush-To-Zero . . . 10-6 10.2.2.4. Denormals Are Zeros . . . 10-6 10.2.3. Compatibility of the SSE Extensions with the SSE2 Extensions,

MMX Technology, and x87 FPU Programming Environments . . . 10-7 10.3. SSE DATA TYPES . . . 10-7 10.4. SSE INSTRUCTION SET . . . 10-8 10.4.1. SSE Packed and Scalar Floating-Point Instructions . . . 10-8 10.4.1.1. SSE Data Movement Instructions . . . 10-10 10.4.1.2. SSE Arithmetic Instructions . . . 10-10 10.4.2. SSE Logical Instructions . . . 10-12 10.4.2.1. SSE Comparison Instructions . . . 10-12

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PAGE 10.4.2.2. SSE Shuffle and Unpack Instructions. . . .10-13 10.4.3. SSE Conversion Instructions. . . .10-14 10.4.4. SSE 64-bit SIMD Integer Instructions . . . .10-15 10.4.5. MXCSR State Management Instructions. . . .10-16 10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions. . . .10-16 10.4.6.1. Cacheability Control Instructions . . . .10-17 10.4.6.2. Caching of Temporal Vs. Non-Temporal Data . . . .10-17 10.4.6.3. PREFETCHh Instructions . . . .10-18 10.4.6.4. SFENCE Instruction . . . .10-18 10.5. FXSAVE AND FXRSTOR INSTRUCTIONS . . . 10-19 10.6. HANDLING SSE INSTRUCTION EXCEPTIONS. . . 10-19 10.7. WRITING APPLICATIONS WITH THE SSE EXTENSIONS . . . 10-20

CHAPTER 11

STREAMING SIMD EXTENSIONS 2 (SSE2)

11.1. OVERVIEW OF THE SSE2 EXTENSIONS . . . 11-1 11.2. SSE2 PROGRAMMING ENVIRONMENT . . . 11-3 11.2.1. Compatibility of the SSE2 Extensions with the SSE, MMX Technology,

and x87 FPU Programming Environments . . . 11-4 11.2.2. Denormals-Are-Zeros Flag . . . .11-4 11.3. SSE2 DATA TYPES. . . 11-4 11.4. SSE2 INSTRUCTIONS . . . 11-6 11.4.1. Packed and Scalar Double-Precision Floating-Point Instructions . . . .11-6 11.4.1.1. Data Movement Instructions . . . 11-7 11.4.1.2. SSE2 Arithmetic Instructions . . . 11-8 11.4.1.3. SSE2 Logical Instructions. . . .11-9 11.4.1.4. SSE2 Comparison Instructions. . . .11-10 11.4.1.5. SSE2 Shuffle and Unpack Instructions. . . .11-10 11.4.1.6. SSE2 Conversion Instructions . . . .11-12 11.4.2. SSE2 64-Bit and 128-Bit SIMD Integer Instructions . . . .11-15 11.4.3. 128-Bit SIMD Integer Instruction Extensions. . . .11-16 11.4.4. Cacheability Control and Memory Ordering Instructions . . . .11-17 11.4.4.1. FLUSH Cache Line. . . .11-17 11.4.4.2. Cacheability Control Instructions . . . .11-17 11.4.4.3. Memory Ordering INstructions . . . .11-17 11.4.4.4. Pause . . . .11-18 11.4.5. Branch Hints . . . .11-18 11.5. SSE AND SSE2 EXCEPTIONS . . . 11-18 11.5.1. SIMD Floating-Point Exceptions . . . 11-19 11.5.2. SIMD Floating-Point Exception Conditions . . . 11-19 11.5.2.1. Invalid Operation Exception (#I) . . . 11-20 11.5.2.2. Denormal Operand Exception (#D) . . . 11-21 11.5.2.3. Divide-By-Zero Exception (#Z) . . . .11-21 11.5.2.4. Numeric Overflow Exception (#O) . . . .11-22 11.5.2.5. Numeric Underflow Exception (#U) . . . 11-22 11.5.2.6. Inexact-Result (Precision) Exception (#P) . . . .11-22 11.5.3. Generating SIMD Floating-Point Exceptions . . . .11-23 11.5.3.1. Handling Masked Exceptions . . . .11-23 11.5.3.2. Handling Unmasked Exceptions. . . 11-24 11.5.3.3. Handling Combinations of Masked and Unmasked Exceptions . . . .11-25 11.5.4. Handling SIMD Floating-Point Exceptions in Software . . . .11-25

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PAGE 11.5.5. Interaction of SIMD and x87 FPU Floating-Point Exceptions . . . 11-25 11.6. WRITING APPLICATIONS WITH THE SSE AND SSE2 EXTENSIONS . . . 11-26 11.6.1. General Guidelines for Using the SSE and SSE2 Extensions. . . 11-27 11.6.2. Checking for SSE and SSE2 Support . . . 11-27 11.6.3. Checking for the DAZ Flag in the MXCSR Register . . . 11-28 11.6.4. Initialization of the SSE and SSE2 Extensions . . . 11-28 11.6.5. Saving and Restoring the SSE and SSE2 State . . . 11-29 11.6.6. Guidelines for Writing to the MXCSR Register . . . 11-30 11.6.7. Interaction of SSE and SSE2 Instructions with x87 FPU and

MMX Instructions . . . 11-31 11.6.8. Compatibility of SIMD and x87 FPU Floating-Point Data Types . . . 11-31 11.6.9. Intermixing Packed and Scalar Floating-Point and 128-Bit SIMD

Integer Instructions and Data. . . 11-32 11.6.10. Interfacing with SSE and SSE2 Procedures and Functions . . . 11-33 11.6.10.1. Passing Parameters in XMM Registers . . . 11-33 11.6.10.2. Saving XMM Register State on a Procedure or Function Call . . . 11-33 11.6.10.3. Caller-Save Requirement for Procedure and Function Calls . . . 11-34 11.6.11. Updating Existing MMX Technology Routines Using 128-Bit SIMD

Integer Instructions1 . . . 1-34 11.6.12. Branching on Arithmetic Operations . . . 11-35 11.6.13. Cacheability Hint Instructions . . . 11-35 11.6.14. Effect of Instruction Prefixes on the SSE and SSE2 Instructions . . . 11-36

CHAPTER 12 INPUT/OUTPUT

12.1. I/O PORT ADDRESSING . . . 12-1 12.2. I/O PORT HARDWARE . . . 12-1 12.3. I/O ADDRESS SPACE . . . 12-2 12.3.1. Memory-Mapped I/O . . . 12-2 12.4. I/O INSTRUCTIONS . . . 12-3 12.5. PROTECTED-MODE I/O . . . 12-4 12.5.1. I/O Privilege Level . . . 12-4 12.5.2. I/O Permission Bit Map . . . 12-5 12.6. ORDERING I/O . . . 12-6

CHAPTER 13

PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

13.1. PROCESSOR IDENTIFICATION . . . 13-1 13.2. IDENTIFICATION OF EARLIER IA-32 PROCESSORS. . . 13-6

APPENDIX A

EFLAGS CROSS-REFERENCE

APPENDIX B

EFLAGS CONDITION CODES

APPENDIX C

FLOATING-POINT EXCEPTIONS SUMMARY

C.1. X87 FPU INSTRUCTIONS . . . C-2 C.2. SSE INSTRUCTIONS . . . C-4 C.3. SSE2 INSTRUCTIONS . . . C-6

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xii

PAGE APPENDIX D

GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS

D.1. ORIGIN OF THE MS-DOS* COMPATIBILITY MODE FOR HANDLING X87

FPU EXCEPTIONS . . . D-2

D.2. IMPLEMENTATION OF THE MS-DOS* COMPATIBILITY MODE IN THE

INTEL486, PENTIUM, AND P6 FAMILY, AND PENTIUM 4 PROCESSORS . . . D-3 D.2.1. MS-DOS* Compatibility Mode in the Intel486 and Pentium Processors . . . D-3 D.2.1.1. Basic Rules: When FERR# Is Generated. . . D-4 D.2.1.2. Recommended External Hardware to Support the

MS-DOS* Compatibility Mode D-5

D.2.1.3. No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt in Window . . . D-7 D.2.2. MS-DOS* Compatibility Mode in the P6 Family and Pentium 4 Processors . . . . D-9

D.3. RECOMMENDED PROTOCOL FOR MS-DOS* COMPATIBILITY HANDLERS. . D-10

D.3.1. Floating-Point Exceptions and Their Defaults . . . D-11 D.3.2. Two Options for Handling Numeric Exceptions . . . D-11 D.3.2.1. Automatic Exception Handling: Using Masked Exceptions . . . D-11 D.3.2.2. Software Exception Handling . . . D-13 D.3.3. Synchronization Required for Use of x87 FPU Exception Handlers . . . D-14 D.3.3.1. Exception Synchronization: What, Why and When . . . D-14 D.3.3.2. Exception Synchronization Examples. . . D-15 D.3.3.3. Proper Exception Synchronization in General . . . D-16 D.3.4. x87 FPU Exception Handling Examples . . . D-17 D.3.5. Need for Storing State of IGNNE# Circuit If Using x87 FPU and SMM. . . D-20 D.3.6. Considerations When x87 FPU Shared Between Tasks . . . D-22 D.3.6.1. Speculatively Deferring x87 FPU Saves, General Overview . . . D-22 D.3.6.2. Tracking x87 FPU Ownership. . . D-23 D.3.6.3. Interaction of x87 FPU State Saves and Floating-Point Exception

Association . . . D-23 D.3.6.4. Interrupt Routing From the Kernel . . . D-26 D.3.6.5. Special Considerations for Operating Systems that Support Streaming

SIMD Extensions . . . D-27 D.4. DIFFERENCES FOR HANDLERS USING NATIVE MODE. . . D-27 D.4.1. Origin with the Intel 286 and Intel 287, and Intel386 and Intel 387

Processors. . . D-28 D.4.2. Changes with Intel486, Pentium and Pentium Pro Processors with

CR0.NE=1 . . . D-28 D.4.3. Considerations When x87 FPU Shared Between Tasks Using

Native Mode . . . D-29

APPENDIX E

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS

E.1. TWO OPTIONS FOR HANDLING FLOATING-POINT EXCEPTIONS . . . E-1 E.2. SOFTWARE EXCEPTION HANDLING . . . E-1 E.3. EXCEPTION SYNCHRONIZATION. . . E-3

E.4. SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE STANDARD 754 FOR

BINARY FLOATING-POINT ARITHMETIC E-4

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xiii CONTENTS

PAGE E.4.1. Floating-Point Emulation . . . E-4 E.4.2. SSE and SSE2 Response To Floating-Point Exceptions . . . E-6 E.4.2.1. Numeric Exceptions . . . E-7 E.4.2.2. Results of Operations with NaN Operands or a NaN Result for

SSE and SSE2 Numeric Instructions . . . E-7 E.4.2.3. Condition Codes, Exception Flags, and Response for Masked

and Unmasked Numeric Exceptions . . . E-10 E.4.3. SIMD Floating-Point Emulation Implementation Example . . . E-13

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PAGE

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xv

FIGURES

PAGE Figure 1-1. Bit and Byte Order . . . .1-7 Figure 2-1. The P6 Processor Micro-Architecture with Advanced Transfer

Cache Enhancement . . . 2-10 Figure 2-2. The Intel NetBurst Micro-Architecture. . . .2-13 Figure 2-3. Comparison of an IA-32 Processor with Hyper-Threading

Technology and a Traditional Dual Processor System. . . .2-15 Figure 3-1. IA-32 Basic Execution Environment . . . 3-3 Figure 3-2. Three Memory Management Models . . . .3-6 Figure 3-3. General System and Application Programming Registers . . . 3-9 Figure 3-4. Alternate General-Purpose Register Names . . . .3-10 Figure 3-5. Use of Segment Registers for Flat Memory Model. . . 3-11 Figure 3-6. Use of Segment Registers in Segmented Memory Model . . . 3-11 Figure 3-7. EFLAGS Register . . . 3-13 Figure 3-8. Memory Operand Address . . . .3-19 Figure 3-9. Offset (or Effective Address) Computation . . . 3-20 Figure 4-1. Fundamental Data Types . . . .4-1 Figure 4-2. Bytes, Words, Doublewords, Quadwords, and Double Quadwords

in Memory . . . 4-2 Figure 4-3. Numeric Data Types . . . .4-3 Figure 4-4. Pointer Data Types . . . .4-7 Figure 4-5. Bit Field Data Type . . . .4-7 Figure 4-6. 64-Bit Packed SIMD Data Types . . . .4-8 Figure 4-7. 128-Bit Packed SIMD Data Types . . . .4-9 Figure 4-8. BCD Data Types. . . .4-10 Figure 4-9. Binary Real Number System . . . 4-13 Figure 4-10. Binary Floating-Point Format . . . 4-13 Figure 4-11. Real Numbers and NaNs . . . 4-15 Figure 5-1. SIMD Extensions, Register Layouts, and Data Types . . . 5-14 Figure 6-1. Stack Structure . . . .6-2 Figure 6-2. Stack on Near and Far Calls. . . 6-6 Figure 6-3. Protection Rings . . . .6-8 Figure 6-4. Stack Switch on a Call to a Different Privilege Level . . . .6-9 Figure 6-5. Stack Usage on Transfers to Interrupt and Exception Handling

Routines . . . .6-13 Figure 6-6. Nested Procedures . . . .6-19 Figure 6-7. Stack Frame after Entering the MAIN Procedure . . . .6-20 Figure 6-8. Stack Frame after Entering Procedure A . . . .6-20 Figure 6-9. Stack Frame after Entering Procedure B . . . .6-21 Figure 6-10. Stack Frame after Entering Procedure C . . . .6-22 Figure 7-1. Basic Execution Environment for General-Purpose Instructions . . . .7-2 Figure 7-2. Operation of the PUSH Instruction . . . .7-6 Figure 7-3. Operation of the PUSHA Instruction . . . 7-7 Figure 7-4. Operation of the POP Instruction . . . .7-7 Figure 7-5. Operation of the POPA Instruction . . . .7-8 Figure 7-6. Sign Extension . . . .7-8 Figure 7-7. SHL/SAL Instruction Operation. . . .7-12 Figure 7-8. SHR Instruction Operation . . . .7-13 Figure 7-9. SAR Instruction Operation . . . .7-13 Figure 7-10. SHLD and SHRD Instruction Operations . . . .7-14

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FIGURES

xvi

PAGE Figure 7-11. ROL, ROR, RCL, and RCR Instruction Operations . . . .7-15 Figure 7-12. Flags Affected by the PUSHF, POPF, PUSHFD, and POPFD

instructions . . . 7-25 Figure 8-1. x87 FPU Execution Environment . . . .8-2 Figure 8-2. x87 FPU Data Register Stack. . . .8-3 Figure 8-3. Example x87 FPU Dot Product Computation . . . .8-4 Figure 8-4. x87 FPU Status Word . . . .8-5 Figure 8-5. Moving the Condition Codes to the EFLAGS Register . . . 8-8 Figure 8-6. x87 FPU Control Word . . . .8-9 Figure 8-7. x87 FPU Tag Word . . . .8-11 Figure 8-8. Contents of x87 FPU Opcode Registers. . . .8-13 Figure 8-9. Protected Mode x87 FPU State Image in Memory, 32-Bit Format . . . .8-14 Figure 8-10. Real Mode x87 FPU State Image in Memory, 32-Bit Format . . . 8-14 Figure 8-11. Protected Mode x87 FPU State Image in Memory, 16-Bit Format . . . .8-15 Figure 8-12. Real Mode x87 FPU State Image in Memory, 16-Bit Format . . . 8-15 Figure 8-13. x87 FPU Data Type Formats . . . 8-16 Figure 9-1. MMX Technology Execution Environment . . . .9-2 Figure 9-2. MMX Register Set . . . .9-3 Figure 9-3. Data Types Introduced with the MMX Technology . . . 9-4 Figure 9-4. SIMD Execution Model . . . .9-5 Figure 10-1. SSE Execution Environment. . . 10-3 Figure 10-2. XMM Registers . . . .10-4 Figure 10-3. MXCSR Control/Status Register. . . 10-5 Figure 10-4. 128-Bit Packed Single-Precision Floating-Point Data Type . . . .10-7 Figure 10-5. Packed Single-Precision Floating-Point Operation. . . 10-9 Figure 10-6. Scalar Single-Precision Floating-Point Operation. . . .10-9 Figure 10-7. SHUFPS Instruction Packed Shuffle Operation . . . 10-13 Figure 10-8. UNPCKHPS Instruction High Unpack and Interleave Operation . . . .10-14 Figure 10-9. UNPCKLPS Instruction Low Unpack and Interleave Operation . . . .10-14 Figure 11-1. Steaming SIMD Extensions 2 Execution Environment . . . 11-3 Figure 11-2. Data Types Introduced with the SSE2 Extensions . . . 11-5 Figure 11-3. Packed Double-Precision Floating-Point Operations . . . .11-7 Figure 11-4. Scalar Double-Precision Floating-Point Operations . . . .11-7 Figure 11-5. SHUFPD Instruction Packed Shuffle Operation . . . .11-11 Figure 11-6. UNPCKHPD Instruction High Unpack and Interleave Operation . . . .11-12 Figure 11-7. UNPCKLPD Instruction Low Unpack and Interleave Operation . . . .11-12 Figure 11-8. SSE and SSE2 Conversion Instructions. . . .11-13 Figure 11-9. Example Masked Response for Packed Operations . . . .11-24 Figure 12-1. Memory-Mapped I/O. . . .12-3 Figure 12-2. I/O Permission Bit Map . . . .12-5 Figure D-1. Recommended Circuit for MS-DOS* Compatibility x87 FPU

Exception Handling. . . D-6 Figure D-2. Behavior of Signals During x87 FPU Exception Handling . . . D-7 Figure D-3. Timing of Receipt of External Interrupt . . . D-8 Figure D-4. Arithmetic Example Using Infinity . . . D-12 Figure D-5. General Program Flow for DNA Exception Handler . . . D-25 Figure D-6. Program Flow for a Numeric Exception Dispatch Routine . . . D-25 Figure E-1. Control Flow for Handling Unmasked Floating-Point Exceptions . . . E-6

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xvii

TABLES

PAGE Table 2-1. Key Features of Most Recent IA-32 Processors. . . .2-8 Table 2-2. Key Features of Previous Generations of IA-32 Processors . . . .2-9 Table 3-1. Effective Operand- and Address-Size Attributes . . . .3-17 Table 3-2. Default Segment Selection Rules . . . .3-19 Table 4-1. Signed Integer Encodings. . . .4-4 Table 4-2. Length, Precision, and Range of Floating-Point Data Types . . . .4-5 Table 4-3. Floating-Point Number and NaN Encodings. . . .4-6 Table 4-4. Packed Decimal Integer Encodings . . . 4-11 Table 4-5. Real and Floating-Point Number Notation . . . .4-14 Table 4-6. Denormalization Process . . . 4-16 Table 4-7. Rules for Handling NaNs . . . 4-18 Table 4-8. Rounding Modes and Encoding of Rounding Control (RC) Field . . . 4-20 Table 4-9. Numeric Overflow Thresholds . . . .4-24 Table 4-10. Masked Responses to Numeric Overflow. . . .4-25 Table 4-11. Numeric Underflow (Normalized) Thresholds. . . .4-25 Table 5-1. Instruction Groups and IA-32 Processors. . . .5-1 Table 6-1. Exceptions and Interrupts . . . .6-12 Table 7-1. Move Instruction Operations. . . 7-3 Table 7-2. Conditional Move Instructions. . . .7-4 Table 7-3. Bit Test and Modify Instructions . . . 7-16 Table 7-4. Conditional Jump Instructions. . . .7-19 Table 8-1. Condition Code Interpretation. . . .8-7 Table 8-2. Precision Control Field (PC) . . . 8-10 Table 8-3. Unsupported Double Extended-Precision Floating-Point Encodings an

d Pseudo-Denormals . . . 8-18 Table 8-4. Data Transfer Instructions . . . .8-20 Table 8-5. Floating-Point Conditional Move Instructions . . . .8-21 Table 8-6. Setting of x87 FPU Condition Code Flags for Floating-Point Number

Comparisons. . . .8-24 Table 8-7. Setting of EFLAGS Status Flags for Floating-Point Number

Comparisons. . . .8-24 Table 8-8. TEST Instruction Constants for Conditional Branching . . . .8-25 Table 8-9. Arithmetic and Non-arithmetic Instructions . . . 8-31 Table 8-10. Invalid Arithmetic Operations and the Masked Responses to Them . . . 8-34 Table 8-11. Divide-By-Zero Conditions and the Masked Responses to Them . . . 8-36 Table 9-1. Data Range Limits for Saturation . . . .9-6 Table 9-2. MMX Instruction Set Summary . . . .9-7 Table 9-3. Effect of Prefixes on MMX Instructions. . . .9-14 Table 10-1. PREFETCHh Instructions Caching Hints . . . .10-19 Table 11-1. Masked Responses of SSE and SSE2 Instructions to Invalid

Arithmetic Operations . . . .11-20 Table 11-2. SSE and SSE2 State Following a Power-up/Reset or INIT . . . .11-29 Table 11-3. Effect of Prefixes on SSE and SSE2 Instructions. . . .11-37 Table 12-1. I/O Instruction Serialization. . . .12-7 Table 13-1. Highest CPUID Source Operand for IA-32 Processors and

Processor Families . . . .13-2 Table 13-2. Information Returned by CPUID Instruction . . . .13-2 Table 13-3. Feature Flags Returned in EDX Register . . . .13-3 Table A-1. EFLAGS Cross-Reference . . . A-1

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xviii TABLES

PAGE Table B-1. EFLAGS Condition Codes . . . B-1 Table C-1. x87 FPU and SIMD Floating-Point Exceptions . . . C-1 Table C-2. Exceptions Generated With x87 FPU Floating-Point Instructions . . . C-2 Table C-3. Exceptions Generated With the SSE Instructions . . . C-4 Table C-4. Exceptions Generated With the SSE2 Instructions . . . C-6 Table E-1. ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVPS, DIVSS. . . E-8 Table E-2. CMPPS.EQ, CMPSS.EQ, CMPPS.ORD, CMPSS.ORD. . . E-8 Table E-3. CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CMPSS.UNORD . . . E-8 Table E-4. CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE . . . E-8 Table E-5. CMPPS.NLT, CMPSS.NLT, CMPSS.NLT, CMPSS.NLE . . . E-8 Table E-6. COMISS . . . E-9 Table E-7. UCOMISS . . . E-9 Table E-8. CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI . . . E-9 Table E-9. MAXPS, MAXSS, MINPS, MINSS . . . E-9 Table E-10. SQRTPS, SQRTSS . . . E-9 Table E-11. #I - Invalid Operations . . . E-10 Table E-12. #Z - Divide-by-Zero . . . E-11 Table E-13. #D - Denormal Operand . . . E-12 Table E-14. #O - Numeric Overflow . . . E-12 Table E-15. #U - Numeric Underflow . . . E-13 Table E-16. #P - Inexact Result (Precision) . . . E-13

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1

About This Manual

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1-1

CHAPTER 1 ABOUT THIS MANUAL

The IA-32 Intel^® Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Order Number 245470) is part of a three-volume set that describes the architecture and programming environment of all IA-32 Intel^® Architecture processors. The other two volumes in this set are:

•

The IA-32 Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference (Order Number 245471).

•

The IA-32 Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide (Order Number 245472).

The IA-32 Intel Architecture Software Developer’s Manual, Volume 1, describes the basic archi- tecture and programming environment of an IA-32 processor; the IA-32 Intel Architecture Soft- ware Developer’s Manual, Volume 2, describes the instruction set of the processor and the opcode structure. These two volumes are aimed at application programmers who are writing programs to run under existing operating systems or executives. The IA-32 Intel Architecture Software Developer’s Manual, Volume 3 describes the operating-system support environment of an IA-32 processor, including memory management, protection, task management, interrupt and exception handling, and system management mode. It also provides IA-32 processor compatibility information. This volume is aimed at operating-system and BIOS designers and programmers.

1.1. IA-32 PROCESSORS COVERED IN THIS MANUAL

This manual includes information pertaining primarily to the most recent IA-32 processors, which include the Pentium^® processors, the P6 family processors, the Pentium^® 4 processors, the Intel^® Xeon™ processors. The P6 family processors are those IA-32 processors based on the P6 family micro-architecture, which include the Pentium^® Pro, Pentium^® II, and Pentium^® III processors. The Pentium 4 and Intel Xeon processors are based on the Intel^® NetBurst™ micro- architecture.

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1-2

1.2. OVERVIEW OF THE IA-32 INTEL ARCHITECTURE

SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE

The contents of this manual are as follows:

Chapter 1 — About This Manual. Gives an overview of all three volumes of the IA-32 Intel Architecture Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel manuals and documentation of interest to programmers and hardware designers.

Chapter 2 — Introduction to the IA-32 Architecture. Introduces the IA-32 architecture and the families of Intel processors that are based on this architecture. It also gives an overview of the common features found in these processors and brief history of the IA-32 architecture.

Chapter 3 — Basic Execution Environment. Introduces the models of memory organization and describes the register set used by applications.

Chapter 4 — Data Types. Describes the data types and addressing modes recognized by the processor; provides an overview of real numbers and floating-point formats and of floating- point exceptions.

Chapter 5 — Instruction Set Summary. Lists the all the IA-32 architecture instructions, divided into technology groups (general-purpose, x87 FPU, MMX™ technology, Streaming SIMD Extensions (SSE), Streaming SIMD Extensions 2 (SSE2), and system instructions).

Within these groups, the instructions are presented in functionally related groups.

Chapter 6 — Procedure Calls, Interrupts, and Exceptions. Describes the procedure stack and the mechanisms provided for making procedure calls and for servicing interrupts and exceptions.

Chapter 7 — Programming With the General-Purpose Instructions. Describes the basic load and store, program control, arithmetic, and string instructions that operate on basic data types and on the general-purpose and segment registers; describes the system instructions that are executed in protected mode.

Chapter 8 — Programming With the x87 Floating Point Unit. Describes the x87 floating- point unit (FPU), including the floating-point registers and data types; gives an overview of the floating-point instruction set; and describes the processor’s floating-point exception conditions.

Chapter 9 — Programming with Intel MMX Technology. Describes the Intel MMX tech- nology, including MMX registers and data types, and gives an overview of the MMX instruction set.

Chapter 10 — Programming with Streaming SIMD Extensions (SSE). Describes the SSE extensions, including the XMM registers, the MXCSR register, and the packed single-precision floating-point data types; gives an overview of the SSE instruction set; and gives guidelines for writing code that accesses the SSE extensions.

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1-3 ABOUT THIS MANUAL

Chapter 11 — Programming with Streaming SIMD Extensions 2 (SSE2). Describes the SSE2 extensions, including XMM registers and the packed double-precision floating-point data types; gives an overview of the SSE2 instruction set; and gives guidelines for writing code that accesses the SSE2 extensions. This chapter also describes the SIMD floating-point exceptions that can be generated with SSE and SSE2 instructions, and it gives general guidelines for incor- porating support for the SSE and SSE2 extensions into operating system and applications code.

Chapter 12 — Input/Output. Describes the processor’s I/O mechanism, including I/O port addressing, the I/O instructions, and the I/O protection mechanism.

Chapter 13 — Processor Identification and Feature Determination. Describes how to deter- mine the CPU type and the features that are available in the processor.

Appendix A — EFLAGS Cross-Reference. Summarizes how the IA-32 instructions affect the flags in the EFLAGS register.

Appendix B — EFLAGS Condition Codes. Summarizes how the conditional jump, move, and byte set on condition code instructions use the condition code flags (OF, CF, ZF, SF, and PF) in the EFLAGS register.

Appendix C — Floating-Point Exceptions Summary. Summarizes the exceptions that can be raised by the x87 FPU floating-point and the SSE and SSE2 SIMD floating-point instructions.

Appendix D — Guidelines for Writing x87 FPU Exception Handlers. Describes how to design and write MS-DOS* compatible exception handling facilities for FPU exceptions, including both software and hardware requirements and assembly-language code examples.

This appendix also describes general techniques for writing robust FPU exception handlers.

Appendix E — Guidelines for Writing SIMD Floating-Point Exception Handlers. Gives guidelines for writing exception handlers to handle exceptions generated by the SSE and SSE2 SIMD floating-point instructions.

1.3. OVERVIEW OF THE IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 2:

INSTRUCTION SET REFERENCE

The contents of the IA-32 Intel Architecture Software Developer’s Manual, Volume 2 are as follows:

Chapter 1 — About This Manual. Gives an overview of all three volumes of the IA-32 Soft- ware Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel manuals and documentation of interest to programmers and hardware designers.

Chapter 2 — Instruction Format. Describes the machine-level instruction format used for all IA-32 instructions and gives the allowable encodings of prefixes, the operand-identifier byte (ModR/M byte), the addressing-mode specifier byte (SIB byte), and the displacement and immediate bytes.

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1-4

Chapter 3 — Instruction Set Reference. Describes each of the IA-32 instructions in detail, including an algorithmic description of operations, the effect on flags, the effect of operand- and address-size attributes, and the exceptions that may be generated. The instructions are arranged in alphabetical order. The general-purpose, x87 FPU, MMX, SSE, SSE2, and system instructions are included in this chapter.

Appendix A — Opcode Map. Gives an opcode map for the IA-32 instruction set.

Appendix B — Instruction Formats and Encodings. Gives the binary encoding of each form of each IA-32 instruction.

Appendix C — Intel C/C++ Compiler Intrinsics and Functional Equivalents. Lists the Intel C/C++ compiler intrinsics and their assembly code equivalents for each of the IA-32 MMX, SSE, and SSE2 instructions.

1.4. OVERVIEW OF THE IA-32 INTEL ARCHITECTURE

SOFTWARE DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE

The contents of the IA-32 Intel Architecture Software Developer’s Manual, Volume 3 are as follows:

Chapter 1 — About This Manual. Gives an overview of all three volumes of the IA-32 Intel Architecture Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related Intel manuals and documentation of interest to programmers and hardware designers.

Chapter 2 — System Architecture Overview. Describes the modes of operation of an IA-32 processor and the mechanisms provided in the IA-32 architecture to support operating systems and executives, including the system-oriented registers and data structures and the system- oriented instructions. The steps necessary for switching between real-address and protected modes are also identified.

Chapter 3 — Protected-Mode Memory Management. Describes the data structures, registers, and instructions that support segmentation and paging and explains how they can be used to implement a “flat” (unsegmented) memory model or a segmented memory model.

Chapter 4 — Protection. Describes the support for page and segment protection provided in the IA-32 architecture. This chapter also explains the implementation of privilege rules, stack switching, pointer validation, user and supervisor modes.

Chapter 5 — Interrupt and Exception Handling. Describes the basic interrupt mechanisms defined in the IA-32 architecture, shows how interrupts and exceptions relate to protection, and describes how the architecture handles each exception type. Reference information for each IA- 32 exception is given at the end of this chapter.

Chapter 6 — Task Management. Describes the mechanisms the IA-32 architecture provides to support multitasking and inter-task protection.

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Chapter 7 — Multiple-Processor Management. Describes the instructions and flags that support multiple processors with shared memory, memory ordering, and Hyper-Threading technology.

Chapter 8 — Advanced Programmable Interrupt Controller (APIC). Describes the programming interface to the local APIC and gives an overview of the interface between the local APIC and the I/O APIC.

Chapter 9 — Processor Management and Initialization. Defines the state of an IA-32 processor after reset initialization. This chapter also explains how to set up an IA-32 processor for real-address mode operation and protected- mode operation, and how to switch between modes.

Chapter 10 — Memory Cache Control. Describes the general concept of caching and the caching mechanisms supported by the IA-32 architecture. This chapter also describes the memory type range registers (MTRRs) and how they can be used to map memory types of physical memory. Information on using the new cache control and memory streaming instructions introduced with the Pentium III, Pentium 4, and Intel Xeon processors is also given.

Chapter 11 — Intel MMX™ Technology System Programming. Describes those aspects of the Intel MMX technology that must be handled and considered at the system programming level, including task switching, exception handling, and compatibility with existing system environments. The Intel MMX technology was introduced into the IA-32 architecture with the Pentium processor.

Chapter 12 — SSE and SSE2 System Programming. Describes those aspects of SSE and SSE2 extensions that must be handled and considered at the system programming level, including task switching, exception handling, and compatibility with existing system environments.

Chapter 13 — System Management. Describes the IA-32 architecture’s system management mode (SMM) and the thermal monitoring facilities.

Chapter 14 — Machine-Check Architecture. Describes the machine-check architecture.

Chapter 15 — Debugging and Performance Monitoring. Describes the debugging registers and other debug mechanism provided in the IA-32 architecture. This chapter also describes the time-stamp counter and the performance-monitoring counters.

Chapter 16 — 8086 Emulation. Describes the real-address and virtual-8086 modes of the IA- 32 architecture.

Chapter 17 — Mixing 16-Bit and 32-Bit Code. Describes how to mix 16-bit and 32-bit code modules within the same program or task.

Chapter 18 — IA-32 Architecture Compatibility. Describes architectural compatibility among the IA-32 processors, which include the Intel 286, Intel386™, Intel486™, Pentium, P6 family, Pentium 4, and Intel Xeon processors. The P6 family includes the Pentium Pro, Pentium II, and Pentium III processors. The differences among the 32-bit IA-32 processors are also described throughout the three volumes of the IA-32 Software Developer’s Manual, as relevant to particular features of the architecture.

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1-6

This chapter provides a collection of all the relevant compatibility information for all IA-32 processors and also describes the basic differences with respect to the 16-bit IA-32 processors (the Intel 8086 and Intel 286 processors).

Appendix A — Performance-Monitoring Events. Lists the events that can be counted with the performance-monitoring counters and the codes used to select these events. Both Pentium processor and P6 family processor events are described.

Appendix B — Model Specific Registers (MSRs). Lists the MSRs available in the Pentium processors, the P6 family processors, and the Pentium 4 and Intel Xeon processors and describes their functions.

Appendix C — MP Initialization For P6 Family Processors. Gives an example of how to use of the MP protocol to boot P6 family processors in n MP system.

Appendix D — Programming the LINT0 and LINT1 Inputs. Gives an example of how to program the LINT0 and LINT1 pins for specific interrupt vectors.

Appendix E — Interpreting Machine-Check Error Codes. Gives an example of how to inter- pret the error codes for a machine-check error that occurred on a P6 family processor.

Appendix F — APIC Bus Message Formats. Describes the message formats for messages transmitted on the APIC bus for P6 family and Pentium processors.

1.5. NOTATIONAL CONVENTIONS

This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. A review of this notation makes the manual easier to read.

1.5.1. Bit and Byte Order

In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to two raised to the power of the bit position. IA-32 processors are “little endian” machines; this means the bytes of a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions.

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1.5.2. Reserved Bits and Software Compatibility

In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable. Software should follow these guidelines in dealing with reserved bits:

•

Do not depend on the states of any reserved bits when testing the values of registers which contain such bits. Mask out the reserved bits before testing.

•

Do not depend on the states of any reserved bits when storing to memory or to a register.

•

Do not depend on the ability to retain information written into any reserved bits.

•

When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register.

NOTE

Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits. Programs that depend upon reserved values risk incompat- ibility with future processors.

Figure 1-1. Bit and Byte Order Byte 3

Highest Data Structure

Byte 1

Byte 2 Byte 0

31 24 23 16 15 8 7 0

Address

Lowest Bit offset 28

24 20 16 12 8 4

0 Address

Byte Offset

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1-8

1.5.3. Instruction Operands

When instructions are represented symbolically, a subset of the IA-32 assembly language is used. In this subset, an instruction has the following format,

label: mnemonic argument1, argument2, argument3 where:

•

A label is an identifier which is followed by a colon.

•

A mnemonic is a reserved name for a class of instruction opcodes which have the same function.

•

The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands, depending on the opcode. When present, they take the form of either literals or identifiers for data items. Operand identifiers are either reserved names of registers or are assumed to be assigned to data items declared in another part of the program (which may not be shown in the example).

When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left operand is the destination.

For example:

LOADREG: MOV EAX, SUBTOTAL

In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand, and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.

1.5.4. Hexadecimal and Binary Numbers

Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.

Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for example, 1010B). The “B” designation is only used in situations where confu- sion as to the type of number might arise.

1.5.5. Segmented Addressing

The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes. Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes memory. The range of memory that can be addressed is called an address space.

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The processor also supports segmented addressing. This is a form of addressing where a program may have many independent address spaces, called segments. For example, a program can keep its code (instructions) and stack in separate segments. Code addresses would always refer to the code space, and stack addresses would always refer to the stack space. The following notation is used to specify a byte address within a segment:

Segment-register:Byte-address

For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS register:

DS:FF79H

The following segment address identifies an instruction address in the code segment. The CS register points to the code segment and the EIP register contains the address of the instruction.

CS:EIP

1.5.6. Exceptions

An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to divide by zero generates an exception. However, some exceptions, such as break- points, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the error. An example of the notation used to show an exception and error code is shown below.

#PF(fault code)

This example refers to a page-fault exception under conditions where an error code naming a type of fault is reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate code. In this case, the error code is zero, as shown below for a general-protection exception.

#GP(0)

See Chapter 5, Interrupt and Exception Handling, in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3, for a list of exception mnemonics and their descriptions.

1.6. RELATED LITERATURE

Literature related to IA-32 processors is listed on-line at the following Intel web site:

http://developer.intel.com/design/processors/

Some of the documents listed at this web site can be viewed on-line; others can be ordered on- line. The literature available is listed by Intel processor and then by the following literature types: applications notes, data sheets, manuals, papers, and specification updates. The following literature may be of interest:

•

Data Sheet for a particular Intel IA-32 processor.

•

Specification Update for a particular Intel IA-32 processor.

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1-10

•

AP-485, Intel Processor Identification and the CPUID Instruction, Order Number 241618.

•

AP-578, Software and Hardware Considerations for FPU Exception Handlers for Intel Architecture Processors, Order Number 243291.

•

Intel^® Pentium^® 4 and Intel^® Xeon™ Processor Optimization Reference Manual, Order Number 248966.

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2

Introduction to the

IA-32 Architecture

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2-1

CHAPTER 2 INTRODUCTION TO THE IA-32 INTEL ARCHITECTURE

The exponential growth of computing power and personal computer ownership made the computer one of the most important forces that shaped business and society in the second half of the twentieth century. Furthermore, computers are expected to continue to play crucial roles in the growth of technology, business, and other new arenas in the future, because new applications (such as, the Internet, digital media, and genetics research) are strongly dependent on ever increasing computing power for their growth.

The IA-32 Intel Architecture has been at the forefront of the computer revolution and is today clearly the preferred computer architecture, as measured by the number of computers in use and total computing power available in the world. Two of the major factors that may be the cause of the popularity of IA-32 architecture are: compatibility of software written to run on IA-32 processors, and the fact that each generation of IA-32 processors delivers significantly higher performance than the previous generation. This chapter provides a brief historical summary of the IA-32 architecture, from its origin in the Intel 8086 processor to the latest version imple- mented in the Pentium 4 and Intel Xeon processors.

2.1. BRIEF HISTORY OF THE IA-32 ARCHITECTURE

The developments leading to the latest version of the IA-32 architecture can be traced back to the Intel 8085 and 8080 microprocessors and to the Intel 4004 microprocessor (the first microprocessor, designed by Intel in 1969). Before the IA-32 architecture family introduced 32-bit processors, it was preceded by 16-bit processors including the 8086 processor, and quickly followed by a more cost-effective version, the 8088. From a historical perspective, the IA-32 architecture contains both 16-bit processors and 32-bit processors. At present, the 32-bit IA-32 architecture is a very popular computer architecture for many operating systems and a very wide range of applications.

One of the most important achievements of the IA-32 architecture is that the object code programs created for these processors starting in 1978 still execute on the latest processors in the IA-32 architecture family.

The 8086 had 16-bit registers and a 16-bit external data bus, with 20-bit addressing giving a 1- MByte address space. The 8088 is similar to the 8086 except it had an 8-bit external data bus.

These early processors introduced segmentation to the IA-32 architecture. With segmentation, a 16-bit segment register contains a pointer to a memory segment of up to 64 KBytes. Using four segment registers at a time, the 8086/8088 processors are able to address up to 256KBytes without switching between segments. The 20-bit addresses that can be formed using a segment register pointer and an additional 16-bit pointer provide a total address range of 1 MByte.

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2-2

INTRODUCTION TO THE IA-32 INTEL ARCHITECTURE

The Intel 286 processor introduced protected mode operation into the IA-32 architecture.

Protected mode uses the segment register contents as selectors or pointers into descriptor tables.

The descriptors provide 24-bit base addresses, maximum physical memory size of up to 16MBytes, support for virtual memory management on a segment swapping basis, and various protection mechanisms. The protection mechanisms include: segment limit checking, read-only and execute-only segment options, and up to four privilege levels to protect operating system code (in several subdivisions, if desired) from application or user programs. In addition, hardware task switching and local descriptor tables allow the operating system to protect application or user programs from each other.

The Intel386 processor was the first 32-bit processor in the IA-32 architecture family. It introduced 32-bit registers, for use both to hold operands and for addressing. The lower half of each 32-bit register retained the properties of the 16-bit registers of the two earlier generations, to provide complete backward compatibility. The new virtual-8086 mode provided greater effi- ciency when executing programs created for the 8086 and 8088 processors on the new 32-bit processors.

The Intel386 processor has a 32-bit address bus, and can support up to 4GBytes of physical memory. The 32-bit architecture provides logical address space for each software process. The 32-bit architecture supports both a segmented-memory model and a “flat”¹ memory model. In the “flat” memory model, the segment registers point to the same address, and all 4GBytes of addressable space within each segment are accessible to the software programmer. The original 16-bit instructions were enhanced with new 32-bit operand and addressing forms, and among the new instructions provided were those for bit manipulation. The Intel386 processor introduced paging into the IA-32 architecture, with the fixed 4KByte page size providing a method for virtual memory management that was significantly superior to using segments for this purpose. This paging system was much more efficient for operating systems, and completely transparent to the applications, without a significant sacrifice in execution speed. The ability to support 4GBytes of virtual address space, memory protection, together with paging support, enabled the IA-32 architecture to be a popular choice for advanced operating systems and wide variety of applications.

The IA-32 architecture is committed to maintaining backward compatibility at the object code level to preserve Intel customers’ huge investment in software. At the same time, each genera- tion of the architecture uses the latest most effective micro-architecture and silicon fabrication technologies to produce high-performance processors. With each generation of IA-32 processors, Intel has conceived and incorporated increasingly sophisticated techniques into its microarchitecture in pursuit of ever faster computers.

Various forms of parallel processing has been the best performance enhancing of these techniques, and the Intel386 processor was the first to include a number of parallel stages. The six stages are: the bus interface unit (accesses memory and I/O for the other units), the code prefetch unit (receives object code from the bus unit and puts it into a 16-byte queue), the instruction decode unit (decodes object code from the prefetch unit into microcode), the execution unit (executes the microcode instructions), the segment unit (translates logical addresses to linear addresses and does protection checks), and the paging unit (translates linear addresses to

1. Requires only one 32-bit address component to access anywhere in the linear address space.

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2-3 INTRODUCTION TO THE IA-32 INTEL ARCHITECTURE

physical addresses, does page based protection checks, and contains a cache with information for up to 32 most recently accessed pages).

The Intel486 processor added more parallel execution capability by expanding the Intel386 processor’s instruction decode and execution units into five pipelined stages, where each stage (when needed) operates in parallel with the others on up to five instructions in different stages of execution. Each stage can do its work on one instruction in one clock, and so the Intel486 processor can execute as rapidly as one instruction per clock cycle. An 8-KByte on-chip first- level cache was added to the Intel486 processor to greatly increase the percent of instructions that could execute at the scalar rate of one per clock: memory access instructions were now included if the operand was in the first-level cache. The Intel486 processor also for the first time integrated the x87 FPU onto the processor and added new pins, bits and instructions to support more complex and powerful systems (second-level cache support and multiprocessor support).

Late in the Intel486 processor generation, Intel incorporated features designed to support power savings and other system management capabilities into the IA-32 architecture mainstream with the Intel486 SL Enhanced processors. These features were developed in the Intel386 SL and Intel486 SL processors, which were specialized for the rapidly growing battery-operated note- book PC market segment. The features include the new System Management Mode, triggered by its own dedicated interrupt pin, which allows complex system management features (such as power management of various subsystems within the PC), to be added to a system transparently to the main operating system and all applications. The Stop Clock and Auto Halt Powerdown features allow the processor itself to execute at a reduced clock rate to save power, or to be shut down (with state preserved) to save even more power.

The Intel Pentium processor added a second execution pipeline to achieve superscalar performance (two pipelines, known as u and v, together can execute two instructions per clock). The on-chip first-level cache was also doubled, with 8 KBytes devoted to code, and another 8 KBytes devoted to data. The data cache uses the MESI protocol to support the more efficient write-back cache, as well as the write-through cache that is used by the Intel486 processor.

Branch prediction with an on-chip branch table was added to increase performance in looping constructs. Extensions were added to make the virtual-8086 mode more efficient, and to allow for 4-MByte as well as 4-KByte pages. The main registers are still 32 bits, but internal data paths of 128 and 256 bits were added to speed internal data transfers, and the burstable external data bus has been increased to 64 bits. The Advanced Programmable Interrupt Controller (APIC) was added to support systems with multiple Pentium processors, and new pins and a special mode (dual processing) was designed in to support glueless two processor systems.

The last processor in the Pentium family (the Pentium Processor with MMX™ technology) introduced the Intel MMX technology to the IA-32 architecture. The Intel MMX technology uses the single-instruction, multiple-data (SIMD) execution model to perform parallel compu- tations on packed integer data contained in the 64-bit MMX registers. This technology greatly enhanced the performance of the IA-32 processors in advanced media, image processing, and data compression applications.