Chap. 12 Memory Organization



12-1 Memory Hierarchy



Memory hierarchy in a computer system :



Main Memory : memory unit that communicates directly with the CPU (RAM)



Auxiliary Memory : device that provide backup storage (Disk Drives)



Cache Memory : special very-high-speed memory to increase the processing speed (Cache RAM)



Multiprogramming



enable the CPU to process a number of independent program concurrently



Memory Management System :



supervise the flow of information between auxiliary memory and main memory

M a g n e tic ta p e s

M a g n e tic d is k s

I/ O p ro c e s s o r

C P U

M a in m e m o ry

C a c h e m e m o ry A u x ilia ry m e m o ry



12-2 Main Memory

 Bootstrap Loader



A program whose function is to start the computer software operating when power is turned on

 RAM and ROM Chips



Typical RAM chip : Fig. 12-2

» 128 X 8 RAM : 2⁷ = 128 (7 bit address lines)



Typical ROM chip : Fig. 12-3

» 512 X 8 ROM : 2⁹ = 512 (9 bit address lines)

×

1 2 8 × 8 R A M C S 1

A D 7 W R R D C S 2 C h ip s e le c t 1

C h ip s e le c t 2 R e a d W rite 7 b it a d d re s s

8 b it d a ta b u s

( a ) B lo c k d ia g ra m

C S 1 C S 2 R D W R M e m o ry f u n c tio n S ta te o f d a ta b u s

0

×

×

× 0

0 0

0 0

1 0 1

1 1 1

1

×

0

×

× 0

1 1

In h ib it

In h ib it In h ib it

W rite R e a d In h ib it

H ig h - im p e d a n c e

H ig h - im p e d a n c e H ig h - im p e d a n c e

In p u t d a ta to R A M O u tp u t d a ta f ro m R A M H ig h - im p e d a n c e

( b ) F u n c tio n ta b le

5 1 2 × 8 R O M C S 1

A D 9 C S 2 C h ip s e le c t 1

C h ip s e le c t 2

9 b it a d d re s s

8 b it d a ta b u s

P o w e r - O N

F F F F : 0 0 0 0 ( R e s e t P o in t )

P O S T S y s t e m I n i t .

I N T 1 9

L o a d B o o t s t r a p R e c o r d ( T r a c k 0 , S e c t o r 0 )

L o a d O p e r a t i n g S y s t e m

( I O . S Y S , M S D O S . S Y S , C O M M A N D . C O M )

Bootstrap Loader Bootstrap ROM Boot ROM

 Memory Address Map



Memory Configuration : 512 bytes RAM + 512 bytes ROM

» 1 x 512 byte ROM + 4 x 128 bytes RAM



Memory Address Map : Tab. 12-1

» Address line 9 8

 RAM 1 0 0 : 0000 - 007F

 RAM 1 0 1 : 0080 - 00FF

 RAM 1 1 0 : 0100 - 017F

 RAM 1 1 1 : 0180 - 01FF

» Address line 10

 ROM 1 : 0200 - 03FF



Memory Connection to CPU : Fig. 12-4

» 2 x 4 Decoder : RAM select (CS1)

» Address line 10

 RAM select : CS2

 ROM select : CS2 의 Invert

» 참고

 RD : ROM 의 CS1 은 보통 OE(Output Enable)로 사용

1 2 8 × 8 R A M 1 C S 1

A D 7 W R R D C S 2

1 2 8 × 8 R A M 2 C S 1

A D 7 W R R D C S 2

1 2 8 × 8 R A M 4 C S 1

A D 7 W R R D C S 2

1 2 8 × 8 R A M 3 C S 1

A D 7 W R R D C S 2

1 2 8 × 8 R O M C S 1 C S 2

A D 9 D a ta D a ta D a ta

D a ta

D a ta C P U

W R R D 1 6 - 1 1 1 0 9 8 7 - 1

A d d re s s b u s

D a ta b u s

D e c o d e r 3 2 1 0

1 - 7 8 9



12-3 Auxiliary Memory

 Magnetic Disk : Fig. 12-5, FDD, HDD

 Magnetic Tape : Backup or Program 저장

 Optical Disk : CDR, ODD, DVD



12-4 Associative Memory

 Content Addressable Memory (CAM)



A memory unit accessed by content



Block Diagram : Fig. 12-6

t e x t t e x t t e x t t e x t

Sector

R e a d / W rite h e a d

T ra c k s

A Register 101 111100 K Register 111 000000

Word 1 100 111100 M = 0 Word 2 101 000011 M = 1

A rg u m e n t re g is te r ( A )

K e y re g is te r ( K )

A s s o c ia tiv e m e m o ry a rra y a n d lo g ic

m w o rd s n b its p e r w o rd

M M a tc h re g is te r I n p u t

W rite R e a d

O u tp u t

이름 주소

Argument Key (Mask)

Match Logic Memory 내용

M = 1 일때 출력

 m word x n cells per word : Fig. 12-7

 Match Logic



One cell of associative memory : Fig. 12-8

» Input = 1 or 0 에 따라 Write 신호와 동시에 F/F 에 저장

» A 와 K 에 의해 Match Logic 에서 M=1 이면 (M을 READ 에 직접 연결 가능함 )

» Read 신호에 따라 F/F 에서 데이터를 읽는다

A1

C1 1

An

A j

K1 K j Kn

C 1 j C1 n

C i1 C ij C in

Cm 1 Cm j Cm n

M1

Mm

Mi

B it 1 B it j B it n

W o rd 1

W o rd m W o rd i

R S M a tc h lo g ic In p u t

R e a d W rite

O u tp u t

T o M i

K j

A i

Fij



Match Logic : Fig. 12-9

» Aj = Argument, F_ij = Cell ij 번째 bit

» j 번째 1 bit match 조건

x_j = A_j F_ij (1 AND 1)+ A_j’ F_ij’ (0 AND 0)

» 1 - n 까지 n bits match 조건 Mi = x₁x₂…..x_n

» Key bit K_j : x_j + K_j’

 Kj = 0 : Aj 와 Fij 는 no comparison ( Kj : xj + 1 = 1 )

 Kj = 1 : Aj 와 Fij 는 comparison ( Kj : xj + 0 = xj )

» Match Logic for word I :

M_i = (x₁ + K₁’) (x₂ + K₂’)…. (x_n + K_n’) = (x_j + K_j’)

= (A_j F_ij + A_j’ F_ij’ + K_j’)

 n

j 1

 n j 1

F 'i1 Fi1

A1

K1

F 'i 2 Fi2

A2

K2

F 'in Fi n

An

Kn

M i



12-5 Cache Memory



Locality of Reference



the references to memory tend to be confined within a few localized areas in memory



Cache Memory : a fast small memory



keeping the most frequently accessed instructions and data in the fast cache memory



Cache 의 설계 요소



cache size :



mapping method : 1) associative, 2) direct, 3) set-associative



replace algorithm : 1) LRU, 2) LFU, 3) FIFO



write policy : 1) write-through, 2) write-back



Hit Ratio



the ratio of the number of hits divided by the total CPU references (hits + misses) to memory

» hit : the CPU finds the word in the cache ( 보통 0.9 이상)

» miss : the word is not found in cache (CPU must read main memory)



예제 : cache memory access time = 100 ns, main memory access time = 1000 ns, hit ratio = 0.9

» 1 회 miss : 1 x 1000 ns

» 9 회 hit : 9 x 100 ns 총 10 회

Memory 참조

1900 ns / 10 회 = 190 ns Cache가 없으면 1000 ns, 따라서 약 5 배 성능 향상

 Mapping



The transformation of data from main memory to cache memory

» 1) Associative mapping

» 2) Direct mapping

» 3) Set-associative mapping

 Example of cache memory : Fig. 12-10

main memory : 32 K x 12 bit word (15 bit address lines) cache memory : 512 x 12 bit word

» CPU sends a 15-bit address to cache

 Hit : CPU accepts the 12-bit data from cache

 Miss : CPU reads the data from main memory (then data is written to cache)

 Associative mapping : Fig. 12-11



Cache memory 로 고가의 associative memory 사용



Address 와 Data 가 직접 Cache memory 에 사용됨

 Direct mapping : Fig. 12-12



Cache memory 로 저가의 일반 memory 사용



Tag field (n - k) 와 Index field (k) 를 사용

» 2^k words cache memory + 2ⁿ words main memory

 Tag = 6 bit (15 - 9), Index = 9 bit

Cache Coherence (Sec. 13-5)

M a in m e m o r y

3 2 K × 1 2 C P U

C a c h e m e m o ry 5 1 2 × 1 2

A rg u m e n t re g is te r

0 1 0 0 0

2 2 3 4 5 0 2 7 7 7

3 4 5 0

1 2 3 4 6 7 1 0

A d d re s s D a ta

C P U a d d re s s ( 1 5 b its )



Direct mapping cache organization : Fig. 12-13

» 예제 : 02000 번지를 읽는 경우

 1) 우선 Index 000을 cache 에서 찾는다

 2) 다음은 Tag 를 cache 에서 비교한다

 3) 000 Index에 있는 cache tag 는 00 이다 (02가 아니다)

 4) 따라서 miss

 5) 그러므로 main memory 에서 data read (address 02000 = 5670 read)

3 2 K × 1 2

M a in m e m o ry

A d d re s s = 1 5 b its D a ta = 1 2 b its

T a g In d e x

6 b its 9 b its

H e x A d d re s s

0 0 0 0 0

3 F 1 F F

5 1 2 × 1 2 C a c h e m e m o ry

A d d re s s = 9 b its D a ta = 1 2 b its 0 0 0

1 F F O c ta l a d d re s s

1 2 2 0

2 3 4 0 3 4 5 0

4 5 6 0 5 6 7 0

6 7 1 0 M e m o ry d a ta M e m o ry

a d d re s s 0 0 0 0 0 0

0 2 7 7 7 0 2 0 0 0 0 1 7 7 7 0 1 0 0 0 0 0 7 7 7

0 0 1 2 2 0

0 2 6 7 1 0

T a g D a ta

In d e x a d d re s s

0 0 0

7 7 7

( a ) M a in m e m o ry

( b ) C a c h e m e m o ry

Tag (6 bit) 00 - 63 Index (9 bit)

000 - 511



Direct mapping cache with block size of 8 words : Fig. 12-14

» 64 block x 8 word = 512 cache words size

 8 word 를 1 개의 block 단위로 update

 Set-associative mapping : Fig. 12-15 (two-way)



Direct mapping (

) 에서 같은 Index 에 다른 tag 를 자주 읽으면 속도가 저 하됨 ( 예제 02777, 01777 )



따라서 set 의 개수를 증가시키면 속도가 향상된다 .

0 0 0 0 0 7 0 1 0 0 1 7

0 1 0 1

7 7 0 7 7 7

0 2 0 2

3 4 5 0 6 5 7 8

6 7 1 0

In d e x T a g D a ta

B lo c k 0

B lo c k 1

B lo c k 6 3

T a g B lo c k W o rd

6 6 3

In d e x

0 1 3 4 5 0 0 2 5 6 7 0

0 2 6 7 1 0 0 0 2 3 4 0 0 0 0

7 7 7

In d e x T a g D a ta T a g D a ta

 Replacement Algorithm : cache miss

full 일때



1) LRU (Least Recently Used) : 최근에 가장 적게 사용된 block 교체



2) LFU (Least Frequently Used) : 사용 빈도가 가장 적은 block 교체



3) FIFO (First-In First-Out) : 가장 오래된 block 교체

 Writing to Cache : Cache Coherence(

)



Cache 에 있는 내용이 변경된 (WRITE) 경우 , Cache 의 block 이 교체되기 전에 main memory 에 내용도 update 해야 함

» 1) Write-through : Cache write 와 동시에 main memory 도 항상 동시에 write 한다 .

» 2) Write-back : Cache write 시에 내용이 변경되었다는 flag 만 set 해 놓고 나중에 block 이 교체되기 전에 flag 를 검사하여 변경된 부분만 나중에 write 한다 .

 따라서 Write-back 방식은 main memory 가 무효한 상태에 빠져 있을 수 있다 .

 Cache Initialization



Cache is initialized :

.

» 1) when power is applied to the computer

» 2) when main memory is loaded with a complete set of programs from auxiliary memory



valid bit

» indicate whether or not the word contains valid data

Main memory 와 Cache memory 의 내용이 동일해야 함 : 통일성 ( 일관성 ) 유지

Cache READ 는 문제 없음



12-6 Virtual Memory

 Virtual Memory : Auxiliary memory Main memory



Translate program-generated (Aux. Memory) address into main memory location

» Give programmers the illusion that they have a very large memory, even though the computer actually has a relatively small main memory



예제 : Intel Pentium Processor

» Physical Address Lines = A₀ - A₃₁ : 2³² = 2³⁰ X 2² = 4 Giga

» Logical Address = 46 bits address : 2⁴⁶ = 2⁴⁰ X 2⁶ = 64 Tera

 Address Space & Memory Space



Address Space : Virtual Address

» Address used by a programmer



Memory Space : Physical Address(Location)

» Address in main memory

 예제 : Fig. 12-16



address space (N) = 1024 K = 2

» Auxiliary Memory



memory space (M) = 32 K = 2

» main Memory

P ro g ra m 1 D a ta 1 , 1 D a ta 1 , 2

P ro g ra m 2 D a ta 2 , 1

P ro g ra m 1

D a ta 1 , 1 A u x ilia ry m e m o ry

M a in m e m o ry

A d d re s s s p a c e N = 1 0 2 4 K =

M e m o ry s p a c e M = 3 2 K = 2^{1 5}

2^{2 0}

 Memory table for mapping a virtual address : Fig. 12-17



Translate the 20 bits Virtual address into the 15 bits Physical address

 Address Mapping Using Pages : Fig. 12-18



Address mapping 을 간단하게 하기 위하여 사용

» Address space 와 memory space 를 fixed size 로 분할하여 사용함

 Address space : 1 K page 로 분할

 Memory space : 1 k block으로 분할

» Address space 의 4 개 page 가 memory space 에 block에 들어 갈수 있다 .

V irtu a l a d d r e s s

re g is te r ( 2 0 b its )

M e m o r y m a p in g

ta b le

M e m o ry ta b le b u ffe r r e g is t e r

M a in m e m o r y a d d re s s

r e g is te r ( 1 5 b it s )

M a in m e m o r y

M a in m e m o r y b u ffe r re g is t e r V irtu a l a d d re s s

P a g e 0

P a g e 7 P a g e 6 P a g e 5 P a g e 4 P a g e 3 P a g e 2 P a g e 1

B lo c k 0

B lo c k 3 B lo c k 2 B lo c k 1

A d d re s s s p a c e N = 8 K = 2^{1 3}

M e m o ry s p a c e M = 4 K = 2^{1 2}

 Memory table in a paged system : Fig. 12-19

1 0 1 0 1 0 1 0 1 0 0 1 1

0 0 0 1 1

1 0 0 1

1

0 1 10 1 1 10

0 1 1

0 0 0

1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1 T a b le

a d d re s s P re s e n c e

b it

P a g e n o . L in e n u m b e r

V irtu a l a d d re s s

0 1 0 1 0 1 0 1 0 0 1 1

B lo c k 0 B lo c k 1 B lo c k 2 B lo c k 3

M B R M a in m e m o ry

a d d re s s re g is te r

M e m o ry p a g e ta b le

M a in m e m o ry

 Associative memory page table : Fig. 12-20



Associative memory 를 이용하여 block number(01) 를 곧바로 찾는다

 Page( Block ) Replacement



Page Fault : the page referenced by the CPU is not in main memory

» a new page should be transferred from auxiliary memory to main memory



Replacement algorithm : FIFO 와 LRU 주로 사용

1 0 1 L in e n u m b e r

1 1 1 0 0 0 0 1 1 1

1 1 0 1 0 1 0 1 0 1 0 1 0 0 0

A rg u m e n t re g is te r K e y re g is te r

A s s o c ia tiv e m e m o ry

P a g e n o .

P a g e n o . B lo c k n o .

V irtu a l m e m o ry



12-7 Memory Management Hardware

 Basic components of a Memory Management Unit



1) Address mapping



2) Common program sharing



3) Program protection

 MMU : OS 에서 지원 해야 함



1) CPU 에 내장된 형태



2) 별도의 memory controller 형태

 Segment



A set of logically related instruction or data elements associated with a given name



예제 : a subroutine, an array of data, a table of symbol, user’s program

 Logical Address



the address generated by a segmented program



similar to virtual address

» Virtual Address : fixed-length page

» Logical Address : variable-length segment

 Segmented-page MMU



Fig. 12-21(a) : 2 개의 table(segment, page) 을 사용함

» 따라서 2 개의 table 을 읽는데 많은 시간이 소모됨



Fig. 12-21(b) : Associative memory 를 이용한 1 개의 table 을 사용함

» 따라서 속도가 빠르다

» TLB (Translation Look-a-side Buffer)

 associative memory를 이용한 most recently reference table

 Numerical Example



예제 : Logical address & Physical address (Fig. 12-22)

» Logical Address :

 4 bit segment : 16 segments

 8 bit page : 256 pages

 8 bit word : 256 address field

» Physical Address :

 12 bit block : 4096 blocks

 8 bit word : 256 address field

( a ) L o g ic a l a d d re s s f o rm a t : 1 6 s e g m e n ts o f 2 5 6 p a g e s e a c h , e a c h p a g e h a s 2 5 6 w o rd s

× 3 2 P h y s ic a l m e m o ry

2^{2 0}

B lo c k W o rd

1 2 8

( b ) P h y s ic a l a d d re s s f o rm a t : 4 0 9 6 b lo c k s o f 2 5 6 w o rd e a c h , e a c h w o rd h a s 3 2 b its

S e g m e n t P a g e W o rd

4 8 8

Address or Index

P a g e 0

P a g e 4 P a g e 3 P a g e 2 P a g e 1 P a g e n u m b e r

6 0 0 0 0 6 0 0 F F

H e x a d e c im a l a d d re s s

S e g m e n t P a g e B lo c k 6

6 6 6 6

0 0

0 4 0 3 0 2 0 1

0 1 2

A 6 1 0 5 3 0 1 9 0 0 0

( a ) L o g ic a l a d d re s s a s s ig n m e n t ( b ) S e g m e n t- p a g e v e rs u s m e m o ry b lo c k a s s ig n m e n t

6 0 1 0 0 6 0 1 F F 6 0 2 0 0 6 0 2 F F 6 0 3 0 0 6 0 3 F F 6 0 4 0 0 6 0 4 F F



예제 : Logical & Physical address assignment (Fig. 12-23)

Logical Address

Page Table

Block number

019

Segment Page

3 5

A 3 0

6

F

S e g m e n t ta b le

0 1 2

A 6 1 0 5 3 0 1 9 0 0 0

0 1 2 0 0

3 5

3 8 3 7 3 6

3 9

A 3

P a g e ta b le

B lo c k 0

6 0 2 7 E

L o g ic a l a d d re s s ( in h a x a d e c im a l)

B lo c k 1 2

3 2 b it w o rd P h y s ic a l m e m o ry 0 0 0 0 0

0 0 0 F F

0 1 2 0 0 0 1 2 F F

0 1 9 0 0 0 1 9 F F 0 1 9 7 E

( a ) S e g m e n t a n d p a g e ta b le m a p p in g

6 0 2 0 1 9

6 0 4 A 6 1

S e g m e n t P a g e B lo c k

( b ) A s s o c ia tiv e m e m o ry ( T L B )

S e g m e n t P a g e W o rd

+

S e g m e n t ta b le P a g e ta b le

L o g ic a l a d d re s s

B lo c k W o rd P h y s ic a l a d d re s s ( a ) L o g ic a l to p h y s ic a l a d d re s s m a p p in g

S e g m e n t P a g e B lo c k

A rg u m e n t re g is te r

( b ) A s s o c ia tiv e m e m o ry tra n s la tio n lo o k - a s id e b u ffe r ( T L B )

+

 Memory Protection



Typical segment descriptor : Fig. 12-25



Access Rights : protecting the programs residing in memory

» 1) Full read and write privileges : no protection

» 2) Read only : write protection

» 3) Execute only : program protection

» 4) System only : operating system protection

B a s e a d d re s s L e n g th P ro te c tio n segment

Base address Length

1 2 8 × 8 R A M 1 C S 1

A D 7 W R R D C S 2

1 2 8 × 8 R A M 2 C S 1

A D 7 W R R D C S 2

1 2 8 × 8 R A M 4 C S 1

A D 7 W R R D C S 2

1 2 8 × 8 R A M 3 C S 1

A D 7 W R R D C S 2

1 2 8 × 8 R O M C S 1 C S 2

A D 9 D a ta D a ta D a ta

D a ta

D a ta C P U

W R R D 1 6 - 1 1 1 0 9 8 7 - 1

A d d re s s b u s

D a ta b u s

D e c o d e r 3 2 1 0

1 - 7 8 9