MOS Transistors as Switches

MOS Transistors as Switches

G (gate) D (drain) (source)S G D S nMOS transistor:

Closed (conducting) when Gate = 1 (V_DD)

Open (non-conducting) when Gate = 0 (ground, 0V)

pMOS transistor:

Closed (conducting) when Gate = 0 (ground, 0V)

Open (non-conducting) when Gate = 1 (VDD)

For nMOS switch, source is typically tied to ground and is used to pull-down signals:

G

Out

S

when Gate = 1, Out = 0, (OV)

when Gate = 0, Out = Z (high impedance)

For pMOS switch, source is typically tied to VDD, used to pull signals up:

Out G

S

when Gate = 0, Out = 1 (V_DD)

when Gate = 1, Out = Z (high impedance)

Note: The MOS transistor is a symmetric device. This means that the drain and source terminals are interchangeable. For a conducting nMOS transistor, VDS > 0V; for the pMOS transistor, VDS

The CMOS Inverter

Out I I Out Truth Table I Out 0 1 1 0 GND V_DD Rin→∞

Note: Ideally there is no static power dissipation. When "I" is fully is high or fully low, no current path between VDD and GND exists (the output is usually tied to the gate of another MOS

transistor which has a very high input impedance).

Power is dissipated as "I" transistions from 0→1 and 1→0 and a momentory current path exists between Vdd and GND. Power is also dissipated in the charging and discharging of gate capacitances.

Parallel Connection of Switches

A Y B Y = 0, if A or B = 1 A + B Y A B Y = 1 if A or B = 0 A + B

Series Connection of Switches

A Y B Y = 0, if A and B = 1 A ⋅ B A B Y Y = 1, if A and B = 0 A ⋅ B

NAND Gate Design

p-type transistor tree will provide "1" values of logic function n-type transistor tree will provide "0" values of logic function

Truth Table (NAND):

AB 00 1 01 1 10 1 11 0 K-map (NAND): 1 1 1 0 0 1 0 1 A B

NAND circuit example:

Y A B Vdd Ptree = A + B Ntree = A ⋅ B Y A B

NOR Gate Design

p-type transistor tree will provide "1" values of logic function n-type transistor tree will provide "0" values of logic function

Truth Table: AB 00 1 01 0 10 0 11 0 K-map: 1 0 0 0 0 1 0 1 A B

NOR circuit example:

Y A B Vdd Y A B Ptree = A ⋅ B Ntree = A + B

What logic gate is this?

Y A B Vdd Y = 1 when A ⋅ B Y = 0 when A + B

Answer: AND function, but poor design!

Why? nMOS switches cannot pass a logic "1" without a threshold voltage (VT) drop.

G D S VDD VDD VDD - VT where VT = 0.7V to 1.0V (i.e.,

threshold voltage will vary) output voltage = 4.3V to 4.0V, a weak "1"

The nMOS transistor will stop conducting if VGS < VT. Let VT = 0.7V, G 5V S →D 0V → 5V D → ? 0V → _?

As source goes from 0V → 5V, VGS goes from 5V → 0V.

When VS > 4.3V, then VGS < VT, so switch stops conducting.

VD left at 5V − VT = 5V − 0.7V = 4.3V or VDD− VT.

What about nMOS in series? 5V 0V→ 5V _{0V→ 4.3V} 0V→ 4.3V _{0V→ 4.3V} 5V - 0.7V 4.3V 5V 5V 5V 0V → (VDD−VT)

For pMOS transistor, VT is negative.

pMOS transistor will conduct if |VGS| > |VTp| (VSG > |VTp|),

or VGS < VTp G 0V 5V S _D conducting VTp = −0.7V VGS = 0V − 5V = −5V VGS < VTp or |VGS| > |VTp| −5V < −0.7V 5V > 0.7V

How will pMOS pass a "0"? G 0V

S →D

5V → ? D → ? 5V → 0V

When |VGS| < |VTp|, stop conducting

So when |VGS| < |−0.7V|, VD will go from 5V

→ 0.7V,

a weak "0"

How are both a strong "1" and a strong "0" passed? Transmission gate pass transistor configuration

I A B When I = 1, B = strong 1, if A = 1; B = strong 0, if A = 0 When I = 0, non-conducting

About that AND Gate...

Y A B Vdd No!!!

Poorly designed AND (circuit designer fired)

Instead use this,

Y A B A Vdd Y B

More Complex Gates

F = AB + CD

⇒ Ntree will provide 0's, Ptree will provide 1's

0's of function F is

F

, ⇒

F = AB + CD = AB + CD

nMOS transistors need high true inputs, so it is desirable for all input variables to be high true, just as above. Y A B C D

AB + CD

Likewise, a Ptree will provide 1's.

F = AB + CD

, need a form involving

A

,

B

,

C

,

D

Apply DeMorgan's Theorem:

F = AB

⋅

CD = (A + B)

⋅

(C + D)

Implementation ⇒

Y

A B

Can also use K-maps:

F = AB + CD

1 1 1 AB CD 0 0 1 0 0 0 0 1 1 1 0 1 1

For Ntree, minimize 0's; for Ptree, minimize 1's

AB CD 0 0 0 0 0 0 0 Ntree = AB + CD 1 1 1 AB CD 1 1 1 1 1 1

_P

tree

= A

⋅

C + A

⋅

D + B

⋅

C + B

⋅

D

= A (C + D) + B (C + D)

= (A + B)

⋅

(C + D)

Introduction to Static Load Inverters

1) I R O resistor load VOH = 5V,

VOL close to 0V, depends on ratio R/RON

When I = 1, inverter dissipates static power.

Switching point of inverter depends on ratio of R to RON (on resistance of nMOS device.

Note: output can swing from almost 0V to 5V (VDD)

2)

I

O D S

Load is enhancement-mode nMOS device.

Again, static power dissipation occurs when I = 1.

Note: output swings from nearly 0V to (VDD− VTn)

Using a transistor as a load tends to require much less silicon area than a resistor. VOH = VDD− VTn,

Depletion-mode nMOS

nMOS device with VTn < 0V (negative threshold voltage). Device is always conducting if VGS >

0V. 3) I O D S VGS = 0V always

Load device is always on, looks like a load resistor.

Dissipates static power when I = 1

VOH = 5V; VOL nearly 0V, depending on ratio of RON,dep to RON,enh.

Depletion-mode devices were used before it was economical to put both p-type and n-type devices on the same die.

4) pMOS device as static load

I

O D

S Here also the load device is always on (conducting).

Dissipates static power when I = 1.

Basic MOS Device Equations

Gate

Source Drain

Bulk (or substrate for nMOS device in n-well technology)

The nMOS device is a four terminal device: Gate, Drain, Source, Bulk.

Bulk (substrate) terminal is normally ignored at schematic level, usually tied to ground for the nMOS case. In analog applications, however, the bulk terminal may not be ignored.

Gate controls channel formation for conduction between Drain and Source. Drain at higher potential than Source — Source usually tied to GND to act as pull-down (nMOS).

Three regions of operations — first-order (ideal) equations: Cutoff region

ID = 0A VGS≤ VTn (nMOS threshold voltage)

Linear region ID = ß











−

−

2

V

)V

V

(V

2 DS DS T GS n



0 < VDS < VGS− VTn

Note: ID is linear with respect to (VGS− VTn) only when

(

V

2

)

2 DS is small. Saturation region ID =

(

V

_GS

V

_T

)

2 0 < V

2

ß

n

−

GS− VTn < VDS

Device parameters:

ß = transistor gain factor, dependent on process parameters and device geometry (Kn)

ß = µ

ε

t

ox

W

L

process dependent, constant

under control of the designer

As W/L increases, effective RON of device decreases µ = surface mobility of the carriers in the channel

ε = permittivity of the gate insulator tox = thickness of the gate insulator

See Figure 2.5, 2.8 concerning µ, ε, and tox SPICE represents ß by a factor given by

K' = µCox = µ _toxε = KP So, ID =

(

V

_GS

V

_T 2

L

W

2

K'

n

−

)

; saturation region

VI characteristic

V

DS

V

GS

I

D V_DS V_GS1 V_GS2 V_GS3 V_GS4 V_GS5 GS |V_GS - V_T| = |V_DS| boundary between linear & saturation regions (dashed line)

SATURATION LINEAR CUTOFF V D

I

Things to note:

In the "linear" region, ID becomes less and less linear with VGS as VDS becomes large.

This is because the

(

V

_DS2

2

)

term in the linear region grows large.

Higher VGS values increase channel conductance allowing for higher values of ID for a

*MOSFET Characteristics Vds 1 0 DC 10

Vgs 2 0 DC -.723 Vdummy 3 0 DC 0 M1 1 2 3 3 Mfet

.MODEL Mfet NMOS(KP=3686U VTO=2.30 LAMBDA=0.137) .DC Vds 0 10 .2 Vgs 2.5 5 .5

.probe .end

What do W and L physically look like?

nMOSFET layout: W L Drain n+ diffusion Source n+ diffusion Gate (polysilicon)

In digital logic, typically will draw all transistors with the minimum gate length and vary the width.

Larger W ⇒larger transconductance (more current flow for given gate voltage), higher gate capacitance

During fabrication process, the actual width and length of the channel can be reduced by diffusion from the bulk, source, and drain into the device channel.

SPICE has some MOSFET model parameters to account for this effect, LD and WD, where the actual the actual length and width is calculated as

Leffective = Ldrawn - 2 × LD

Weffective = Wdrawn - 2 × WD

Ideal Inverter

Vout Vin VDD VDD 2 switching point

Actual Inverter Characteristics, some definitions

V

_in

(V)

V

_OH

V

_OL

V

_IL

V

_IH

V

_th

V

out

(V)

• VIL represents the maximum logic 0 (LOW) input voltage that will guarantee a logic 1

(HIGH) at the output

• VIH represents the minimum logic 1 (HIGH) input voltage that will guarantee a logic 0

Noise Margin

Illustration of Noise Margin:

NM_L NM_H Vin Input logic 1 Input logic 0 0V V_IL V_IH V_DD Vout V_OH V_DD 0V V_OL Output logic 1 Output logic 0

Calculate noise margin using

NML = VIL - VOL NMH = VOH - VIH

How do we determine VIL, VOL, VOH, and VIH?

CMOS Inverter Regions of Operation

0 1 2 3 4 5 0 100 3 10-5 6 10-5 9 10-5 1.2 10-4 1.5 10-4 0 1 2 3 4 5 Vout (V) I DD (A) V_in (V) V_out I_DD A B D E C Region A:

0 ≤ Vin < VTn ⇒ pMOS nonsaturated; nMOS cutoff

• nMOS is cutoff because Vin < VTn

Why is the pMOS device in the linear region?

Linear region ≡ VSDp < VSGp - |VTp|

(5 − 5)V < (5 − 0)V − |−0.7|V

[for VDD = 5V and VTp = −0.7V]

0V < 4.3V

Region B:

VTn≤ Vin < Vth ⇒ pMOS nonsaturated, nMOS saturated

Why is nMOS saturated? Is VDSn > VGSn - VTn?

Because (VDSn = Vout) > Vth and (VGSn = Vin) < Vth ,

then VDSn > VGSn - VTn

Vout > Vin - VTn [B-1]

Why is pMOS in linear region?

It started out in linear and will remain in linear as long as VSDp < VSGp - |VTp|

(VDD - Vout) < (VDD - Vin) - |VTp|

Vin < Vout - |VTp| [B-2]

Vout in the above expression (Eqn. [B-2]) is decreasing towards Vth and Vin is increasing

towards Vth. When Eqn. [B-2] no longer holds, then the pMOS device will become

saturated.

For the pMOS device, then

regions A ⇒ B ⇒ C correspond to linear ⇒ linear ⇒ saturated, respectively.

How can you predict the output voltage for region B?

The nMOS is saturated, so IDn =

(V

_in

V

_T

)

2

2

ß

n n

−

₌ 2 T GS

V

)

(V

2

ß

n n n

−

The pMOS is linear, so

IDp =

(

2(V

_SG

|

V

_T

|)V

_SD

(V

_SD

)

2

)

2

ß

p p p p p

₋

₋

IDp =

(

2(V

_DD

V

_in

|

V

_T

|)(V

_DD

V

_out

)

(V

_DD

V

_out

)

2

)

2

ß

−

−

−

−

−

p p

Can solve for Vout since

IDn = IDp GND S D D S IDp IDn VDD

Equivalent circuit for region B ⇒ Vout IDn

Region C:

Vin = Vth ⇒ pMOS saturated, nMOS saturated

In order for nMOS to be saturated, need

VDSn > VGSn− VTn

Vout > Vin− VTn

In order for pMOS to be saturated, need

VSDp > VSGp− |VTp|

VDD− Vout > VDD− Vin− |VTp|

Vout < Vin + |VTp|

So _{Vout in region C,}

Vin− VTn < Vout < Vin + |VTp|

The CMOS inverter has very high gain in region C so small changes in Vin produce large

changes in Vout. No closed form equation for Vout. Somewhere in this region, Vout = Vin,

which is the switching point for this gate. Equivalent circuit for region C:

Vout IDn

IDp VDD

What is Vin in region C?

In region C, both devices in saturation so

IDp =

(V

_DD

V

_in

|

V

_T

|)

2

2

ß

p p

₋

₋

IDn =

(V

_in

V

_T

)

2

2

ß

n n

−

So, using IDn = IDp, Vin can be solved for (more on this later....)

Region D:

Vth < Vin≤ VDD− |VTp| ⇒ pMOS saturated, nMOS linear

Hence, IDp =

(V

_DD

V

_in

|

V

_T

|)

2

2

ß

p p

₋

₋

IDn =

(

)

2 out out T in n

_2(V

_V

_)V

_V

2

ß

−

−

n

Again, since IDp = IDn, we can solve for Vout:

Vout2− 2(Vin− VTn)Vout +

(V

_DD

V

_in

|

V

_T

|)

2

ß

ß

p n p

₋

₋

= 0 using x =

a

ac

b

b

2

4

2

₋

±

−

and, recognizing from above,

a = 1, b = −2(Vin− VTn), c =

(V

_DD

V

_in

|

V

_T

|)

2

ß

ß

p n p

₋

₋

we get

Vout = (Vin− VTn) − _{in T} 2

(V

_in

V

_DD

|

V

_T

|)

2

ß

ß

)

V

(V

_p n p n

−

−

−

−

.

Equivalent circuit for region D ⇒ Vout IDp

Region E:

Vin > VDD− |VTp| ⇒ pMOS is cutoff, nMOS is linear mode

Since VSGp = VDD− Vin (< |VTp|),

∴ Vout≅ 0V

CMOS Inverter Transfer Characteristic

0 1 2 3 4 5 0 100 3 10-5 6 10-5 9 10-5 1.2 10-4 1.5 10-4 0 1 2 3 4 5 Vout (V) I DD (A) V_in (V) V_out I_DD A B D E C Analysis:

VOH: Vin < VTn, the nMOS transistor is in cutoff while the pMOS transistor is turned-on

(inversion layer established). The result is VOH≅ VDD.

VOL: (VDD− Vin) < |VTp|, the pMOS is in cutoff while the nMOS is on and providing a

conduction channel to ground. Hence, VOL≅ 0V.

VIL: Input low voltage, here the nMOS transistor is saturated and the pMOS is nonsaturated.

Equating the currents provides

2 T IL

V

)

(V

2

ß

n n

−

₌

(

2

)

out DD out DD T IL DD

V

|

V

|)(V

V

)

(V

V

)

2(V

2

ß

−

−

−

−

−

p p .

VIL: (continued) Since two unknowns exist, Vin = VIL and Vout, a second equation is needed.

Use the unity-gain condition to obtain this second equation,

in out

dV

dV

=

)

V

/

I

(

)

V

/

I

(

)

V

/

I

(

out D in D in D

∂

∂

∂

∂

−

∂

∂

p p n = −1, provides VIL















+

p n

ß

ß

1



= 2Vout +













p n

ß

ß





VTn− VDD− |VTp|.

Now the two equations needed to solve for VIL and Vout exist.

VIH: Input high voltage, here the nMOS is nonsaturated and the pMOS is saturated.

Equating the drain currents yields

(

2

)

out out T IH V )V V 2(V 2 ß − − _n n ₌ 2 T IH DD V |V |) (V 2 ß p p _{− −} ,

the first of two equations needed to solve two unknowns, Vin = VIH and Vout. Use the

unity-gain condition to get the second,

in out

dV

dV

=

)

V

/

I

(

)

V

/

I

(

)

V

/

I

(

out D in D in D

∂

∂

∂

∂

−

∂

∂

n n p _{= −1.} This provides VIH











+

n p

ß

ß

1



= 2Vout + VTn +

(V

|

V

|)

ß

ß

T DD p n p

₋

,

Vth: At the CMOS inverter's switching point, or inverter threshold, Vth = Vin = Vout and both

the pMOS and nMOS transistors are saturated. Again, equating the drain currents,

2 T th

V

)

(V

2

ß

n n

−

₌ 2 T th DD

V

|

V

|)

(V

2

ß

p p

₋

₋

is obtained which can be easily solved to provide Vth,

Vth =

















+

−

+

n p p n p n

ß

ß

1

|)

V

|

(V

ß

ß

V

_{T DD T}

Note: switching point of gate (Vth) is

2

V

_DD -if- p n

ß

ß

= 1 and VTn = −VTp.

So, switching point of inverter is function of the ratio of the nMOS/pMOS gains and the threshold voltages of the nMOS, pMOS transistors.

β

n/

β

p

Ratio

The ßn (gain of nMOS) / ßp (gain of pMOS) ratio determines the switching point of the CMOS

inverter. 0 1 2 3 4 5 0 1 2 3 4 5

V

_out

(V)

V

_in

(V)

ß_n ß_p = 10 ß_ßn_p = 1 ßßn_p = 0.1 Strong pull-down Strong pull-up Equal pull-up/pull-down "strength" VDD 2 Switching point = V_DD/2 if ß_n/ß_p = 1 and V_Tn = |V_Tp|

Recall that

ß = _toxµε W_{L .}

If we assume that the nMOS and pMOS transistors have equal W/L ratios, then

ß_n ß_p = µ_nε tox W_n L_n µ_pε tox W_p L_p = µ_µn p = electron mobility hole mobility .

In silicon, the ratio µ_n/µ_p is usually between 2 to 3.

This means, that if Ln = Lp,

then W_p must be 2 to 3 times W_n

in order for ß_n = ß_p . 0 1 2 3 4 5 0 1 2 3 4 5

V

_out

V

_in if Wp Lp = W n Ln because ßn ßp > 1 VDD 2

Calculate the switching point of a static load inverter as function of ßn/ßp: In region C, already know nMOS device is saturated from previous analysis.

Vin

Vout VDD

For pMOS to be saturated need: VSDp > VSGp− |VTp|

VDD− Vout > VDD− 0V − |VTp|

Vout < |VTp|

Not true!!! (If Vout in region C is about

2 V_DD and 2 V_DD > |VTp|

(typically this is true)) ∴ pMOS must be in linear region

Then _D (V_GS V_T )2 2 ß I _n= n _n− _n (V_in V_T )2 2 ß n n ₋ = and _D

(

2(V_SG |V_T |)V_SD V_SD 2

)

2 ß I _p = p _p− _{p p} − _p

(

2

)

out DD out DD T DD D ₂ 2(V |V |)(V V ) (V V ) ß I _p = p − _p − − −

Equate IDn = IDp and solve for Vout.

2 T in 2 T DD T out | V | (V |V |) _ßß (V V ) V _n p n p p + − − − =

Can also solve for ß_n/ß_p,

2 T in 2 T out 2 T DD ) V (V |) V | (V |) V | (V ß ß n p p p n − − − − =

Consider again 2 T in 2 T out 2 T DD ) V (V |) V | (V |) V | (V ß ß n p p p n − − − − =

for the pseudo-nMOS inverter.

Let |VTp| = VTn = 0.2VDD and Vin = Vout =

2 V_DD . Then, for VDD = 5V, p n

ß

ß

≅ 6.1 !!!

Note that this is very different result from the CMOS inverter case!

If VDD = 3.3V, but the value of VTn = |VTp| is unchanged (i.e., 1V in the above example),

then p n

ß

ß

≅ 11.5

for a switching point equal to 2 V_DD

.

The ßn/ßp ratio depends on the absolute value of VDD! This means that the operation of

the pseudo-nMOS inverter will NOT scale with VDD (for a given CMOS technology).

For the CMOS inverter, the ßn/ßp ratio for a switching point of VDD/2 is independent of

VDD so its operation will scale with supply voltage. This is a another big advantage of

CMOS technology.

Not unusual for static CMOS circuits to operate over a very large range of power supply voltages, i.e., 2.0V to 6.0V is common.