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Gate tunable, normally on to normally off memristance transition inpatterned LaAlO3/SrTiO3 interfaces

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Figure

Fig. 1. (a) Sketch of the device depicting the wire, lateral gates, Ti/Au contacts and back gate
Fig. 2. (a) Current-voltage-characteristics of the device. The arrows indicate the sweep cycle direction
Fig. 3. (a) Current-voltage-characteristics for different back gate voltages obtained after an annealing time  For increasing annealing time, the maximal area is observed at larger gate voltages
Fig. 4. (a) Conductance  Larger gate voltages lead to enhanced conductance values after applying 50 pulses as shown in (b)

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