Objectives
We know that CPU can be shared by a set of processes. As a result of
CPU scheduling, we can improve both the CPU utilization and the speed of the computer’s response to the users.
To realize this increase in performance, however we must keep
several processes in memory; that is , we must share memory.
The main objective here is to understand the various ways of
managing memory.
To discuss various memory-management techniques, including paging
Address Binding
Program must be brought (from disk) into memory for it to be executed.
Depending on the memory management in use, the process may be
moved between disk and memory during its execution.
The collection of processes on the disk that is waiting to be brought into
memory for execution forms the input queue.
Most systems allow a user process to reside in any part of the physical
memory.
In most cases, a user program will go through several steps where
binding takes place at every level.
Binding of Instructions and Data to Memory
Address binding of instructions and data to memory addresses can happen at
three different stages
Compile time: If you know at compile time where the process will reside in
memory, then absolute code can be generated; must recompile code if starting location changes
Load time: Must generate relocatable code if memory location is not
known at compile time
Execution time: Binding delayed until run time if the process can be
Logical vs. Physical Address Space
The concept of a logical address space that is bound to a separate
physical address space is central to proper memory management
Logical address – generated by the CPU; also referred to as
virtual address.
Physical address – address seen by the memory unit, one which
is loaded into the memory address register of the memory.
Logical and physical addresses are the same in compile-time and
Logical vs. Physical Address Space
Logical address space : The set of all logical addresses generated by a
program is a logical address space.
Physical address space: The set of all physical addresses corresponding
Memory-Management Unit (
MMU
)
Hardware device that maps virtual to physical address
In MMU scheme, the value in the relocation register is added to
every address generated by a user process at the time it is sent to memory
Swapping
A process can be swapped temporarily out of memory to a backing store, and then
brought back into memory for continued execution.
Assume a multiprogramming environment with round robin scheduling implementation.
The quantum must be sufficiently large that reasonable amounts of computing are
done between swaps.
Roll out, roll in – swapping variant used for priority-based scheduling algorithms;
lower-priority process is swapped out so higher-priority process can be loaded and executed.
Normally, a process that is swapped out will be swapped back into the same memory
Swapping
Backing store – fast disk large enough to accommodate copies of all
memory images for all users; must provide direct access to these memory images
System maintains a ready queue of ready-to-run processes which have
memory images on disk.
Major part of swap time is transfer time; total transfer time is directly
Contiguous Allocation
Main memory usually into two partitions:
Resident operating system
User processes
Relocation registers used to protect user processes from each other, and
from changing operating-system code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each logical address
must be less than the limit register
Base and Limit Registers
Memory Management
1. Keep track of what parts of memory are in use.
2. Allocate memory to processes when needed.
3. Deallocate when processes are done.
4. Swapping between main memory and disk, when memory is too small to
Contiguous Allocation (Cont)
Multiple-partition allocation
Hole – block of available memory; holes of various size are
scattered throughout memory
When a process arrives, it is allocated memory from a hole
large enough to accommodate it
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
Dynamic Storage-Allocation Problem
First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless
ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
How to satisfy a request of size
n
from a list of free holes. There are
many solutions to this problem. The set of holes is searched to
determine which hole is best to allocate.
Best Fit
Best fit: The allocator places a process in the smallest block of unallocated
Worst Fit
Worst fit: The memory manager places a process in the largest block of
First Fit
First fit: There may be many holes in the memory, so the operating system,
Example
The shaded areas are allocated blocks; the white
areas are free blocks.
The next FOUR memory requests are 20K, 50K, 10K
and 30K (loaded in that order).
Using the following placement algorithms, show the
partition allocated for the requests.
First-fit
Best-fit
40K
80K
30K
50K
30K
1
Example: First-fit
20K, 50K, 10K and 30K (in that order).
Allocate for 20K
40K
80K
30K
50K
30K
1
0K
2
0K
20
K
2
0K
10
K
1
0K
2
0K
Example: First-fit
20K, 50K, 10K and 30K (in that order).
Allocate for 20K
Allocate for 50K
40K
80K
30K
50K
30K
1
0K
2
0K
20
K
2
0K
10
K
1
0K
2
0K
Example: First-fit
20K, 50K, 10K and 30K (in that order).
Allocate for 20K
Allocate for 50K
Allocate for 10K
40K
80K
30K
50K
30K
1
0K
2
0K
20
K
2
0K
10
K
1
0K
2
0K
20
50
Example: First-fit
20K, 50K, 10K and 30K (in that order).
Allocate for 20K
Allocate for 50K
Allocate for 10K
Allocate for 30K
40K
80K
30K
50K
30K
1
0K
2
0K
20
K
2
0K
10
K
1
0K
2
0K
20
50
Example: Best-fit
20K, 50K, 10K and 30K (in that order).
40K
80K
30K
50K
30K
1
Example: Best-fit
20K, 50K, 10K and 30K (in that order).
Allocate for 20K
40K
80K
30K
50K
30K
1
0K
2
0K
20
K
2
0K
10
K
1
0K
2
0K
Example: Best-fit
20K, 50K, 10K and 30K (in that order).
Allocate for 20K
Allocate for 50K
40K
80K
30K
50K
30K
1
0K
2
0K
20
K
2
0K
10
K
1
0K
2
0K
Example: Best-fit
20K, 50K, 10K and 30K (in that order).
Allocate for 20K
Allocate for 50K
Allocate for 10K
40K
80K
30K
50K
30K
1
0K
2
0K
20
K
2
0K
10
K
1
0K
2
0K
20
50
Example: Best-fit
20K, 50K, 10K and 30K (in that order).
Allocate for 20K
Allocate for 50K
Allocate for 10K
Allocate for 30K
40K
80K
30K
50K
30K
1
0K
2
0K
20
K
2
0K
10
K
1
0K
2
0K
20
50
Contiguous Allocation Techniques
Given five memory partitions of 100Kb, 500Kb, 200Kb, 300Kb, 600Kb (in
Contiguous Allocation Techniques
First-fit:
212K is put in 500K partition 417K is put in 600K partition
112K is put in 288K partition (new
partition 288K = 500K - 212K)
426K must wait
Best-fit:
212K is put in 300K partition 417K is put in 500K partition 112K is put in 200K partition 426K is put in 600K partition
Worst-fit:
212K is put in 600K
partition 417K is put in 500K partition 112K is put in 388K partition
426K must wait In this example,
FRAGMENTATION
All the
preceding algorithms suffer from:External Fragmentation
As processes are loaded and removed from memory the free memory
is broken into little pieces and enough total space exists to satisfy
a
request, but it is not contiguous.
Internal Fragmentation
Internal Fragmentation – allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a partition, but not being used
One solution to Reduce external fragmentation is by compaction
Shuffle memory contents to place all free memory together in
one large block
Compaction is possible only if relocation is dynamic, and is
done at execution time as it requires changing the base register to reflect the new base address.
This scheme can be expensive.
Another possible solution is to permit the logical address space
Paging
Logical address space of a process can be noncontiguous; process
is allocated physical memory whenever the latter is available
Divide physical memory into fixed-sized blocks called frames (size
is power of 2, between 512 bytes and 16 MB per page)
Divide logical memory into blocks of same size called pages
When a process is to be executed, its pages are loaded into any
Paging Hardware
The pages size (like the frame size) is defined by the hardware. The size of
Paging
No External Fragmentation.
Frame Table
Since the operating system is managing physical memory, it must be
aware of the allocation details of physical memory.: which frames are allocated, which frames are available, how many total frames are there and so on.
So, to keep track of all these frames, operating system maintains a
Hardware Support
Each operating system has its own methods fro storing page tables. Most
allocate a page table for each process. And a pointer to the page table is stored with the other register values in the process control block.
The hardware implementation of the page table can be done in several
ways. In the simplest case, the page table is implemented as a set of dedicated registers.
The use of registers for page table is satisfactory if the page table is
Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PRLR) indicates size of the page table
In this scheme every data/instruction access requires two memory
accesses. One for the page table and one for the data/instruction.
The two memory access problem can be solved by the use of a special
Effective Access Time
If the page number is found in the TLB, that is known as TLB hit.
Otherwise, it is known as TLB miss.
The percentage of times that a particular page number is found in
the TLB is called TLB hit ratio.
An 80 percent TLB hit ratio means that we find the desired page
Memory Protection
Memory protection implemented by associating protection bit with
each frame
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
“invalid” indicates that the page is not in the process’ logical
Structure of the Page Table
Hierarchical Paging
Hashed Page Tables
Hierarchical Page Tables
Break up the logical address space into multiple page tables
Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into: a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into: a 12-bit page number
a 10-bit page offset
Thus, a logical address is as follows:
where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table
page number page offset
pi p2 d
Hashed Page Tables
Common in address spaces > 32 bits
The virtual page number is hashed into a page table
This page table contains a chain of elements hashing to the
same location
Virtual page numbers are compared in this chain searching for a
match
If a match is found, the corresponding physical frame is
Inverted Page Table
One entry for each real page of memory
Entry consists of the virtual address of the page stored in
that real memory location, with information about the process that owns that page
Decreases memory needed to store each page table, but
increases time needed to search the table when a page reference occurs
Use hash table to limit the search to one — or at most a
Segmentation
An important aspect of memory management that became unavoidable with
paging is the separation of user’s view of memory and the actual physical memory.
Memory-management scheme that supports user view of memory A program is a collection of segments
A segment is a logical unit such as:
main program procedure function method object
local variables, global variables stack
Segmentation
Elements within a segment are identified by their offset from the beginning
of the segment: the first statement of the program, the seventh stack frame entry in the stack and so on.
Segmentation is a memory management technique that supports this user
view of memory.
A logical address space is a collection of segments. Each segment has a
name and length.
The addresses specify both the name of the segment and the offset with in
Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>,
Segment table – maps one-dimensional physical addresses; each table
entry has:
base – contains the starting physical address where the segments
reside in memory
limit – specifies the length of the segment
Segment-table base register (STBR) points to the segment table’s
location in memory
Segment-table length register (STLR) indicates number of segments
used by a program;
Segmentation
For example, segment 2 is 400 bytes long and begins at location 4300.
thus a reference to byte 53 of segment 2 is mapped onto location 4300+53 = 4353.
A reference to segment 3 byte 852 is mapped to 3200+852 = 4052.
A reference to byte 1222 of segment 0 would result in a trap to the
External Fragmentation
Segmentation may cause external fragmentation, when all blocks of free
memory are too small to accommodate a segment.
In this case, the process may simply have to wait until some memory ( or at
least a larger hole) becomes available, or until compaction creates a larger hole.
If the CPU scheduler must wait for one process, because of a memory
Example: The Intel Pentium
Supports both segmentation and segmentation with paging
In Pentium systems, the CPU generates logical addresses which are
Given to segmentation unit
Which produces linear addresses
Linear address given to paging unit
Which generates physical address in main memory
Intel Pentium Segmentation
The Pentium architecture allows a segment to be as large as 4 GB and the
Maximum number of segments per process is 16 KB.
The logical address space of a process is divided into two partitions.
First 8 KB – private to that process (Local descriptor table)
Last 8 KB – shared among all the processes. (Global descriptor table).
Each entry in the LDT and GDT consists of an 8-byte segment descriptor with detailed information about a particular segment , including the base location and limit of that segment.
The logical address is a pair (selector, offset) where the selector is a 16-bit number:
In which s designates the segment number
G indicates whether the segment is in GDT or LDT P deals with the protection.
Intel Pentium Segmentation
The segment number in selector part points to the appropriate entry in the GDT or LDT.
The base and limit information about the segment in question is used to generate the linear address.
First, the limit is checked for address validity. If the address is not valid, a memory fault is generated.
Intel Pentium Paging
The Pentium architecture allows a page size of either 4 KB or 4 MB.
For 4 KB pages, the Pentium uses a two level paging scheme in which the
division of the 32 bit linear address is as follows:
Pentium Paging Architecture
The ten high order bits reference an entry in the outermost page table, which the Pentium terms the page directory.(The CR3 register points to the page
directory for the current
process)
The page directory entry points to the inner page table that is indexed by the contents of the innermost ten bits in the linear address.
Pentium Paging Architecture
One entry in the page directory is the page size flag, which if set indicates that the size of the page frame is 4 MB.
