# An Encoder is a digital circuit that perform the inverse operation of a decoder. An encoder has 2 n (or fewer) input and n output lines.

N/A
N/A
Protected

Share "An Encoder is a digital circuit that perform the inverse operation of a decoder. An encoder has 2 n (or fewer) input and n output lines."

Copied!
14
0
0

Full text

(1)

Example :Desgin Full-adder from two (74139) decoder.

1-

### Encoders

An Encoder is a digital circuit that perform the inverse operation of a decoder . An encoder has 2n (or fewer) input and n output lines.

The output lines generate the binary code corsponding to the input value. One of the most common Decoders is (4 to 2) encoder.The encoder in this system must translate the decimal input signals to binary output signals.

Inputs Outputs F0 F1 F2 F3 A B

1 0 0 0 0 0

(2)

0 0 1 0 1 0

0 0 0 1 1 1

Truth table Of (4-2) Encoder

The truth table is the origin of most logic circuit you must have al the combinations that generate a logic 1 in the truth table, therefore

A=F2 + F3 , B=F1 + F3

Block Diagram Of Encoder

Logic Diagram of Encoder

2-

### Multiplexers

A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. F 0 4 to 2 Encoder F0 F1 F2 F3 A B

(3)

The selection of a particular input line is controlled by a set of selection lines. Normally , there are 2n inputs and n selection lines whose bit combination determine which input is selected and 1 output.

### 2 – to- 1 Line multiplexer

A 2 to 1 multiplexer connects one of two sources to a common destination as shown

### in figure below:

the block diagram of 2-to-1 multiplexer can be shown fellow :

The circuit has two data input lines, one output line, and one selection line

S.

When S=0 , the upper AND gate is enabled and I0 has a path to the output. When S=1 the lower AND gate is enabled and I1 has a path to the output. The multiplexer acts like an electronic switch that selects one of two sources.

### 4 – to - 1 Line multiplexer

mux

I0 I1

(4)

S1 S2 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3

 Each of the four inputs , Io through I3 , is applied to one input of an

AND gate . selection lines S1 and S0 are decoded to select a particular AND gate.

 The outputs of the AND gates are applied to a single OR gate that provides the 1-line output.

 The function table lists the input that passed to the output for each combination of the binary selection values .

 To demonstrate the circuit operation , consider the case when s1s0=10. The AND gate associated with input I2 has two of its input equal to 1 And the third input connected to I2 has the other three AND

(5)

gates have at least one input equal to 0, which makes their outputs equal to 0.

 The OR gat output is now equal to the value of I2 , providing a path from the selected input to the output.

 A multiplexer is also called data selector, since is selects one of many inputs and steers the binary information to the output line.

 The AND gates and inverters in the multiplexer resemble a decoder circuit and indeed they decode the selection input lines.

 In general 2n-to-1 line multiplexers constructed from an 2n input lines , one to each AND gate.

 The outputs of the AND gates are applied to a single OR gate.

 The size of a multiplexer is specified by the number 2nof its data input lines and the single output line.

 The n selection lines are implied from 2ndata lines.

 As in decoders, multiplexers may have an enable input to control the operation of the unit . when the enable input is in the in active state, the outputs are disabled , and when it is in the active state , thr circuit functions as a normal multiplexer.

When (S0=0 and S1=0) the output Y will be I0

S0 Data

selection

Data inputs output Y I0

I1 I2 I3 S0

(6)

And if (S0=1 and S1=0)  y= I1 And if (S0=1 and S1=1)  y= I2 And if (S0=1 and S1=1)  y= I3 Data inputs Data Selected Output S1 S0 Y I0 0 0 1 0 0 S S II1 0 1 1 0 1 S S II2 1 0 1 0 0 S S II3 1 1 I0S1S0

Selection lines(s1) and (so) are decoded to select a particular AND gate. The outputs of the AND gates are applied to a single OR gates that provide the (1-line) output.

## MUX

Z I0 I1 I2 I3 I4 I5 I6 I7 A B C

(7)

An 8-t0-1 Mux can be used to realize any 4-variable function with no added gates. Three of variable are used as control inputs to Mux and the remaining variable is used as required on the data inputs.

Data Inputs Data Selected Output A B C I0 0 0 0 I0 I1 0 0 1 I1 I2 0 1 0 I2

(8)

I3 0 1 1 I3

I4 1 0 0 I4

I5 1 0 1 I5

I6 1 1 0 I6

I7 1 1 1 I7

Example1: using (8*1) multiplexer to realize full adder

from truth table

inputs output A B Cin (s) C0 Decimal NO. 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 2 0 1 1 0 1 3 1 0 0 1 0 4 1 0 1 0 1 5 1 1 0 0 1 6 1 1 1 1 1 7

(9)

1. first we have 23 inputs =8

2. then we have n=3 selection line to each mux 3. one output

4. full adder need 2 outputs sum and carry then we must connect two mux.

Example2: Design A<>B comparator by using Multiplexers

when A, B consist of two digits(N=2) ? hint (use 74153 Mux)

(10)

A <> B XOR Gates Decimal B0 A0 y 0 0 0 0 1 0 1 1 2 1 0 1 3 1 1 0

(11)

Example3: using multiplexer to realize the switching function F(A , B , C)=

### 

(1,4 ,5, 7) Decimal A B C Y 0 0 0 0 0 1 0 0 1 1 2 0 1 0 0 3 0 1 1 0 4 1 0 0 1

(12)

5 1 0 1 1

6 1 1 0 0

7 1 1 1 1

3-

### Demultiplexer

Is a combinational circuit that perform the inverse operation of Mux

It has one input and 2n outputs and n control lines. The uses of demux is less than

the mux circuit in electronics world .

0 1 0 0 1 1 0 1 F 8 *1 MUX A B C output Control Demultiplexer input

(13)

Example : design (1 * 4) Demux S1 S0 output 0 0 F0 0 1 F1 1 0 F2 1 1 F3 F0 F1 F2 F3 Demux 1*4 S1 S2

(14)

References

Related documents

The total coliform count from this study range between 25cfu/100ml in Joju and too numerous to count (TNTC) in Oju-Ore, Sango, Okede and Ijamido HH water samples as

Temporal analysis: 20 years return levels for the linear trend model in time for WmSh (top left); comparison of return values for the Linear Trend model to No-Trend model

between CFSR and simulated seasonal temperature using WRFfor 1997 and 1998. The 8-station mean values in winter and summer are plotted as dashed red lines in Fig. Note that Fig. The

For instance, it is well known that there is no information processing by the human brain during a saccade (movement between two fixations) [1]. In a fast-paced game like Mario

An initial eff ort was made to compare the gene and repeat content of the tomato and potato genomes, based on the available BAC-end sequences for both species (Datema et al.,

None of reference is invalid, drug information to opioids under the references from a group of the technologies we cannot show you already on our pdr.. Just some electronic access

innovation in payment systems, in particular the infrastructure used to operate payment systems, in the interests of service-users 3.. to ensure that payment systems

Community Mental Health Center (CMHC) services Community Mental Health Center (CMHC) services are paid on Cost Reimbursement (for the moment). The WS I Series is designed to

12 Data Science Master Entrepreneur- ship Data Science Master Engineering entrepreneurship society engineering. Eindhoven University of Technology

proyecto avalaría tanto la existencia de una demanda real e insatisfe- cha de este servicio por parte de la población titular de derechos como la capacidad de ambos

Therefore, the flow of information within and between domains is crucial in order to solve the problems of organizing teams, designing modular product structures and define

The person covering for the person in charge was not ensuring adequate oversight in regard to residents' health and social care needs, protection of residents from the risk of peer

[r]

� We �nish this note by reproving an earlier (unpublished) result of the author:.

The number of data pins is related to the size of the memory location.. For example, an 8-bit wide (byte-wide) memory device has 8

Asst Finance Executive Consultant-SKP Cross Consultant Head Finance CFO Director - Finance Technical Head Accounts Executive VP-Finance MD Finance Executive Manager

Last but not least, if the bridge falls outside the framework of common structural conﬁgurations mainly addressed by Eurocode 8 (e.g. as in arch bridges, or those having some

UPnP Control Point (DLNA) Device Discovery HTTP Server (DLNA, Chormecast, AirPlay Photo/Video) RTSP Server (AirPlay Audio) Streaming Server.. Figure 11: Simplified

Federal income individuals or future obligations are considered taxable income taxes add up for your income tax rates in studying the regressive of an a tax the example is a

Recently, the issue of black money and corruption has come into being with participation of our civil society and parliament institutions. In this connection,

[r]

• Combinational circuit that selects binary information from one of many input lines and directs it to one output line. 2