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IMPLEMENTATION OF HIGH PERFORMANCE CONVOLUTIONAL ENCODER WITH VITERBI
DECODER FOR LOW AREA SATELLITE COMMUNICATION RELEVANCE’S
K.Dharani
1, A.Narasimha Reddy
21Pursuing M.tech, 2Assistant Professor (ECE), Nalanda Institute of Engineering and Technology (NIET), Siddharth Nagar, Kantepudi village, Sattenepalli Mandal, Guntur Dist.,A.P. (India)
ABSTRACT
This paper presents an efficient logic Design of a secret data transmission system. This type of system presented in this project is convolutional encoder and adaptive Viterbi decoder (AVD) with a required length, K and a data transmission code rate (k/n) is ½ using field programmable gate array (FPGA) technology. Here, the specifications of Convolutional encoder and Viterbidecoder architecture are introduced and the path it can be implementable as an ASIC. The Viterbi Decoder can be implemented for faster decoding speed and less routing area with a special path management unit. In this we are adding a clock gating to the Viterbi decoder such that clock gating makes the whole Design power efficient due to discrete intervals of clock circuit will function. The whole Design is designed by using Verilog HDL and synthesis and simulated by Xilinx 13.2 ISE software.
Keywords: Clock Gating, Convolutional Encoder, Viterbi Decoder, Verilog HDL.
I. INTRODUCTION
Convolutional encoding is thought to be one of the forward error correctionplan. This coding plan is regularly utilized as a part of the field of profound space communications and that's only the recent digital communications. Versatile Viterbi decoders are utilized to decipher Convolutional codes. This method is utilized for error correction. It is extremely productive and strong. The principle point of interest of Viterbi Decoder is it has settled decoding time furthermore it suites for hardware decoding implementation. In any case, the execution requires the exponential increment in the range of area and power utilization to accomplish expanded decoding precision.
Convolution coding with Viterbi decoding is a FEC system that is especially suited to a direct in which transmitted signal is ruined fundamentally by additive white Gaussian noise (AWGN). In a large portion of constant applications like sound and video applications, the Convolutional codes are utilized for mistake adjustment. A large portion of the Viterbi decoders in the market sector are a parameterizable intelligent property (IP) canter with a productive calculation for decoding of one convolution ally-encoded arrangement just and this is for the most part utilized as a part of the field of satellite what's more, radio communications.
141 | P a g e Furthermore, the expense for the convolutional encoder what's more, Viterbi decoder is costly for a predetermined outline as a result of the patent issue. Accordingly, to understand a versatile Convolutional encoder and Viterbi decoder on a field programmable entry path cluster (FPGA) board is exceptionally requesting. Inthis paper, we worry with planning and executing a convolutional encoder and Viterbi decoder which are the fundamental bit in digital communication frameworks utilizing FPGA innovation.
Convolutional codes offer a distinct option for block codes for transmission over a boisterous channel.
Convolution coding can be connected to a constant data stream (which is impossible with block codes), and in addition squares of information. The general block diagram of this paper is appeared in the fig. 1. The message bits are created and they are sent to the crypto framework and afterward the decoded output is acquired. The sort of crypto system utilized is Convolutional Encoder and Viterbi Decoder. The Convolutional encoder encodes the message and afterward the encoded bits are produced. The bits which are encoded are again sent to the Viterbi Decoder and afterward the decoded output is acquired.
Figure.1. Block Diagram II. CLOCK GATING TECHNIQUE
Progresses in procedure innovations have empowered thick combination and higher operational frequencies in present VLSI plans, which, then again, expand the power dissipation in the chip. Decrease of power utilization gets to be one of essential subjects in VLSI plan. The dynamic exchanging of the clock organizes commonly represents 30-40% of the aggregate power dissemination of a present day VLSI outlines. Among the techniques for diminishing element power utilization in sequential circuits, clock gating strategy is a standout amongst the most productive and generally utilized strategies with a restricted punishment in range and timing. In clock gating, the clock signal is specifically exchanged off by the control signal for registers in the configuration when they don't have to change their state values. Hence the switching movement of the registers could be decreased in order to spare the power utilization of the registers and the entire circuit. Without clock gating, business EDA devices all in all actualize a Streamlining of Clock Gating Logic for Low Power LSI Design - 16 - register by utilizing a criticism circle and a multiplexer as appeared in Figure 2-1 in view of the monitored register task with a few conditions like a particular express, a particular information esteem and so forth. The accompanying is a case of such safe register element: "always @(posedge clock) if (EN) DATA_OUT_A <= DATA_IN_A;".
For this situation, register reg_A ought to reload the same value when EN is at the logicalvalue 0. Just when EN is at the logical value 1, new DATA_IN_A quality is permitted to stack at the input of reg_A by the multiplexer.
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Fig.2 Register with Clock Gating
In this path, when the same value is reloaded in reg_A through different clock cycles (when EN measures up to 0), superfluous power is devoured by reg_A. Furthermore, the multiplexer likewise expends additional power and area, particularly at the point when different registers (for packaged information) are actualized by business EDA instruments utilizing multiplexers for every register. At the point when a register keeps up Preliminaries the same state esteem through numerous clock cycles, such power scattering connected with reloading the register can be maintained a strategic distance from by applying clock gating method to switch off the check signal in these cases. Figure 2-2 demonstrates the circuit applying clock gating. CG is a clock gating cell which just output clock beats when EN is 1.
Fig.3 Latch free Clock Gating with Clock Gating
There are two regular executions of clock gating for positiveedge-activated registers: one is latch free clock gating style and the other is latch based clock gating style. For the lock free clock gating style, as appeared in Figure 2-3, clock signals to the registers are gated by a straightforward Aa AND r OR gate (contingent upon the edge on which flip-failures are activated). In the event of AND clock gating for instance, the EN signal must be steady amid the rising edge of the clock. Generally glitches on the EN signal can degenerate the clock signal to the register as appeared in Figure 2-3. Note that if EN changes just when clock is low, then such circumstance does not happen. In reality, OR gate is utilized for lock free clock gating for positive edge-activated registers, where EN is refuted. On the off chance that the calculation of EN Advancement of Clock Gating Logic for Low
143 | P a g e Power LSI Design wraps up the rising edge of clock, then the right conduct is kept without glitches. Note that the combinational postponement of EN ought to be less than half clock cycle.
Fig.4 Latch based clock gating style
Latch based clock gating style comprising of a latch and an AND gatecan likewise maintain a strategic distance from glitches as appeared in Figure 2-4. The EN signal is engendered to the data of the AND gate at the falling edge of the clock signal and after that the level-touchy lock can hold the empowersignal when clock is high. Not the same as the OR clock gating, in the lock based clock gating, the combinational bit of EN can utilize the full clock cycle.
III. IMPORTANT TERMS AND ITS DEFINITIONS
The accompanying terms are essential to the comprehension of Convolutional coding and Viterbi decoding.
1. Hard-decision/soft decision decoding: Hard-decision decoding implies that the demodulator is quantized to two levels: zero and one. On the off chance that you determine more than two quantization steps to the demodulator, then that decoder can represented as asoft decision decoding.
2. Code rate R(=k/n): Number of bits into Convolutional encoder (k)/number of bits in output which compares current input bit, as well as past (K-1)ones. It is additionally characterized as the proportion of the quantity of output bits to the quantity of information bits
3. Constraint length K: It means the "length" of the Convolutional encoder, i.e., no of k bit stages are accessible to bolster the combinatorial rationale that delivers the output data.
4. Branch Metric: Difference between the received arrangement what's more, the branch word is known as the Branch metric.
5. Pay Metric: Branch metric gathers to shape Path metric.
IV. CONVOLUTIONAL ENCODER
Convolutional coding has been utilized as a part of communication systems including profound space communications what's more, wireless communications. Convolutional codes are utilized as a different option for block codes of transmission. Convolutional encoding can be transferred to a multiple inputformation stream (which is impossible with block codes), and additionally squares of information. A convolutional encoder is a Mealy machine, where the output is an element of the present state and the presentinput information. It comprises of one or more shiftregisters(DFF) and different XOR gates. XOR gates are joined with some phase of the shift registers and in addition to the presentinput information to produce the output polynomials.
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Fig.5 Convolutional encoder with code rate 1/2
The encoder in figure 2 produces two bits of encoded data for single bit of input data, so it is known as a rate 1/2 encoder. A Convolutional encoder is by and large spoken to in (n, k, m) design with a rate of k/n, here n is represented as a number of outputs of the encoder, k is number of inputs of the encoder, m is number of flip- lemon. In this paper, we talk about decoding of convolutional codes produced by a (n,1,m) encoder with the rate 1/n with the quantity of outputs n=2. A Convolutional encoder is a Mealy machine, where the output is a component of the present current state and the current input. It comprises of one or more shift registers and numerous XOR gates. The above figure 2 demonstrates the Convolutional Encoder with rate =1/2.
Convolutional encoder can be portrayed as far as state table, state chart and trellis outline.
V. VITERBI DECODER
This part examines the distinctive parts of the Viterbi decoder. It performs fundamentally two operations, they are Synchronization and Quantization. Simple analogy signals are quantized and changed over into digital signals in the quantization square. The synchronization block recognizes the edge limits of code words and symbol limits. The Viterbi decoder gets progressive code symbols, in which the limits of the symbols and the edges have been recognized. The Viterbi decoder is fundamentally partitioned into two sorts who are talked about beneath.
A. Hard decision
Viterbi decoding-In this decoding process, the path through the trellis is resolved utilizing the Hamming distance measure. Accordingly, the most ideal path through the trellis is the path with the base Hamming distance. In this sort of decoding itshows just two conceivable outcomes, one is the decoding of signal and the other is nonappearance of sign i.e either "1" or '0'. The Hamming distance can be characterized as various bits that are diverse between the watched symbol at the decoder and the sent symbol from the encoder. Besides, the hard decision decoding applies one bit quantization on the receivedten bits.
B. Soft decision
Viterbi decoding-Soft decision Viterbi decodingis connected for the most extreme probability decoding, when the information is transmitted over the Gaussian channel. On the opposition to the hard decision decoding, Soft decision Viterbi decoding uses multi-bit quantization for the received bits, and Euclidean distance as a distance measure rather than the hamming distance.
145 | P a g e C. Internal Architecture of Viterbi Decoder-A hardware Viterbi decoder for fundamental (not punctured) code more often than not comprises of the accompanying real squares: • Branch metric unit (BMU) • Path metric unit (PMU) • Trace back unit (TBU)The block diagram of the equipment Viterbi decoder is appeared in fig. 3.
Fig.6 Hardware Implementation of Viterbi Decoder
In the above graph the encoded data is connected to the branch metric unit which gives the metrics, and these branch metrics are again given to the path metric unit which again creates the pathmetrics from which utilizing traceback method the decoded stream is receivedten.
i. Branch metric unit -
The initial unit is called branch metric unit. Here the received ten information symbols are contrasted with the perfect outputs of the encoder from the transmitter and branch metric is figured. Hamming distance or the Euclidean distance is utilized for branch metric calculation. The example usage of branch metric count unit is appeared in the fig. 4.
Fig.6 Branch Metric Unit
A branch metric unit's capacity is to compute branch metrics, which are normed separations between every conceivable symbol in the code letters in order, and the received symbol. The branch measurements are distinction qualities between received code symbol and the relating branch words from the encoder trellis.
ii. Path metric unit
The PMU figures new path metric qualities and decision qualities. Since every state can be accomplished from two states from the prior stage, there are two conceivable pathmetrics going to the present state. The center components of a PMU are ACS (Add-Compare-Select) units. The path in which they are associated between themselves is characterized by a particular code's trellis chart. The ACS unit, as appeared in fig. 5, adds for each of the two approaching branches the comparing states path metric, bringing about two new pathmetrics. The path with the better metric is picked and put a new path as the new path metric for current state, while creating a decision bit.
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Fig.7 Path Metric unit
A path metric unit calculates the branch metrics to receive the branch metrics for 2k-1the length of code is k. The result of this unit will be connected to the trace back unit.
VI. TRACE BACK UNITI
It is used to store the decisions of the ACS unit and utilize them to calculate the decoded output. We have two techniques to find out the path history these are trace back technique and register exchange method., but trace back unit takes more area compare with the register exchange method so for that it is used to implement the trellis diagram for the given convolution code. The final has less routing area and fast decoding than register exchange method.
VII. PERMUTATION NETWORK BASED PATH HISTORY (PNPH) UNIT
The PNPH unit design for a 5L stage permutation network convolutional code with 1 to 2k DE multiplexers, every demux performed by the node of trellis diagram with K register and 2K input OR gate, and the K bit register is used to store the value of the partial survivor path associated with the node and also represent the state of the survivor path.The add compare unit has calculate the new decision bit values. The below diagram represent the PNPH unit.
Fig.8 PNPH unit
147 | P a g e PROPOSED VITERBIDECODER
Viterbi decoder
Fig.9 Proposed Viterbi decoder
The Existing Viterbi decoder will have less routing area due to the PNPH unit. Still it requires more number of hardware resources; we want to reduce the power consumption and area needed by the design. The proposed version of the Viterbi decoder will require less number of hardware resources due to the sequential logic associated in the design, it needs less area. We also applying clock gating mechanism which in turns induces the less power consumption. The proposed Viterbi decoder will have better trade-off between the area, speed and power. The synthesis results are proved having good are and speed trade off
VII. RESULTS AND DISCUSSIONS
The Clock gating based convolutional encoder and Viterbi decoder will have PNPH unit implementation which make effective the design makes less area. The design will also consume less power due to the clock gating scheme to the design makes efficient power. The individual modules designed in Verilog HDL. The design is synthesised in Xilinx ISE 13.2i. The synthesis reports presented beow
RTL diagram:
BMU PMU SPU
Clock gating
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Fig.11 Area report
Fig.12 Delay report
Simulation result:149 | P a g e
IX. CONCLUSION
In this paper, we have designed the implementation of convolutional encoder and Viterbi decode with clock gating. The design synthesis and simulation has been designed by XILINX ISE 14.7i with Verilog HDL for the constraint length of k=3 and code rate ½ input sequence. The given design has been implemented with the clock gating for low power dissipation. It has less power dissipation with the existed design.
REFERENCES
[1] Anh Dinh, Ralph mason and Joe tothe,” High speedv.32 Trellis encoder & decoder implementation usingFPGA,”in IEEE transactions on communications,1999.
[2] Ming-Bo Lin, “New path history management circuits for Viterbi decoders,” in IEEE transactions oncommunications, vol 48, no.10, october 2000.
[3] A.J. Viterbi, "Error bounds for convolutional codesand an asymptotically optimum decoding algorithm,"
IEEE transactions on information theory, vol. it-13,april, 1967, pp. 260-269.
[4] Samir KumarRanpara,”On a Viterbi decoder designfor low power dissipation,” towards his master’sm thesis submitted to virginia polytechnic institute andstate university.
[5] Chip fleming,”A tutorial on Convolutional codingwith Viterbi decoding”
[6] S.Lin and D.J. Costello, Error control coding.Englewood cliffs, nj: prentice hall, 1982.
[7] Wong, Y.S. et.al “Implementation of convolutional encoderand Viterbi decoder using VHDL” IEEE Tran. on Inform. Theory, Pp. 22-25, Nov. 2009.
[8] Hema.S, Suresh Babu.V and Ramesh.P, “FPGAImplementation of Viterbi decoder” proceedings of the 6thWSEAS ICEHWOC,Feb. 2007.
[9] Irfan Habib, ÖzgünPaker, Sergei Sawitzki, “Design SpaceExploration of Hard-Decision Viterbi Decoding: Algorithmand VLSI Implementation” IEEE Tran. On Very LargeScale Integration (VLSI) Systems, Vol. 18, Pp. 794-807,May 2010.
[10] G. Davis Forney Jr., "The Viterbi algorithm," Proc. IEEE,vol. 61, pp. 268-278, March 1973.
[11] M. Kivioja, J. Isoaho and L.Vanska, "Design andimplementation of Viterbi decoder with FPGAs,"
Journal of VLSI Signal Processing Systems for Signal, Image, andVideo Technology, Kluwer Academic Publishers, vol. 21,no. 1, pp. 5-14, May 1999.
[12] M. Kling, "Channel Coding Application for CDMA2000implemented in a FPGA with a Soft Processor Core,"Linköping University, Department of ElectricalEngineering, 2005.
[13] R. W. Hamming, “Error detecting and correcting codes,”Bell Sys. Tech.J., vol. 29, pp. 147–160, 1950.
[14] V.Kavinilavu1, S. Salivahanan, V. S. KanchanaBhaaskaran2, SamiappaSakthikumaran, B. Brindha and C.Vinoth, “Implementation of Convolutional Encoder andViterbi Decoder using Verilog HDL” in IEEE tran. Oninform theory, 2011.
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AUTHOR DETAILS
K.DHARANI is pursuing M.tech from Nalanda Institute of Engineering and Technology.
She completed her B.tech from Electronics and communication Engineering. Her research of interest includes CMOS mixed, Low power VLSI and VLSI designetc.
A.NARASIMHA REDDY is working as assistant professor in Nalanda Institute of Engineering and Technology. He completed his post-graduation in VLSI and his area of interest includes VLSI systemdesign,Low power VLSI, microelectronics etc.
