ST10F252M. 16-bit MCU with 256 Kbyte Flash memory and 16 Kbyte RAM. Features

(1)

ST10F252M

16-bit MCU with 256 Kbyte Flash memory and 16 Kbyte RAM

Features

■ 16-bit CPU with DSP functions

– 50.0 ns instruction cycle time at 40 MHz (maximum) CPU clock

– Multiply/accumulate unit (MAC)16 x 16-bit multiplication, 40-bit accumulator, repeat unit

– Enhanced boolean bit manipulations – Additional instructions to support HLL and

operating systems

– Single-cycle context switching support

■ Memory organization

– 256 Kbyte on-chip IFlash memory (single voltage with program/erase controller, full performance, 32-bit fetch) – 100K erasing/programming cycles

– Up to 16 Mbytes linear address space for code and data (5 Mbyte with CAN) – 2 Kbyte on-chip internal RAM (IRAM) – 14 Kbyte extension RAM (XRAM).

■ Fast and flexible bus

– Programmable external bus characteristics for different address ranges (when 6 ADC added channels are not selected)

– 5 programmable chip-select signals – Hold-acknowledge bus arbitration support.

■ Interrupt

– 8-channel peripheral event controller for single cycle, interrupt driven data transfer – 16-priority-level interrupt system with 56

sources, sample-rate down to 25.0 ns.

■ Two multi-functional general purpose timer units with 5 timers.

■ Two 16-channel capture/compare units(18 used).

■ 16-channel A/D converter

– 10-channel 10-bit (accuracy ± 2LSB) – 6-channel (lower accuracy)

– 4.85 µs minimum conversion time.

■ 4-channel PWM unit and 4-Channel XPWM.

■ X-peripherals clock gating feature.

■ Serial channels

– Two synch./asynch. serial channels – Two high-speed synchronous channels – One I²C standard interface.

■ Fail-safe protection

– Programmable watchdog timer – Oscillator watchdog.

■ Two CAN 2.0B interfaces operating on 1 or 2 CAN buses (64 or 2x32 message, C-CAN version)

■ On-chip bootstrap loader.

■ Clock generation

– On-chip PLL with 4 to 8 MHz oscillator – Direct or pre-scaled clock input.

■ Real time clock.

■ Up to 76 general purpose I/O lines individually programmable as input, output or special function.

■ Idle, power down and stand-by modes.

■ Voltage supply for 5 V ± 10% (embedded regulator for 1.8 V core supply).

■ Temperature range: -40 to +125^oC.

LQFP100

(2)

Contents ST10F252M

1 Introduction . . . 18

1.1 Description . . . 18

2 Pin data . . . 19

3 Functional description . . . 24

4 Memory organization . . . 25

4.1 XPERCON and XPEREMU registers . . . 28

4.2 Emulation dedicated registers . . . 30

4.3 XRAM2 memory range . . . 31

5 Central processing unit . . . 35

5.1 The system configuration register SYSCON . . . 36

6 Multiplier-accumulator unit . . . 38

6.1 MAC features . . . 38

6.1.1 Enhanced addressing capabilities . . . 38

6.1.2 General . . . 38

6.1.3 Program control . . . 39

6.2 MAC operation . . . 39

6.2.1 Instruction pipelining . . . 39

6.2.2 Particular pipeline effects with the MAC unit . . . 40

6.2.3 Address generation . . . 40

6.2.4 16 x 16 signed / unsigned parallel multiplier . . . 42

6.2.5 40-bit signed arithmetic unit . . . 42

6.2.6 40-bit adder/subtracter . . . 43

6.2.7 Data limiter . . . 43

6.2.8 The accumulator shifter . . . 43

6.2.9 Repeat unit . . . 44

6.2.10 MAC interrupt . . . 44

6.2.11 Number representation and rounding . . . 45

6.3 MAC register set . . . 45

6.3.1 Address registers . . . 45

(3)

ST10F252M Contents

6.3.2 Accumulator and control registers . . . 46

7 External bus controller . . . 50

7.1 Controlling the external bus controller . . . 50

7.1.1 External bus controller registers . . . 50

7.2 EA functionality . . . 52

8 Internal Flash memory . . . 53

8.1 Overview . . . 53

8.2 Functional description . . . 53

8.2.1 Structure . . . 53

8.2.2 Modules structure . . . 54

8.2.3 Low power mode . . . 55

8.3 Write operation . . . 56

8.4 Registers description . . . 56

8.4.1 Flash control register 0 low (FCR0L) . . . 56

8.4.2 Flash control register 0 high (FCR0H) . . . 57

8.4.3 Flash control register 1 low (FCR1L) . . . 59

8.4.4 Flash control register 1 high (FCR1H) . . . 59

8.4.5 Flash data register 0 low (FDR0L) . . . 60

8.4.6 Flash data register 0 high (FDR0H) . . . 61

8.4.7 Flash data register 1 low (FDR1L) . . . 61

8.4.8 Flash data register 1 high (FDR1H) . . . 61

8.4.9 Flash address register low (FARL) . . . 62

8.4.10 Flash address register high (FARH) . . . 62

8.4.11 Flash error register (FER) . . . 62

8.5 Protection strategy . . . 63

8.5.1 Protection registers . . . 64

8.5.2 Flash non-volatile write protection I register (FNVWPIR) . . . 64

8.5.3 Flash non-volatile access protection register 0 (FNVAPR0) . . . 64

8.5.4 Flash non-volatile access protection register 1 low (FNVAPR1L) . . . 65

8.5.5 Flash non-volatile access protection register 1 high (FNVAPR1H) . . . . 65

8.5.6 XBus Flash volatile temporary access unprotection register (XFVTAUR0) . . . 65

8.5.7 Access protection . . . 66

8.5.8 Write protection . . . 67

8.5.9 Temporary unprotection . . . 67

(4)

8.6 Write operation examples . . . 67

8.7 Write operation summary . . . 71

9 Interrupt system . . . 72

9.1 Fast external interrupt . . . 72

9.1.1 External interrupt source selection register (EXISEL) . . . 72

9.1.2 External interrupt control register (EXICON) . . . 74

9.2 X-Peripheral interrupt . . . 75

9.3 Interrupt sources . . . 76

9.4 Exception and traps list . . . 78

10 Capture compare (CAPCOM) units . . . 80

11 General purpose timer unit . . . 82

11.1 GPT1 . . . 82

11.2 GPT2 . . . 83

12 PWM modules . . . 85

13 Parallel ports . . . 86

13.1 Introduction . . . 86

13.2 I/O’s special features . . . 88

13.2.1 Open drain mode . . . 88

13.2.2 Input threshold control . . . 88

13.2.3 Alternate port functions . . . 89

13.3 PORT0 . . . 90

13.3.1 Alternate functions of PORT0 . . . 91

13.3.2 Disturb protection on analog inputs . . . 93

13.4 PORT1 . . . 95

13.5 PORT2 . . . 104

13.6 PORT3 . . . 108

13.7 PORT4 . . . 112

(5)

13.8 PORT7 . . . 119

13.9 PORT5 . . . 122

13.9.2 Disturb protection on analog inputs . . . 124

14 Analog / digital converter . . . 125

14.1 Mode selection and operation . . . 127

14.1.1 Fixed channel conversion modes . . . 129

14.1.2 Auto scan conversion modes . . . 129

14.1.3 Wait for ADDAT read mode . . . 130

14.1.4 Channel injection mode . . . 131

14.1.5 ADC power down (ADOFF) . . . 133

14.2 Conversion timing control . . . 134

14.3 ADC interrupt control . . . 135

14.4 Calibration . . . 136

15 Programmable output clock divider . . . 137

15.1 Functionality . . . 137

16 Serial channels . . . 138

16.1 Asynchronous / synchronous serial interfaces . . . 138

16.2 ASCx in asynchronous mode . . . 138

16.3 ASCx in synchronous mode . . . 139

16.4 High speed synchronous serial interfaces . . . 139

17 I2C interface . . . 141

18 CAN modules . . . 142

18.1 Memory and pin mapping . . . 142

18.1.1 CAN1 mapping . . . 142

18.1.2 CAN2 mapping . . . 142

18.1.3 Register summary . . . 143

18.2 Interrupt . . . 145

18.3 Configuration support . . . 145

18.3.1 Configuration examples . . . 146

(6)

18.4 Clock prescaling . . . 148

18.5 CAN module: functional overview . . . 149

18.6 Block diagram . . . 150

18.7 Operating modes . . . 150

18.7.1 Software initialisation . . . 150

18.7.2 CAN message transfer . . . 151

18.7.3 Disabled automatic retransmission . . . 151

18.7.4 Test mode . . . 152

18.7.5 Silent mode . . . 152

18.7.6 Loop back mode . . . 152

18.7.7 Loop back combined with silent mode . . . 153

18.7.8 Basic mode . . . 153

18.7.9 Software control of pin CAN_TX . . . 154

18.8 Programmer’s model . . . 154

18.8.1 Hardware reset description . . . 156

18.8.2 CAN protocol related registers . . . 156

18.8.3 Message interface register sets . . . 161

18.8.4 IFx message buffer registers . . . 164

18.8.5 Message Handler Registers . . . 169

18.8.6 Transmission request registers . . . 170

18.8.7 New data registers . . . 171

18.8.8 Interrupt pending registers . . . 172

18.8.9 Message valid registers . . . 172

18.9 CAN application . . . 173

18.9.1 Management of message objects . . . 173

18.9.2 Message handler state machine . . . 173

18.9.3 Configuration of a transmit object . . . 176

18.9.4 Updating a transmit object . . . 176

18.9.5 Configuration of a receive object . . . 177

18.9.6 Handling of received messages . . . 177

18.9.7 Configuration of a FIFO buffer . . . 178

18.9.8 Reception of messages with FIFO buffers . . . 178

18.9.9 Handling of interrupts . . . 179

18.9.10 Configuration of bit timing . . . 180

19 Watchdog timer . . . 189

(7)

20 System reset . . . 191

20.1 Input filter . . . 191

20.2 Asynchronous reset . . . 192

20.3 Synchronous reset (warm reset) . . . 197

20.4 Software reset . . . 203

20.5 Watchdog timer reset . . . 204

20.6 Bidirectional Reset . . . 205

20.7 Reset circuitry . . . 208

20.8 Reset summary . . . 211

21 Power reduction modes . . . 214

21.1 Idle mode . . . 214

21.2 Power down mode . . . 214

21.2.1 Protected power down mode . . . 216

21.2.2 Interruptible power down mode . . . 217

21.2.3 Real time clock and power down mode . . . 219

21.3 Stand-by mode . . . 219

21.3.1 Entering stand-by mode . . . 220

21.3.2 Exiting stand-by mode . . . 221

21.3.3 Real time clock and stand-by mode . . . 221

22 Real time clock . . . 222

22.1 RTC registers . . . 223

22.1.1 RTCCON: RTC control register . . . 223

22.1.2 RTC prescaler divider loaded value registers . . . 224

22.1.3 RTC prescaler divider current value registers . . . 225

22.1.4 RTC programmable counter registers . . . 226

22.1.5 RTC alarm registers . . . 227

22.2 Programming the RTC . . . 227

23 System start-up configuration . . . 229

24 Bootstrap loader . . . 231

24.1 Selection between user-code or standard bootstrap . . . 231

24.2 Standard bootstrap loader . . . 231

24.2.1 Entering the standard bootstrap loader . . . 231

(8)

24.2.2 ST10 configuration in BSL . . . 233

24.2.3 Booting steps . . . 234

24.2.4 Hardware to activate BSL . . . 235

24.2.5 Memory configuration in bootstrap loader mode . . . 236

24.2.6 Loading the start-up code . . . 237

24.2.7 Exiting bootstrap loader mode . . . 237

24.2.8 Hardware requirements . . . 237

24.3 Standard bootstrap with UART (RS232 or K-Line) . . . 238

24.3.1 Features . . . 238

24.3.2 Entering bootstrap via UART . . . 238

24.3.3 ST10 configuration in UART BSL (RS232 or K-Line) . . . 239

24.3.4 Loading the start-up code . . . 239

24.3.5 Choosing the baud rate for the BSL via UART . . . 240

24.4 Standard bootstrap with CAN . . . 241

24.4.1 Features . . . 241

24.4.2 Entering the CAN bootstrap loader (BSL) . . . 242

24.4.3 ST10 configuration in CAN BSL . . . 242

24.4.4 Loading the startup code via CAN . . . 243

24.4.5 Choosing the baud rate for the BSL via CAN . . . 244

24.4.6 How to compute the baud rate error . . . 247

24.4.7 Bootstrap via CAN . . . 248

24.5 Comparing the old and the new bootstrap loader . . . 248

24.5.1 Software aspects . . . 248

24.5.2 Hardware aspects . . . 249

25 Identification registers . . . 251

26 Register set . . . 254

26.1 General purpose registers . . . 254

26.2 Special function register overview . . . 255

26.2.1 Registers ordered by name . . . 255

26.2.2 Registers ordered by address . . . 262

26.3 X-registers overview . . . 269

26.3.1 X-registers ordered by name . . . 269

26.3.2 X-registers ordered by address . . . 274

26.4 Flash control registers overview . . . 279

(9)

26.4.1 Registers ordered by name . . . 279

26.4.2 Registers ordered by address . . . 279

27 Electrical Characteristics . . . 281

27.1 Absolute maximum ratings . . . 281

27.2 Recommended operating conditions . . . 282

27.3 Power considerations . . . 282

27.4 Parameter interpretation . . . 283

27.5 DC characteristics . . . 283

27.6 Flash characteristics . . . 288

27.7 A/D converter characteristics . . . 289

27.7.1 Conversion timing control . . . 290

27.7.2 A/D conversion accuracy . . . 291

27.7.3 Total unadjusted error . . . 292

27.7.4 Analog reference pins . . . 293

27.8 AC characteristics . . . 299

27.8.1 Test waveforms . . . 299

27.8.2 Definition of internal timing . . . 299

27.8.3 Clock generation modes . . . 300

27.8.4 Prescaler operation . . . 301

27.8.5 Direct drive . . . 301

27.8.6 Oscillator watchdog (OWD) . . . 301

27.8.7 Phase locked loop (PLL) . . . 302

27.8.8 Voltage controlled oscillator . . . 302

27.8.9 PLL jitter . . . 303

27.8.10 PLL lock / unlock . . . 305

27.8.11 Main oscillator specifications . . . 306

27.8.12 External clock drive XTAL1 . . . 307

27.8.13 Memory cycle variables . . . 307

27.8.14 External memory bus timing . . . 308

27.8.15 Multiplexed bus . . . 308

27.8.16 Demultiplexed bus . . . 314

27.8.17 CLKOUT and READY . . . 320

27.8.18 High-speed synchronous serial interface (SSC) timing . . . 321

28 Package information . . . 325

(10)

29 Ordering Information . . . 326 30 Revision history . . . 327

(11)

ST10F252M List of tables

List of tables

Table 1. Pin description . . . 19

Table 2. IFlash addresses . . . 25

Table 3. XPERCON register functions . . . 28

Table 4. XRAM2 memory range functions . . . 31

Table 5. Definition of address areas . . . 32

Table 6. XRAM2EN of XPERCON register programming. . . 32

Table 7. System configuration register SYSCON functions . . . 36

Table 8. Example of MAC register read access . . . 40

Table 9. Pointer post-modification combinations for IDXi and Rwn . . . 41

Table 10. Parallel data move addressing . . . 41

Table 11. Limiter output using CoSTORE instruction . . . 43

Table 12. Address pointer functions . . . 46

Table 13. Offset register functions . . . 46

Table 14. MAH register functions . . . 46

Table 15. MAL register functions . . . 47

Table 16. Status word register functions . . . 47

Table 17. Control register functions . . . 48

Table 18. Repeat register functions . . . 48

Table 19. Register address in CoReg addressing mode . . . 49

Table 20. External bus controller functions. . . 51

Table 21. Address space reserved for the Flash module . . . 53

Table 22. Flash modules sectorization (read operations) . . . 54

Table 23. Flash modules sectorization (write operations or with ROMS1=’1’or Bootstrap mode) . . . 54

Table 24. Control register interface . . . 55

Table 25. Flash control register 0 low . . . 57

Table 26. Flash control register 0 high . . . 58

Table 27. Flash control register 1 low . . . 59

Table 28. Flash control register 1 high . . . 60

Table 29. Banks (BxS) and sectors (BxFy) status bits meaning. . . 60

Table 30. Flash data register 0 low. . . 60

Table 31. Flash data register 0 high . . . 61

Table 32. Flash data register 1 low. . . 61

Table 33. Flash data register 1 high . . . 61

Table 34. Flash address register low . . . 62

Table 35. Flash address register high . . . 62

Table 36. Flash error register . . . 63

Table 37. Flash non-volatile write protection I register . . . 64

Table 38. Flash non-volatile access protection register 0. . . 64

Table 39. Flash non-volatile access protection register 1 low . . . 65

Table 40. Flash non-volatile access protection register 1 high . . . 65

Table 41. XBus Flash volatile temporary access unprotection register . . . 65

Table 42. Summary of access protection level . . . 66

Table 43. Flash write operations. . . 71

Table 44. External interrupt source selection register functions . . . 73

Table 45. EXIxSS interrupts . . . 73

Table 46. CAN parallel mode pin configurations . . . 74

Table 47. External interrupt control register functions . . . 74

Table 48. X-Interrupt detailed mapping . . . 76

(12)

List of tables ST10F252M

Table 49. Interrupt sources . . . 76

Table 50. Trap priorities . . . 78

Table 51. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . 85

Table 52. Port input control register (PICON) . . . 89

Table 53. Additional port input control register (XPICON) . . . 89

Table 54. P0L and P0H registers functions . . . 91

Table 55. DP0L and DP0H registers functions . . . 91

Table 56. Disturb protection register functions . . . 94

Table 57. P1L and P1H registers functions . . . 96

Table 58. DP1L and DP1H registers functions . . . 96

Table 59. XSSCPORT register functions . . . 97

Table 60. XS1PORT register functions. . . 97

Table 61. XPWPORT register functions . . . 98

Table 62. PORT2 register functions . . . 105

Table 63. PORT2 direction register functions . . . 105

Table 64. PORT2 open drain control register functions . . . 105

Table 65. PORT2 alternate functions . . . 106

Table 69. PORT3 alternative functions . . . 110

Table 80. PORT5 digital disable register functions. . . 124

Table 81. ADCON functions . . . 127

Table 82. ADDAT and ADDAT2 registers functions . . . 128

Table 83. ADC programming . . . 135

Table 84. CLKOUTDIV functions . . . 137

Table 85. ASC asynchronous baudrates by reload value and deviation errors (fCPU = 40 MHz) . . 138

Table 86. ASC synchronous baudrates by reload value and deviation errors (fCPU = 40 MHz) . . . 139

Table 87. Synchronous baudrate and reload values (fCPU = 40 MHz) . . . 140

Table 88. CAN1 register mapping . . . 143

Table 89. CAN2 register mapping . . . 144

Table 90. XMISC register functions . . . 146

Table 91. C-CAN register summary . . . 154

Table 92. CAN control register (addresses 0x01 and 0x00) functions . . . 156

Table 93. Status register (addresses 0x03 and 0x02) functions. . . 157

Table 94. Error counter (addresses 0x05 and 0x04) functions . . . 159

Table 95. Bit timing register (addresses 0x07 and 0x06) functions . . . 159

Table 96. Test register (addresses 0x0B and 0x0A) functions . . . 160

Table 97. BRP extension register (addresses 0x0D and 0x0C) functions . . . 161

Table 98. IF1 and IF2 message interface register sets . . . 161

Table 99. IFx command request registers functions . . . 162

Table 100. IFx command mask registers functions . . . 163

(13)

ST10F252M List of tables

Table 101. IFx command mask registers functions (direction - write). . . 163

Table 102. IFx command mask registers functions (direction - read) . . . 164

Table 103. IFx Data A and Data B registers . . . 166

Table 104. Message object functions . . . 167

Table 105. Interrupt register (addresses 0x09 and 0x08) functions . . . 170

Table 106. Transmission request register functions . . . 171

Table 107. New data register functions . . . 171

Table 108. Interrupt pending register functions . . . 172

Table 109. Message valid register functions . . . 173

Table 110. Parameters of the CAN bit time . . . 181

Table 111. WDTCON register functions . . . 189

Table 112. Reset flag settings . . . 190

Table 113. Reset event definition . . . 191

Table 114. Reset events summary . . . 211

Table 115. PORT0 latched configuration for the different reset events . . . 212

Table 116. XMISC register functions . . . 215

Table 117. SYSCON PWDCFG functions . . . 216

Table 118. EXICON register functions . . . 217

Table 119. RTC control register functions . . . 224

Table 120. RTC external interrupt control register functions . . . 227

Table 121. RTC external interrupt select register functions . . . 228

Table 122. RTC/CAPCOM interrupt control requests . . . 228

Table 123. Start up configuration register functions . . . 230

Table 124. ST10F252M boot mode selection . . . 231

Table 125. Register configuration in BSL . . . 233

Table 126. Register configuration in UART BSL . . . 239

Table 127. Ranges of timer contents in function of BRP value . . . 246

Table 128. Software topics summary . . . 248

Table 129. Hardware topics summary . . . 249

Table 130. Manufacturer identifier register functions . . . 251

Table 131. Chip identifier register functions . . . 251

Table 132. Internal memory and size identifier register functions. . . 252

Table 133. Programming voltage description register functions . . . 252

Table 134. General purpose registers (GPRs) . . . 254

Table 135. General purpose registers (GPRs) bit wise addressing . . . 254

Table 136. Special function registers listed by name . . . 255

Table 137. Special function registers listed by address . . . 262

Table 138. Registers listed by name . . . 269

Table 139. Registers listed by address. . . 274

Table 140. Flash registers listed by name . . . 279

Table 141. Flash registers listed by address . . . 279

Table 142. Absolute maximum ratings . . . 281

Table 143. Recommended operating conditions . . . 282

Table 144. Thermal characteristics. . . 283

Table 145. DC characteristics. . . 283

Table 146. Flash characteristics . . . 288

Table 147. Flash data retention characteristics . . . 289

Table 148. A/D converter characteristics . . . 289

Table 149. A/D converter programming . . . 291

Table 150. On-chip clock generator selections. . . 300

Table 151. Internal PLL divider mechanism . . . 302

Table 152. PLL characteristics (V

_DD = 5V ± 10%, V_SS = 0V, T_A = -40 to +125°C) . . . 305

(14)

List of tables ST10F252M

Table 153. Main oscillator characteristics . . . 306

Table 154. Main oscillator negative resistance (module) . . . 306

Table 155. External clock drive. . . 307

Table 156. Memory cycle variables . . . 308

Table 157. Multiplexed bus timings . . . 308

Table 158. Demultiplexed bus timings . . . 314

Table 159. CLKOUT and READY timings . . . 320

Table 160. SSC master mode timings . . . 321

Table 161. SSC slave mode timings. . . 323

Table 162. Device summary . . . 326

Table 163. Document revision history . . . 327

(15)

ST10F252M List of figures

List of figures

Figure 1. Logic symbol . . . 18

Figure 2. Pin configuration (top view) . . . 19

Figure 3. Block diagram . . . 24

Figure 4. ST10F252M memory mapping (user mode: flash read operations or XADRS = F006h) . . 33

Figure 5. ST10F252M memory mapping (user mode: flash write operations or ROMS1=1) . . . 34

Figure 6. CPU block diagram (MAC unit not included) . . . 35

Figure 7. MAC unit architecture . . . 39

Figure 8. Example of parallel data move . . . 42

Figure 9. Pipeline diagram for MAC interrupt response time . . . 45

Figure 10. EA/VSTBY external circuit . . . 52

Figure 11. Flash modules structure . . . 53

Figure 12. Write operation control flow . . . 71

Figure 13. X-interrupt basic structure. . . 75

Figure 14. SFR and port pins associated with CAPCOM units . . . 81

Figure 15. SFRs and port pins associated with timer block GPT1. . . 83

Figure 16. SFRs and port pins associated with timer block GPT2. . . 84

Figure 17. Block diagram of PWM module . . . 85

Figure 18. SFRs, XBUS registers and pins associated with the parallel ports. . . 87

Figure 19. Output drivers in push/pull mode and in open drain mode . . . 88

Figure 20. Hysteresis concept . . . 89

Figure 21. PORT0 I/O and alternate functions. . . 92

Figure 22. Block diagram of a PORT0 . . . 93

Figure 23. Block diagram of input section of PORT0L pin . . . 94

Figure 24. Block diagram of a PORT0 pin . . . 95

Figure 26. Block diagram of a PORT1 pin P1H.7...P1H.4 . . . 99

Figure 27. Block diagram of pins P1H.3 ...P1H.1 . . . 100

Figure 28. Block diagram of pin P1L.6, P1.7 . . . 101

Figure 29. Block diagram of pins P1L.5 . . . 102

Figure 30. Block diagram of pins P1L.4 . . . 103

Figure 31. Block diagram of pins P1L.3...P1L.0. . . 104

Figure 35. Block diagram of PORT3 pin with alternate input or alternate output function . . . 111

Figure 36. Block diagram of pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) . . . 112

Figure 38. Block diagram of pins P4.0 ... P4.3. . . 115

Figure 39. Block diagram of pin P4.4 . . . 116

Figure 44. Block diagram of PORT7 pins P7.3...P7.0 . . . 122

Figure 47. SFRs, XBUS registers and port pins associated with the A/D converter . . . 126

Figure 48. Analog to digital converter block diagram . . . 126

(16)

List of figures ST10F252M

Figure 49. Auto scan conversion mode example . . . 130

Figure 50. Wait for read mode example. . . 131

Figure 51. Channel injection example . . . 131

Figure 52. Channel injection example with wait for read . . . 133

Figure 53. Connection to single CAN bus via separate CAN transceivers . . . 147

Figure 54. Connection to single CAN bus via one common transceiver . . . 147

Figure 55. Connection to two different CAN buses (for example, for gateway application) . . . 148

Figure 56. Connection to one CAN bus with internal parallel mode enabled. . . 148

Figure 57. Block diagram of the C-CAN. . . 150

Figure 58. CAN core in silent mode . . . 152

Figure 59. CAN core in loop back mode . . . 153

Figure 60. CAN core in loop back combined with silent mode. . . 153

Figure 61. Structure of a message object in the message memory. . . 167

Figure 62. Data transfer between IFx registers and message RAM . . . 174

Figure 63. Initialisation of a transmit object . . . 176

Figure 64. Initialization of a receive object . . . 177

Figure 65. CPU Handling of a FIFO Buffer . . . 179

Figure 66. Bit timing . . . 181

Figure 67. The propagation time segment . . . 182

Figure 68. Synchronisation on “late” and “early” edges . . . 184

Figure 69. Filtering of short dominant spikes . . . 185

Figure 70. Structure of the CAN Core’s CAN Protocol Controller . . . 186

Figure 71. Asynchronous power-on RESET (EA=1) . . . 194

Figure 72. Asynchronous power-on RESET (EA=0) . . . 195

Figure 73. Asynchronous hardware RESET (EA=1) . . . 196

Figure 74. Asynchronous hardware RESET (EA=0) . . . 197

Figure 75. Synchronous short / long hardware RESET (EA=1). . . 200

Figure 76. Synchronous short / long hardware RESET (EA=0). . . 201

Figure 77. Synchronous long hardware RESET (EA=1) . . . 202

Figure 78. Synchronous long hardware RESET (EA=0) . . . 203

Figure 79. SW / WDT unidirectional RESET (EA=1) . . . 204

Figure 80. SW / WDT unidirectional RESET (EA=0) . . . 205

Figure 81. SW / WDT bidirectional RESET (EA=1) . . . 207

Figure 84. Minimum external reset circuitry . . . 209

Figure 85. System reset circuit . . . 210

Figure 86. Internal (simplified) reset circuitry . . . 210

Figure 87. EXICON register . . . 217

Figure 88. RPD pin: external circuit to exit power down . . . 218

Figure 89. Simplified power down exit circuitry . . . 218

Figure 90. Power down exit sequence using an external interrupt (PLL x 2). . . 219

Figure 91. SFRs associated with the RTC . . . 223

Figure 92. RTC block diagram . . . 223

Figure 93. RTC prescaler register function . . . 225

Figure 94. RTC prescaler divider register functions. . . 226

Figure 95. PORT0 configuration during Reset . . . 229

Figure 96. ST10F252M new bootstrap loader program flow . . . 233

Figure 97. Booting steps for ST10F252M . . . 235

Figure 98. Hardware provisions to activate BSL . . . 235

Figure 99. Memory configuration in bootstrap loader mode . . . 236

Figure 100. UART bootstrap loader sequence . . . 238

(17)

ST10F252M List of figures

Figure 101. Baudrate deviation between host and ST10F252M . . . 240

Figure 102. CAN bootstrap loader sequence. . . 241

Figure 103. Register configuration in CAN BSL. . . 243

Figure 104. Bit rate measurement over a predefined zero-frame . . . 244

Figure 105. Reset Boot Sequence . . . 250

Figure 106. Internal memory and size identifier register . . . 252

Figure 107. Port2 test mode structure . . . 286

Figure 108. Supply current versus the operating frequency (RUN and IDLE modes) . . . 287

Figure 109. A/D conversion characteristics . . . 293

Figure 110. A/D converter input pins scheme . . . 294

Figure 111. Charge sharing timing diagram during sampling phase . . . 295

Figure 112. Anti-aliasing filter and conversion rate . . . 296

Figure 113. Input / output waveforms . . . 299

Figure 114. Float waveforms . . . 299

Figure 115. Generation mechanisms for the CPU clock . . . 300

Figure 116. ST10F252M PLL jitter . . . 305

Figure 117. Crystal oscillator and resonator connection diagram . . . 306

Figure 118. External clock drive XTAL1. . . 307

Figure 119. External memory cycle: multiplexed bus, with/without read/write delay, normal ALE. . . . 310

Figure 120. External memory cycle: multiplexed bus, with/without read/write delay, extended ALE. . 311

Figure 121. External memory cycle: multiplexed bus, with/without r/w delay, normal ALE, r/w CS. . . 312

Figure 122. External memory cycle: multiplexed bus, with/without r/w delay, extended ALE, r/w CS . 313 Figure 123. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE . . . 316

Figure 124. External memory cycle: demultiplexed bus, with/without r/w delay, extended ALE . . . 317

Figure 125. External memory cycle: demultiplexed bus, with/without r/w delay, normal ALE, r/w CS. 318 Figure 126. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 319

Figure 127. CLKOUT and READY . . . 321

Figure 128. SSC master timing . . . 322

Figure 129. SSC slave timing . . . 324

Figure 130. LQFP100 mechanical data and package dimensions . . . 325

(18)

Introduction ST10F252M

1 Introduction

1.1 Description

The ST10F252M is a new derivative of the STMicroelectronics ST10 family of 16-bit single- chip CMOS microcontrollers.

The ST10F252M combines high CPU performance (up to 24 million instructions per second) with high peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.

The ST10F252M is processed in 0.18 µm CMOSM8 technology. The MCU core and the logic is supplied with a 5 V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work at 5 V.

The ST10F252M is an optimized version of ST10F252E device, upward compatible with the following set of differences.

● The AC and DC parameters are modified due to a difference in the maximum CPU frequency. Refer to Section 27.5 and Section 27.8 for detailed description.

● XASC, XSSC, XPWM and I²C have been changed. Refer to Chapter 13.

● No external bus is available when all 16 ADC channels are selected.

● Pin T3EUD is added for encoder interface as alternate function of P1H.0.

● A/D Converter has 16 channels, 10 are on standard Port5, 6 channels on Port0.

● XPERCON register bit mapping modified according to new peripherals implementation.

● External bus NO ARBITRATION and READY, hold and ready pins not available

● On-chip low power oscillator, 32 KHz, is no longer available.

Figure 1. Logic symbol

XTAL1

RSTIN XTAL2

RSTOUT

NMI EA / V_STBY

RPD ALE RD WR / WRL

Port 5 10-bit Port 4 (high) 4-bit Port 3 12-bit Port 2 14-bit Port 1 16-bit Port 0 16-bit V_DD V_SS

Port 7 or Port 4 (low) 4-bit

V_AREF V_AGND

ST10F252M

V₁₈

(19)

ST10F252M Pin data

2 Pin data

Figure 2. Pin configuration (top view)

1 2 3

5 6 4

7 8 9 10

45 11

46 47 48 49 50 86 85 84 83 82 81 80 79 78 77 76

70 69 68

66 65 67 75 74 73

71 72

TQFP100 40 41 42 43 44

97 96 95 94 93 92 91 90 89 88 87 100 99 98

34 35 36 37 38 39 29 30 31 32 33

26 27 28 12 13 14

16 17 15

18 19 20 21 22

59 58 57

55 54 56 64 63 62

60 61

23 24 25

52 51 53 RSTIN

RSTOUT NMI P2.2 / CC2IO P2.3 / CC3IO P2.4 / CC4IO P2.5 / CC5IO P2.6 / CC6IO P2.7 / CC7IO P2.8 / CC8IO / EX0IN P2.9 / CC9IO / EX1IN VDD VSS V18 P2.10 / CC10IO / EX2IN P2.11 / CC11IO / EX3IN P2.12 / CC12IO / EX4IN P2.13 / CC13IO / EX5IN P2.14 / CC14IO / EX6IN P2.15 / CC15IO / EX7IN / T7IN P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4

VAREF VAGND P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9 P3.0 / T0IN P3.1 / T6OUT P3.2 / CAPIN P3.6 / T3IN VSS VDD P3.7 / T2IN P3.8 / MRST0 P3.9 / MTSR0 P3.10 / TxD0 P3.11 / RxD0 P3.12 / BHE/ WRH P3.13 / SCLK0 P3.15 / CLKOUT P4.0 / A16 / P7.0 / POUT0 P4.1 / A17 / P7.1 / POUT1 P4.2 / A18 / P7.2 / POUT2 P4.3 / A19 / P7.3 / POUT3

P0H.4 / AD12 / AN15 P0H.3 / AD11 / AN14 P0H.2 / AD10 / AN13 P0H.1 / AD9 / AN12 P0H.0 / AD8 / AN11 P0L.7 / AD7 / AN10 P0L.6 / AD6 P0L.5 / AD5 P0L.4 / AD4 P0L.3 / AD3 P0L.2 / AD2 P0L.1 / AD1 P0L.0 / AD0 V18 VSS VDD EA / Vstby ALE WR / WRLN RD RPD

P4.7 / A23 / CAN2_TxD P4.6 / A22 / CAN1_TxD / CAN2_TxD P4.5 / A21 / CAN1_RxD / CAN2_RxD P4.4 / A20 / CAN2_RxD VSS XTAL1 XTAL2 VDD P1H.7 / A15 / CC27I P1H.6 / A14 / CC26I P1H.5 / A13 / CC25I P1H.4 / A12 / CC24I P1H.3 / A11 / SCLK1 P1H.2 / A10 / MTSR1 P1H.1 / A9 / MRST1 P1H.0 / A8 /T3EUD VSS VDD P1L.7 / A7 / SDA P1L.6 / A6 / SCL P1L.5 / A5 / RXD1 P1L.4 / A4 / TXD1 P1L.3 / A3 / XPOUT3 P1L.2 / A2 / XPOUT2 P1L.1 / A1 / XPOUT1 P1L.0 / A0 / XPOUT0 P0H.7 / AD15 P0H.6 / AD14 P0H.5 / AD13

ST10F252M

Table 1. Pin description

Symbol Pin Type Function

RSTIN 1 I

Reset Input with Schmitt-trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F252M. An internal pull-up resistor permits power-on reset using only a capacitor connected to V_SS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence.

RSTOUT 2 O

Internal reset indication output. This pin is set to a low level when the device is executing either a hardware, a software or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed.

NMI 3 I

Non-maskable interrupt input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power-down) instruction is executed, the NMI pin must be low in order to force the ST10F252M to go into power-down mode. If NMI is high and PWDCFG

=’0’, when PWRDN is executed, the part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

(20)

Pin data ST10F252M

P2.2 - P2.15

4-11 15-20 I/O

PORT2 is a 14-bit bidirectional I/O port. It is bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT2 outputs can be configured as push/pull or open drain drivers. The input threshold of PORT2 is selectable (TTL or CMOS).

The following PORT2 pins have alternate functions:

4 I/O P2.2 CC2IO CAPCOM1: CC2 capture input / compare output

... ... ... ... ...

9 I/O P2.7 CC7IO CAPCOM1: CC7 capture input / compare output

10 I/O

P2.8

CC8IO CAPCOM1: CC8 capture input / compare output I EX0IN Fast external interrupt 0 input

11 I/O

P2.9

CC9IO CAPCOM1: CC9 capture-in/compare-out I EX1IN Fast external interrupt 1input

15 I/O

P2.10

CC10IO CAPCOM1: CC10 capture-in/compare-out I EX2IN Fast external interrupt 2 input

... ... ... ... ...

20 I/O

P2.15

CC15IO CAPCOM1: CC15 capture-in/compare-out I EX7IN Fast external interrupt 7 input

I T7IN CAPCOM2 timer T7 count input

P5.0–P5.9

21-25 I PORT5 is a 10-bit input-only port with Schmitt-trigger characteristics. The pins of PORT5 can be the analog input channels (up to 10) for the A/D converter where P5.x equivals ANx (analog input channel x).

28-32 I

P3.0–P3.2, P3.6 P3.7-P3.13

P3.15

33-35 36, 39-45

46 I/O I/O I/O

PORT3 is a 12-bit (P3.3:5, P3.14 are missing) bidirectional I/O port, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT3 outputs can be configured as push/pull or open drain drivers. The input threshold of PORT3 is selectable (TTL or CMOS).

33 I P3.0 T0IN CAPCOM:1 timer T0 count input 34 O P3.1 T6OUT GPT2: timer T6 toggle latch output 35 I P3.2 CAPIN GPT2: register CAPREL capture input 36 I P3.6 T3IN GPT1: timer T3 count / gate input

39 I P3.7 T2IN GPT1: timer T2 input for count / gate / reload / capture 40 I/O P3.8 MRST0 SSC0 master-receiver / slave-transmitter I/O

41 I/O P3.9 MTSR0 SSC0 master-transmitter / slave-receiver O/I

42 O P3.10 TxD0 ASC0: clock / data output (asynchronous / synchronous) 43 I/O P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous)

44 O

P3.12

BHE External memory high byte enable signal O WRH External memory high byte write strobe Table 1. Pin description (continued)

(21)

P3.0–P3.2, P3.6 P3.7-P3.13

P3.15

45 I/O P3.13 SCLK0 SSC0: master clock output / slave clock input

46 O P3.15 CLKOUT System clock output (programmable divider on CPU clock)

P7.0–P7.3

47-50 I/O

PORT7 is a 4-bit bidirectional I/O port, bitwise programmable for input or output via direction bit (this port is connected to pins 47-50 only if bit P7EN of XMISC register is set.). Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT7 outputs can be configured as push/pull or open drain drivers. The input threshold of PORT7 is selectable (TTL or CMOS).

The following PORT7 pins have alternate functions: (only if bit P7EN of XMISC register is set)

47 O P7.0 POUT0 PWM0: channel 0 output ... ... ... ... PWM0: channel 1 output 50 O P7.3 POUT3 PWM0: channel 3 output

P4.0–P4.7

47-54 I/O

PORT4 is an 8-bit bidirectional I/O port. P4.0-P4.3 are connected to pins 47-50 only if P7EN of XMISC is not set (default after reset).

It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state.

In case of an external bus configuration, PORT4 can be used to output the segment address lines (A16...A19 output only if bit P7EN of XMISC register is not set):

47 O P4.0 A16 Segment address line 48 O P4.1 A17 Segment address line 49 O P4.2 A18 Segment address line 50 O P4.3 A19 Segment address line

51 O

P4.4

A20 Segment address line I CAN2_RxD CAN2: receive data input

52 O

P4.5

A21 Segment address line I CAN1_RxD CAN1: receive data input I CAN2_RxD CAN2: receive data input

53 O

P4.6

A22 Segment address line O CAN1_TxD CAN1 transmit data output O CAN2_TxD CAN2 transmit data output

54 O

P4.7

A23 Segment address line O CAN2_TxD CAN2 transmit data output

RPD 55 - Timing pin for the return from interruptible power-down and synchronous / asynchronous reset selection.

RD 56 O External memory read strobe. RD is activated for every external instruction or data read access.

Table 1. Pin description (continued)

(22)

Pin data ST10F252M

WR/WRL 57 O

External memory write strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in SYSCON register for mode selection.

ALE 58 O Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command pf the address lines.

EA / V_STBY 59 I

External access enable pin.

A low level applied to this pin during and after Reset forces the ST10F252M to start the program from the external memory space. A high level forces ST10F252M to start in the internal memory space. This pin is also used (when Stand-by mode is entered, that is ST10F252M under reset and main VDD turned off) to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8V supply for the RTC module (when not disabled) and to retain data inside the Stand-by portion of the XRAM (16 Kbyte).

It can range from 4.5 to 5.5V. In running mode, this pin can be tied low during reset RTC and XRAM activities, since the presence of a stable VDD guarantees the proper biasing of all those modules.

P0L.0-P0L.7, P0H.0-P0H.7

63-70 71-78 I/O

PORT0 is a two 8-bit bidirectional I/O ports P0L and P0H, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of PORT0 is selectable (TTL or CMOS).

In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes

Multiplexed bus modes

The pins of P0L / P0H also serve as the additional (up to six) analog input channels for the A/D converter, where P0L.7 equals to AN10 and P0H.x equals ANy (Analog input channel y, where y = x + 11). This additional function has a higher priority on demultiplexed bus function.

P1L.0-P1L.7, P1H.0-P1H.7

79-86 89-96 I/O

PORT1 is a two 8-bit bidirectional I/O ports P1L and P1H, bitwise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes: If at least BUSCONx is configured such that the demultiplexed mode is selected, the pins of PORT1 are not available for general purpose I/O function. The input threshold of PORT1 is selectable (TTL or CMOS).

79 O P1L.0 XPOUT XPWM: channel 0 output Table 1. Pin description (continued)

Data path width 8-bit 16-bit P0L.0 – P0L.7: D0 – D7 D0 - D7

P0H.0 – P0H.7: I/O D8 - D15

Data path width 8-bit 16-bit P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7 P0H.0 – P0H.7: A8 – A15 AD8 - AD15

(23)

P1L.0-P1L.7, P1H.0-P1H.7

80 O P1L.1 XPOUT XPWM: channel 1 output 81 O P1L.2 XPOUT XPWM: channel 2 output 82 O P1L.3 XPOUT XPWM: channel 3 output

83 O P1L.4 TxD1 ASC1: data input (asynchronous / synchronous) 84 I/O P1L.5 RxD1 ASC1: data input (asynchronous) or I/O (synchronous) 85 I/O P1L.6 SCL I²C interface serial clock

86 I/O P1L.7 SDA I²C interface serial data

89

I/O P1H.0 General purpose input

I P3.4 T3EUD GPT3: external up / down

90 I/O P1H.1 MRST1 SSC1: master-receiver / slave-transmitter I/O 91 I/O P1H.2 MTSR1 SSC1: master-transmitter / slave-receiver O/I 92 I/O P1H.3 SCLK1 SSC1: master clock output / slave clock input 93 I P1H.4 CC24I CAPCOM2: CC24 capture input

94 I P1H.5 CC25I CAPCOM2: CC25 capture input 95 I P1H.6 CC26I CAPCOM2: CC26 capture input 96 I P1H.7 CC27I CAPCOM2: CC27 capture input XTAL2 98 O XTAL2 Output of the oscillator amplifier circuit.

To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC characteristics must be observed.

XTAL1 99 I XTAL1 Main oscillator amplifier circuit and/or external clock input.

V_AREF 26 - A/D converter reference voltage and analog supply.

V_AGND 27 - A/D converter reference and analog ground.

V₁₈ 14, 62 O

1.8 V decoupling pin.

A decoupling capacitor (typical value of 10 nF, max. 100 nF) must be connected between this pin and nearest V_SSpin.

V_DD

12, 38, 60, 87,

97 -

Digital supply voltage = +5 V during normal operation, idle mode and power-down modes.

It can be turned off when Stand-by RAM mode is selected.

V_SS

13, 37, 61, 88,

100

- Digital ground.

Table 1. Pin description (continued)

(24)

Functional description ST10F252M

3 Functional description

The architecture of the ST10F252M combines advantages of both RISC and CISC

processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F252M.

Figure 3. Block diagram

External Bus Controller 10-bit ADC GPT1 / GPT2 ASC0

BRG BRG

SSC0 PWM CAPCOM2 CAPCOM1

Port 0Port 1Port 4

Port 5

CPU-Core and MAC Unit

XCAN2 XSSC XASC

XCAN1 XI2C XRAM1

2K XRAM2

12K (STBY)

(PEC)

IFlash 256K

32

16 16

16

PEC

Interrupt Controller

Port 3 Port 7

16

Watchdog IRAM

2K 16

XRTC

Oscillator

PLL

5V-1.8V Voltage Regulator

Port 2

16

8

10 12 4

14 16

XPWM 16

(25)

ST10F252M Memory organization

4 Memory organization

The memory space of the ST10F252M is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed bytewise or wordwise.

Particular portions of the on-chip memory have additionally been made directly bit addressable.

IFlash: 256 Kbytes of on-chip Flash memory. It is divided in eight blocks (B0F0...B0F7) that constitute the Bank 0. When bootstrap mode is selected, the Test-Flash Block B0TF (4 Kbytes) appears at address 00’0000h: refer to Chapter 8: Internal Flash memory for more details on memory mapping in boot mode. The summary of address range for IFlash is the following Table 2:

Note: When bit ROMEN in SYSCON register is set, the address 05’0000h - 07’FFFFh is considered as reserved (no external memory access is enabled). Trying to read in this address area outputs dummy data (software trap 009Bh).

IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0 to R15) and/or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group. Base address is 00’F600h, upper address is 00’FDFFh.

XRAM: 14Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code.

The XRAM is divided into two areas, the first 2 Kbytes named XRAM1 and the second 12 Kbyte named XRAM2, connected to the internal XBUS and are accessed like an external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (50 ns access at 40 MHz CPU clock). Byte and Word accesses are possible.

The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register), and XRAM1EN (bit 2 of XPERCON register) are set. If bit XRAM1EN or XPEN is cleared, then any access in the address range 00’E000h - 00’E7FFh will be directed to external Table 2. IFlash addresses

Blocks User Mode Size

B0TF Not visible 4K

B0F0 00’0000h - 00’1FFFh 8K

B0F1 00’2000h - 00’3FFFh 8K

B0F2 00’4000h - 00’5FFFh 8K

B0F3 00’6000h - 00’7FFFh 8K

B0F4 01’8000h - 01’FFFFh 32K

B0F5 02’0000h - 02’FFFFh 64K

B0F6 03’0000h - 03’FFFFh 64K

B0F7 04’0000h - 04’FFFFh 64K

Reserved area 05’0000h - 07’FFFFh 192K

Flash Regs 08’0000h - 08’FFFFh 64K

(26)

Memory organization ST10F252M

memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register.

The XRAM2 address range is the one selected programming XADDR3 register, if XPEN (bit 2 in SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register.

After reset, the XRAM2 address range is 09’0000h-09’3FFFh and is mirrored every 16 Kbyte boundary until 0F’FFFFh.

XRAM2 also represents the Stand-by RAM, which can be maintained biased through EA/V_STBY pin when the main supply V_DD is turned off.

As the XRAM appears like external memory, it cannot be used as system stack or as register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable.

SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function register areas. SFRs are Wordwide registers which are used to control and to monitor the function of the different on-chip units.

CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 module access. The CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit 0 of the XPERCON register. Accesses to the CAN1 module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 100 ns at 40 MHz CPU clock. No tristate waitstate is used.

CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 module access. The CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit 1 of the XPERCON register. Accesses to the CAN2 module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used.

Note: If one or the two CAN modules are used, Port 4 cannot be programmed to output all eight segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line).

XRTC: Address range 00’ED00h - 00’EDFFh is reserved for the XRTC module access. The XRTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON register. Accesses to the XRTC module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used.

XPWM: Address range 00’EC00h - 00’ECFFh is reserved for the XPWM module access.

The XPWM is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the XPERCON register. Accesses to the XPWM module use demultiplexed addresses and a 16- bit data bus (only word accesses are possible). Two waitstates give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used. Only word access is allowed.

XASC: Address range 00’E900h - 00’E9FFh is reserved for the XASC module access. The XASC is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON register. Accesses to the XASC module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used.

(27)

ST10F252M Memory organization

XSSC: Address range 00’E800h - 00’E8FFh is reserved for the XSSC module access. The XSSC is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON register. Accesses to the XSSC module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used.

XI²C: Address range 00’EA00h - 00’EAFFh is reserved for the XI²C module access. The XI²C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register. Accesses to the XI²C module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used.

X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON register and bit10 of the XPERCON register. Accesses to these additional features use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 100.0 ns at 40 MHz CPU clock. No tristate waitstate is used. The following set of features are provided:

● CLKOUT programmable divider

● XBUS interrupt management registers

● CAN2 multiplexing on P4.5/P4.6

● CAN1-2 main clock prescaler

● main voltage regulator disable for power-down mode

● TTL / CMOS threshold selection for Port0, Port1, and Port5

● Flash temporary unprotection

● Port4/Port7 selection for pins 47-50

In order to keep the needs of designs where more memory is required than is provided on the chip, up to 16 Mbytes of external memory can be connected to the microcontroller.

Note: When P7EN bit is set in XMISC register, the Port7 low nibble is available on the pins 47 to 50 and Port4 low is not available. Therefore the relative address lines are not available and the external memory space is reduced to 64 Kbytes."

Visibility of XBUS peripherals

In order to keep the ST10F252M compatible with ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the global enabling with XPEN bit in SYSCON register, the corresponding address space, port pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and not available. Refer to Chapter 26: Register set on page 254

XPERCON and XPEREMU clock gating

As already mentioned, the XPERCON register has to be programmed to enable the single X-BUS modules separately. The XPERCON is a read/write ESFR register.

The new feature of clock gating has been implemented by mean of this register. Once the EINIT instruction has been executed, all the peripherals (except RAMs and XMISC), not enabled in the XPERCON register are not be clocked. The clock gating can reduce power consumption and improve EMI when the user doesn’t use all the X-Peripherals

Note: When the clock has been gated in the disabled Peripherals, no Reset will be raised once the EINIT instruction has been executed.

(28)

Memory organization ST10F252M

4.1 XPERCON and XPEREMU registers

Once the XPEN bit of the SYSCON register is set and at least one of the X-peripherals (except memories) is activated, the register XPEREMU must be written with the same content of XPERCON: this is mandatory to allow correct emulation of the features on the X-BUS for the new ST10 generation.

XPEREMU must be programmed after XPERCON and after SYSCON so that the final configuration for X-peripherals is stored in XPEREMU and used for the emulation hardware setup.

XPERCON

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved

XMISC XI2CEN XSSCEN XASCEN XPWM reserved XRTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN

- - - - - RW RW RW RW RW - RW RW RW RW RW

Table 3. XPERCON register functions

Bit Name Function

15:11 Reserved

10 XMISCEN

XBUS additional features enable bit

‘0’: Access to the additional miscellaneous features is disabled. The address range 00’EB00h-00’EBFFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XSSCEN, XPWMEN and XI2CEN are ‘0’ also.

‘1’: The Additional Features are enabled and can be accessed.

9 XI2CEN

XI²C enable bit

‘0’: Accesses to the on-chip XI²C are disabled, external access is performed. The address range 00’EA00h-00’EAFFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XSSCEN, XPWMEN and XMISCEN are ‘0’ also.

‘1’: The on-chip XI²C is enabled and can be accessed.

8 XSSCEN

XSSC enable bit

‘0’: Accesses to the on-chip XSSC are disabled, external access is performed. The address range 00’E800h-00’E8FFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also.

‘1’: The on-chip XSSC is enabled and can be accessed.

7 XASCEN

XASC enable bit

‘0’: Accesses to the on-chip XASC are disabled, external access is performed. The address range 00’E900h-00’E9FFh is directed to external memory only if CAN1EN, CAN2EN, XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also.

‘1’: The on-chip XASC is enabled and can be accessed.