IR Drop using Voltage Strom.pdf

Comprehensive SoC Power Grid verification using

VoltageStorm

Agenda

•

Introduction

•

Static and Dynamic IR drop analysis using

VoltageStorm

•

SoC Hierarchical Analysis Methodology

Results and Observations

•

Conclusions

Q&A

Introduction

• Low power supply voltage causing IR drop problems in SoC

designs

• Increasing demand to handle analog blocks in SoC

– Have their own dedicated supplies

– Must account for block boundary voltages

– IR drop/ground bounce from top-level power routing

– Some analog blocks share digital power supplies

• Integration with VoltageStorm

– Base SoC power integrity product – Hierarchical, cell-based approach

Static and Dynamic IR drop

analysis using VoltageStorm

•

VoltageStorm supports both static and dynamic

Static IR drop analysis using

VoltageStorm

•Static IR drop analysis verifies robustness of power rail by

showing static IR drop, open circuits, missing vias and high current densities

•Static IR drop analysis is based upon average power

calculated by powermeter

•Average power calculation is based upon three methods

–

Full-chip VCD

–

Accura based switching probability propagation

method

Dynamic IR drop analysis using

VoltageStorm

• Dynamic IR drop analysis is used for analyzing the effect of

transient IR drop

• Helps in optimizing number of decoupling capacitors to reduce

leakage in 90nm and sub-90nm designs

• Based upon instance based dynamic current consumption

calculated by powermeter

• Powermeter uses two methods to calculate dynamic current

consumption

– Vector-based

– Uses gate or transistor level simulation to generate dynamic

power/current waveform

– Most accurate solution if “right” vectors are provided by user

– Vectorless

– Uses timing window information to generate dynamic power/current

waveform

SoC Hierarchical Analysis

Methodology

• VoltageStorm uses power grid views for enabling hierarchical

solution

• A power grid is used to model power rail and power

distribution information of each instance in design.

• For SoC design, different type of power grids will include – standard cell views

– digital blocks

– IP/Memory blocks

Types of Power Grid Views

• VoltageStorm uses four types of

power grid views for hierarchical static analysis

– Detailed – Reduced – Abstract – Port

• For hierarchical dynamic

analysis, three additional types of power grid views are used

– Detailed Dynamic – Reduced Dynamic – Port

Static Power Grid Views

Detailed Reduced Abstract Port

Dynamic Power Grid Views

Power Grid Views for Standard

Cells

• For standard cells port views are sufficient. However for dynamic

analysis detailed views are created for CRC modeling of standard cell.

• CRC modeling

– R on

– Device C

– Load C (Pin capacitance)

out device Ron x out VDD Cell x Loading C from SPEF/DSPF

Power Grid Views for

Memory/Hard IP

• For Memory and hard IP, detailed views

are created for verifying that these blocks do not suffer from IR drop within the

instance

• Two methods are used

– Libgen detailed view creation.

– Most common method

– Transistor level VoltageStorm Flow

– Used for detailed dynamic PGV creation – Device recognition and spice netlist

generation

– RC extraction

– Spice-like simulation on spice netlist for

current tap generation

– Analysis on power grid

– Generate detailed/reduced power grid view

from analysis results

VST LibGen Vectors LEF GDS Detailed Dynamic PGV

Power Grid Views for Digital

Blocks

•For creating power grid views of digital blocks, static or

dynamic IR drop analysis is run at block level first. Here are the steps

– Calculate instance based average static/dynamic current. – Run R or RC extraction on block level power grid.

– Merge the static or dynamic current with the extracted

power grid.

– Run static/dynamic analysis.

Power Grid Views for Analog/

Mixed-Signal Blocks (VAVO)

•Analog VoltageStorm (VAVO) accurately characterize power

consumption and power distribution inside analog and mixed signal blocks

– Power integrity verification

– IR drop (power and ground rails) – Power rail Electromigration

– Integrated with Virtuoso ADE environment – Flow supported by existing Cadence products

– Assura LVS – Assura RCX

VAVO FLOW DIAGRAM

Schematic Layout

Assura LVS

Assura RCX (RC extraction) Create simulation netlist

from config view including Assura extracted cellview

Testbench schematic

Assura extracted cellview

Create Simulation files

Run Spectre or UltraSim

Simulation Details in VAVO

automatically added to extracted netlist V V V V V V V V V V V V V V V V V V V V V V

VoltageStorm

Comprehensive SoC Power Grid Verification

Small Digital Design

Mixed-Signal & Analog Design

Power Grid Views

(static & dynamic)

VoltageStorm PE (activity propagation, static, cell-based) VoltageStorm VST (dynamic, transistor) UltraSim

VoltageStorm PE

CeltIC NDC Large Digital Design Large Digital Design Virtuoso Platform Encounter Platform

Results and Observations

•

The power grid views generated by VAVO for the

analog block are more accurate because of the

following reasons:

–

Device recognition is more accurate because Assura

LVS is used to extract analog devices.

–

RCX is more accurate in extracting parasitics for

non-manhattan geometry.

–

Tap current in VAVO is calculated from actual

Spice-like simulation.

Conclusions

•

Here are conclusions from this methodology

VoltageStorm can analyze and characterize all

types of blocks such as digital blocks, memories,

hard IPs and analog/mixed signal blocks accurately

at SoC level.

–

The hierarchical flow of VoltageStorm gives it

infinite capacity since designer can create as many

power grid views as required and feed them into

top level run.