Low Power Design in VLSI

(1)

Low Power Design in VLSI

(2)

(3)

Evolution in Power Dissipation:

(4)

Why worry about power?

H

ea

t

D

is

si

pa

ti

on

DEC 21164 DEC 21164

sou

source :rce : arparpa-ea-estosto

microprocessor power dissipation

(5)

Computers Defined by Watts not MIPS:

MegaWatt MegaWatt Data Centers Data Centers Wireless Wireless Internet Internet Internet Internet PDAs, Cameras, PDAs, Cameras, Cellphones, Cellphones, Laptops, GPS, Laptops, GPS, Set-tops, Set-tops, 0.1-10 Watt Clients 0.1-10 Watt Clients Base Stations Base Stations Routers Routers Wi

Wirerelelessss Sensor Networks Sensor Networks

Wa Watttt

(6)

Why Low Power ?

•• Growth of battery-powered systemsGrowth of battery-powered systems •• Users need for:Users need for:

– – MobilityMobility – – PortabilityPortability – – ReliabilityReliability •• CostCost

(7)

IC Design Space:

(8)

Power Impacts on System Design:

•

• Energy consumed per task determines battery lifeEnergy consumed per task determines battery life

–

– Second order effect is that higher current draws decreaseSecond order effect is that higher current draws decrease effective battery energy capacity

effective battery energy capacity

•

• Current draw causes IR drops in power supply voltageCurrent draw causes IR drops in power supply voltage

–

– Requires more power/ground pins to reduce resistance RRequires more power/ground pins to reduce resistance R

–

– Requires thick&wide on-chip metal wires or dedicatedRequires thick&wide on-chip metal wires or dedicated metal layers

metal layers

•

• Switching current (dI/dT) causes inductive power supplySwitching current (dI/dT) causes inductive power supply

voltage bounce

voltage bounce LdI/dTLdI/dT

–

– Requires more pins/shorter pins to reduce inductance LRequires more pins/shorter pins to reduce inductance L

–

– Requires on-chip/on-package decoupling capacitance toRequires on-chip/on-package decoupling capacitance to help bypass pins during switching transients

help bypass pins during switching transients

•

• Power dissipated as heat, higher temps reduce speed andPower dissipated as heat, higher temps reduce speed and

reliability

–

(9)

Moore´s Law

--

doubling transistors every 18 months doubling transistors every 18 months

••

PoPowerwer is pis proproportortionional tal too die areadie area andand frequencyfrequency!!

•• In the samIn the same techne technology a nology a new archew architectitecture has 2ure has 2-3X in Die-3X in Die Area

Area

•• ChanChanging tging technechnology ology implimplies 2X ies 2X frequfrequencyency

SCALING TECHNOLOGY ... SCALING TECHNOLOGY ...

•• DecrDecreasineasing g voltavoltage ge ( ( 0.7 0.7 scalscaling ing factofactor r )) •• DecreDecreasing asing of of die die area area ( ( 0.5 0.5 scalscaling ing factofactor r )) •• IncreIncreasinasing g C C per per unit unit area area 43% 43% !!!!!!

Facts ...

(10)

This

This implimplies thaies that the powt the power denser density incrity increase of 40ease of 40%% every generation !!!

every generation !!!

Temperature is a function of power density and

Temperature is a function of power density and determinates the type of determinates the type of cooling system needed.

cooling system needed.

VARIABLES VARIABLES

•• PPEEAAK K PPOOWWEER R ( ( wwoorrsst t ccaasse e ))

Today´s packages can sustain a power dissipation over 100W

Today´s packages can sustain a power dissipation over 100W for upfor up to

to 100msec 100msec >>>>>> cheaper package if peaks are reduced cheaper package if peaks are reduced

•• EENNEERRGGY SY SPPEENNT ( T ( ffoor a r a wwoorrkkllooaad )d ) More correlated to battery life

(11)

Low Power Strategies:

•• OS OS llevevel el :: PARTITIONING, POWER DOWNPARTITIONING, POWER DOWN

•• SoSoftftwaware lre levevel :el : REGULARITY, LOCALITY, CONCURRENCYREGULARITY, LOCALITY, CONCURRENCY

(( CompiCompiler tler technolechnology ogy for for low low powerpower, in, instructstruction ion scheduschedulingling ))

•• ArcArchithitectecture ure levlevel :el : PIPELINING, REDUNDANCY, DATA ENCODINGPIPELINING, REDUNDANCY, DATA ENCODING (( ISA, arISA, architecchitectural destural design, memign, memory hieraory hierarchy, HW rchy, HW extensions, etc )

extensions, etc )

•• CirCircuicuit/lt/logiogic lec level vel :: LOGIC STYLES, TRANSISTOR SIZING, ENERGYLOGIC STYLES, TRANSISTOR SIZING, ENERGY RECOVERY

RECOVERY

( Logic families, conditional clocking, adiabatic circuits, ( Logic families, conditional clocking, adiabatic circuits,

asy

asynchnchronronousous desdesign ign ))

(12)

Power Consumption Estimation:

0 0 5 5 10 10 15 15 20 20 25 25 30 30 A

Arrcch h RRTTL L CCiirrccuuiit t LLaayyoouutt Levels of abstraction Levels of abstraction E E r r r r o o r r e e s s t t i i m m a a t t i i o o n n

power consumption power consumption

(13)

Due to the relative high error rate in

Due to the relative high error rate in the architecturalthe architectural estimation

estimation ( no vision of the ( no vision of the total area, circuit types,total area, circuit types, technology, block activity, etc )

technology, block activity, etc )

IMPOR

IMPORTANTTANT DESIGDESIGN DECN DECISIONISIONS MUSS MUST BE T BE DONEDONE AT

AT AARCRCHHITITECECTUTURARALL LLEVEVELEL!!

•• AcAccucurarate pte powower eer evavaluluatatioion is n is dodone ane at lt latate dee desisign pgn phahasesess •• NeNeededs os of gf gooood fd feeeedbdbacack bk betetweween en alall tl the he dedesisign gn phphasaseses

-- Correlation between power estimation from low level to high Correlation between power estimation from low level to high level

(14)

TRY TO IMPROVE ACCURACY AT HIGH

TRY TO IMPROVE ACCURACY AT HIGH LEVELLEVELLEVELLEVEL

--

Critical path based power consumption analysis

(

CIRCUIT TYPES, TECHNOLOGY, ACTIVITY FACTOR )CIRCUIT TYPES, TECHNOLOGY, ACTIVITY FACTOR )

--

Thermal images based correlation analysis

(

HOTTEST SPOTS LOCATION, COOLEST SPOTS HOTTEST SPOTS LOCATION, COOLEST SPOTS LOCATION,

LOCATION, TEMPERATURE TEMPERATURE DIFFERENCES, DIFFERENCES, TEMPERATURE TEMPERATURE DISTRIBUTION )

(15)

Architectural Power Evaluation:

Arc

Archithitececturturalal dedesigsign n parpartitititionon

•• PoPowewer cr cononsusumpmptition on evevalaluauatition on at at blblocock lk levevelel

-- Power Power densidensity ty of of blocblocks ks ( ( SPICE SPICE simulsimulationation, , statistatisticastical l inputinput set,set, technology and circuit types definition ) technology and circuit types definition )

-- Activity of blocks and sub-blocks Activity of blocks and sub-blocks ( ( running benchmarks )running benchmarks )

-- AreaArea ( ( feefeedbadback ck frofrom m VLSVLSI I desdesignign, , circircuicuits ts and and tectechnohnologlogy y defined )

defined )

•• TrTry do y do dedefinfine sce scalalining fag factctorors ths that aat allollow to rw to rememap tap thehe

architectural power simulator when technology, area and architectural power simulator when technology, area and circuit types change

circuit types change

(16)

Power Dissipation in CMOS:

Primary Components: Primary Components:

•

• Capacitor Charging (85-90% of active power)Capacitor Charging (85-90% of active power)

–

– Energy is ½ CVEnergy is ½ CV22_{per transition}_{per transition}

•

• Short-Circuit Current (10-15% of active power)Short-Circuit Current (10-15% of active power)

–

– When both p and n transistors turn on during signalWhen both p and n transistors turn on during signal transition

transition

•

• Subthreshold Leakage (dominates when inactive)Subthreshold Leakage (dominates when inactive)

–

– Transistors don’t turn off completelyTransistors don’t turn off completely

•

• Diode Leakage (negligible)Diode Leakage (negligible)

–

– Parasitic source and drain diodes leak to substrateParasitic source and drain diodes leak to substrate

C C_L_L

Diode Leakage Current Diode Leakage Current Subthreshold Leakage Current Subthreshold Leakage Current Short-Circuit Short-Circuit Current Current Capacitor Capacitor Charging Charging Current Current

(17)

Sources of Power Dissipation:

•• Dy

Dyna

nam

mic

ic po

powe

wer

r di

diss

ssip

ipat

atio

ions

ns::

whenever the logicwhenever the logic level changes at different points in the circuit because of the change in level changes at different points in the circuit because of the change in the input signals the dynamic power dissipation occurs.

the input signals the dynamic power dissipation occurs.

–

– SwiSwitchtching ing popower wer disdissipsipatiation.on. –

– ShShortort-ci-circurcuit poit power dwer dississipaipatiotion.n.

•• S

Sta

tattic

ic p

pow

owe

er d

r dis

issi

sipa

pati

tion

ons:

s:

this is a type of dissipation,this is a type of dissipation, which does not have any effect of level change in the input and output which does not have any effect of level change in the input and output..

–

(18)

Switching Power Dissipation:

•• Ca

Caus

used

ed by

by th

the c

e cha

harg

rgin

ing a

g and

nd di

disch

schar

argi

ging

ng of

of th

the

e

node capacitance.

Figure 1: Switching power Figure 1: Switching power dissipation [1].

(19)

Switching Power Dissipation (Contd.):

•

• P

P

_s/w_s/w

= 0.5 *

αα

* C

L

* V

dddd22

*

f

clkclk

–

– CC_L_L phyphysicsical capaal capacitcitancance,e, VV_dd_ddsupply voltage,supply voltage, αα switching activity,switching activity,

f

f _clk_clkclock frequency.clock frequency.

–

– CC_L_L(i) =(i) = ΣΣ j

j CCININ j j + C+ Cwirewire ++ CCpar(i)par(i) –

– CC_IN_IN the the gate gate input input capaccapacitancitance,e, CC_wire_wire the parasitic interconnectthe parasitic interconnect a

anndd CC_par_pardiffusion capacitances of each gate[I].diffusion capacitances of each gate[I].

•• DDeeppeenndds s oonn::

–

– SSuupppplly vy voollttaaggee –

– PhPhysysicical al CaCapapacicitatancncee –

(20)

Short circuit power dissipation:

•• CaCausused bed by siy simumultaltaneneouous cos condnducuctition oon of n af n and p nd p blblococksks..

Figure 2: Short circuit current Figure 2: Short circuit current

(21)

Short circuit power dissipation

(contd.)

::

w

wheherere k = k = (k(k_n_n == kk_p_p), the trans conductance of the transistor,), the trans conductance of the transistor, τ

τ _{= (t}_{= (t}

rise

rise == ttfallfall), the input/output transition time, V), the input/output transition time, VDDDD = supply voltage,= supply voltage,

ff = clo= clock freck frequequencyncy, and V, and V_T_T = (V= (V_Tn_Tn = |V= |V_Tp_Tp|), the threshold voltage of |), the threshold voltage of MOSFET.

MOSFET.

•• DDeeppeenndds s oon n ::

–

– ThThe e iinnppuut t rraammpp –

– LLooaadd –

– ThThe tre tranansisiststor or sisize ze of tof the he gagatete –

– SSuupppplly vy voollttaaggee –

– FFrreeqquueennccyy –

(22)

Leakage power dissipation:

•• Si

Six

x sh

shor

ort-

t-cha

chann

nnel

el le

leaka

akage

ge me

mech

chan

anis

isms

ms ar

are

e

there:

–

– II₁₁ Reverse-bias p-n junction leakageReverse-bias p-n junction leakage –

– II₂₂ Sub threshold leakageSub threshold leakage –

– II₃₃ Oxide tunneling currentOxide tunneling current –

– II₄₄ Gate current due to hot-carrier injectionGate current due to hot-carrier injection –

– II₅₅ GIDL (Gate Induced Drain Leakage)GIDL (Gate Induced Drain Leakage) –

– II₆₆ Channel punch through currentChannel punch through current

(23)

Leakage power dissipation (contd.)

Figure 3: Summary of leakage current mechanism [2] Figure 3: Summary of leakage current mechanism [2]

(24)

PN Junction reverse bias current:

•• Th

The r

e rev

ever

erse

se bi

bias

asin

ing o

g of p-

f p-n j

n jun

unct

ctio

ion c

n cau

ause

se

reverse bias current

–

– CauseCaused by dd by diffusiffusion/dion/drift of rift of minominority carity carrier nrrier near thear thee edge of the depletion region.

edge of the depletion region.

where

where V V _bias_bias = the reverse bias voltage across = the reverse bias voltage across the p-n junction,the p-n junction, J J _s_s = the= the reverse saturation current density and A = the

(25)

Sub Threshold Leakage Current:

•• Ca

Caus

used

ed wh

when

en th

the g

e gat

ate v

e vol

olta

tage

ge is

is be

belo

low V

w V

_th._th.

Fig 4: Sub threshold current[2]

Fig 4: Sub threshold current[2] Fig 5: Fig 5: SubthSubthresholresholdd leakagleakage in a e in a negatnegative- ive- c

chhaannnneell mmeettaall––ooxxiiddee––sseemmiiccoonndduuccttoor r (NMOS) transistor.[2]

(26)

Contribution of Different Power

Dissipation:

Fig 6: Contribution of different powers[1] Fig 6: Contribution of different powers[1]

Fig 7:Static power increases with Fig 7:Static power increases with shrinking device geometries [7]. shrinking device geometries [7].

(27)

Degrees of Freedom

•• Th

The t

e thr

hree

ee de

degr

gree

ees o

s of f

f fre

reed

edom

om ar

are:

e:

–

– Su

Supp

pply V

ly Vol

olta

tage

ge

–

– Sw

Swit

itch

chin

ing Act

g Activ

ivit

ity

y

–

(28)

Reducing Power:

•

• Switching powerSwitching power activity*½ CVactivity*½ CV22_*frequency_*frequency

–

– (Ignoring short-circuit and leakage currents)(Ignoring short-circuit and leakage currents)

•

• Reduce activityReduce activity

–

– Clock and function gatingClock and function gating

–

– Reduce spurious logic glitchesReduce spurious logic glitches

•

• Reduce switched capacitance CReduce switched capacitance C

–

– Different logic styles (logic, pass transistor, dynamic)Different logic styles (logic, pass transistor, dynamic)

–

– Careful transistor sizingCareful transistor sizing

–

– Tighter layoutTighter layout

–

– Segmented structuresSegmented structures

•

• Reduce supply voltage VReduce supply voltage V

–

– QuadrQuadratic savatic savings in eneings in energy per tranrgy per transitiosition –n – BIG effecBIG effectt

–

– But circuit delay is reducedBut circuit delay is reduced

•

• Reduce frequencyReduce frequency

–

– Doesn’t save energy just reduces rate at which it isDoesn’t save energy just reduces rate at which it is consumed

consumed

–

– Some saving in battery life from reduction in currentSome saving in battery life from reduction in current draw

(29)

Supply Voltage Scaling

•• Sw

Swit

itch

chin

ing a

g and

nd sh

shor

ort c

t cir

ircu

cuit

it po

powe

wer a

r are

re

proportional to the square of the supply

voltage.

•• Bu

But th

t the d

e del

elay i

ay is p

s pro

ropo

port

rtio

iona

nal t

l to th

o the su

e supp

pply

ly

voltage. So, the decrease in supply voltage will

results in slower system.

•• Th

Thre

resh

shol

old vo

d volt

ltag

age ca

e can b

n be sc

e scal

aled d

ed dow

own to

n to ge

gett

the same performance, but it may increase the

concern about the leakage current and noise

margin.

(30)

Supply Voltage Scaling (contd.)

Fig 8: Scaling supply and threshold Fig 8: Scaling supply and threshold voltages [4]

voltages [4] _{Fig 9: Scaling of threshold voltage on}_{Fig 9: Scaling of threshold voltage on} leakage power and delay[4]

(31)

Switching Activity Reduction

•• T

Tw

wo

o c

co

om

mp

po

on

ne

en

ntts

s::

–

– f: Tf: The he averaverage age perioperiodicitdicity oy of daf data ata arrivarrivalsls –

– αα_{: how many transitions each arrival will generate.}_{: how many transitions each arrival will generate.}

•• Th

Ther

ere wi

e will

ll be

be no

no ne

net be

t bene

nefi

fits b

ts by Re

y Redu

duci

cing

ng f.

f.

••

αα

_{can be reduced by algorithmic optimization, by}

architecture optimization, by proper choice of

logic topology and by logic-level optimization.

(32)

Physical capacitance reduction

•• Ph

Physi

ysica

cal c

l cap

apac

acita

itanc

nce i

e in a c

n a cir

ircu

cuit c

it con

onsi

sists

sts of t

of thr

hree

ee

components:

–

– ThThe oe oututpuput nt nodode ce capapacacititanance ce ((C C _L_L).). –

– ThThe ie inpnput ut cacapapacicitatancnce (e (C C _in_in) of the driven gates.) of the driven gates. –

– The The tottotal al intintercerconnonnect ect capcapaciacitantance ce ((C C _int_int).).

•• Sm

Smal

alle

ler t

r the

he si

size

ze of

of a d

a dev

evic

ice,

e, sm

smal

alle

ler i

r is

s

C

_L._L.

•• Th

The

e ga

gate

te ar

area

ea of

of ea

each

ch tr

tran

ansis

sisto

tor d

r det

eter

ermi

mine

nes

s

C

_in._in.

••

C

_int_int

is determine by width and thickness of the

metal/oxide layers with which the interconnect

line is made of, and capacitances between layers

around the interconnect lines.

(33)

Issues

•• T

Te

ec

ch

hn

no

ollo

og

gy S

y Sc

ca

alliin

ng

g

–

– Cap

Capaci

acitan

tance pe

ce per nod

r node red

e reduces

uces by 30

by 30%

%

–

– El

Elec

ectr

tric

ical

al no

node

des

s in

incr

crea

ease

se by

by 2X

2X

–

– Di

Die s

e siz

ize g

e gro

rows

ws by

by 14

14% (

% (Mo

Moor

ore’

e’s

s La

Law)

w)

–

– Sup

Supply

ply vol

voltag

tage r

e redu

educes

ces by

by 15%

15%

–

– And

And freq

frequen

uency in

cy incre

crease

ases by 2

s by 2X

X

This will increase the active power by 2.7X

(34)

Issues (contd.)

•• To

To m

mee

eet f

t fre

requ

quen

ency

cy de

dem

ma

and

nd V

V

_tt

will be

scaled, resulting high leakage power.

*Source: Intel *Source: Intel Fig 10:

(35)

Ultra Low Power System Design:

•• Po

Powe

wer mi

r mini

nim

miz

izat

atio

ion ap

n appr

proa

oach

ches

es::

•• Run

Run at m

at mini

inimum

mum all

allowa

owable

ble vol

voltag

tage

e

(36)

Process

•• P

Pro

rogr

gre

ess

ss in

in S

SOI

OI an

and b

d bul

ulk s

k sililic

icon

on

–

– (a) 0(a) 0.5V o.5V operaperation tion of ICof ICs usis using Sng SOI teOI technochnologylogy –

– (b) 0(b) 0.9V o.9V operaperation otion of bulk f bulk silicosilicon memn memory, loory, logic, agic, andnd processors

processors

•• In

Incr

crea

easi

sing

ng de

dens

nsit

itie

ies a

s and

nd clo

clock f

ck fre

requ

quen

enci

cies

es ha

have

ve

pushed the power up even with reduce power

supply

(37)

Choice of Logic Style

(38)

Choice of Logic Style

•• PoPowewer-r-dedelalay pry prododucuct imt imprprovoves aes as vos voltltagage dee decrcreaeasesess

(39)

--Power Consumption is Data

Power Consumption is Data

Dependent

•• E

Exa

xam

mpl

ple :

e : St

Sta

ati

tic 2

c 2 In

Inpu

put N

t NO

OR G

R Gat

ate

e

Assume : Assume : P(A=1) = ½ P(A=1) = ½ P(B=1) = ½ P(B=1) = ½ Then : Then : P(Out=1) = ¼ P(Out=1) = ¼ P(0 P(0→→1)1) = = P(Out=0).P(OuP(Out=0).P(Out=1)t=1) =3/4 * 1/4 = 3/16 =3/4 * 1/4 = 3/16 C C_EFF_EFF = 3/16 * C= 3/16 * C_L_L

(40)

Transition Probability of 2-input

NOR Gate

as a function of input probabilities as a function of input probabilities

(41)

Switching Activity (

(42)

G

(43)

At the Datapath Level…

Reusable Reusable Irregular

(44)

Balancing Operations

(45)

Carry Ripple

(46)

Data Representation

(47)

Low Power Design Consideration

(cont’)

(Binary v.s. Gray

(48)

Resource Sharing Can Increase

Activity

(Separate Bus Structure) (Separate Bus Structure)

(49)

Resource Sharing Can Increase

Activity (cont’d)

(50)

Operating at the Lowest Possible

Voltage

•• De

Desir

sire

e to

to op

oper

erate

ate at

at lo

lowe

west

st po

possi

ssibl

ble s

e spe

peed

eds

s

(using low supply voltages)

•• Us

Use A

e Arc

rchi

hite

tectu

cture

re op

opti

timi

miza

zati

tion t

on to co

o comp

mpen

ensa

sate f

te for

or

slower operation

Approach : Trade-off

AREA

for lower

POWER

(51)

Reducing V

_dd

(52)

Lowering V

_dd

Increases Delay

(53)

Architecture Trade-offs : Reference

Data Path

(54)

(55)

Parallel Data Path

(56)

Paralelna implementacija dela

datapath :

(57)

Pipelined Data Path

(58)

Proto

(59)

Paralelno-proto

(60)

A Simple Data Path : Summary

(61)

Computational Complexity of DCT

Algorithms

(62)

Power Down Techniques

•• Concept of DynamicConcept of Dynamic

Frequency Scaling (DFS) Frequency Scaling (DFS)

(63)

Energy-efficient Software

Coding

•• Po

Pote

tent

ntia

ial fo

l for po

r powe

wer re

r redu

duct

ctio

ion vi

n via so

a soft

ftwa

ware

re

modification is relatively unexploited.

•• Co

Code

de si

size a

ze and

nd al

algo

gori

rith

thmi

mic ef

c effi

fici

cien

ency c

cy can

an

significantly affect energy dissipation

•• Pi

Pip

pel

elin

inin

ing a

g at so

t soft

ftwa

ware

re le

leve

vel-

l- V

VLI

LIW c

W cod

odin

ing s

g sty

tyle

le

•• E

Ex

xa

am

mp

plle

es

s

(64)

--Po

Powe

wer Hu

r Hung

nger –

er – Cl

Cloc

ock N

k Net

etwo

work

rk

(Always Ticking)

•• H-H-TrTree ee –– dedesisign gn dedefificicienencicies es babasesed od on En Elmlmorore de delelayay model

model

•• PLPLL –L – eveverery dy desesigignener (r (didigigitatal ol or ar ananalolog) g) shshouould ld hahaveve the knowledge of PLL

the knowledge of PLL

•• MuMultiltiplple fre freqequeuencncieies in cs in chihipsps/s/sysystetems –ms – by Pby PLLLL •• LoLow mw maiain fn frereququenencycy, B, Butut

•• Jitter Jitter and and NoiseNoise, Ga, Gain ain and nd BandBandwidthwidth, P, Pull-inull-in and Lock Time, Stability …

and Lock Time, Stability … •• LLooccaal l ttiimme e zzoonnee

•• SSeellff--TTiimmeedd

(65)

Power Analysis in the Design

Flow

(66)

Human Wearable Computing

-Power

Power

•• We

Wear

ara

abl

ble

e co

comp

mput

utin

ing

g –

– em

emb

bed

eddi

ding

ng co

comp

mput

ute

er

r

into clothing or creating a form

into clothing or creating a form that can be used

that can be used

like clothing

•• Cu

Curr

rren

ent co

t comp

mput

utin

ing is

g is lilimi

mite

ted by

d by ba

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output current, and electrical outlet for

recharging

(67)

Conclusions

•• High-speed design is a requirement for many applicationsHigh-speed design is a requirement for many applications

•• Low-power design is also a requirement for IC designers.Low-power design is also a requirement for IC designers.

•• A new way of THINKING to simultaneously achieve both!!!A new way of THINKING to simultaneously achieve both!!!

•• Low power impacts in the cost, size, weight, performance, andLow power impacts in the cost, size, weight, performance, and reliability.

reliability.

•• Variable VVariable V_dd_dd anand Vd Vtt is is a ta trerendnd

•• CAD tools high level power estimation and managementCAD tools high level power estimation and management

•• Don’t juDon’t just work on Vst work on VLSI, paLSI, pay attenty attention to MEMion to MEMS –S – lot oflot of problems and potential is great.