Qsys 11 0 Lab Manual

Lab Exercises

Lab Exercises

Lab Exercise Introduction

Lab Exercise Introduction

 These lab ex

 These lab exercises help yo" b

ercises help yo" become *amiliar with t

ecome *amiliar with the Altera

he Altera

 _{Qsys system integration}

 _{Qsys system integration}

tool by completing the

tool by completing the *ollowing ob+ecti#es

*ollowing ob+ecti#es

•

• /"il! a !esign with Qsys/"il! a !esign with Qsys •

• Create c"stom &, *or the Qsys libraryCreate c"stom &, *or the Qsys library •

• Design a Qsys system Design a Qsys system with hierarchywith hierarchy •

• $im"late the Qsys system with /"s "nctional o!els /s3$im"late the Qsys system with /"s "nctional o!els /s3 •

• Deb"g an! test the Qsys system with $ystem ConsoleDeb"g an! test the Qsys system with $ystem Console

 The exer

 The exercises incl"!e the *ollo

cises incl"!e the *ollowing labs

wing labs

•

• Lab 1 Explore an existing Qsys !esignLab 1 Explore an existing Qsys !esign •

• Lab 2 igrate a !esign *rom $4,C Lab 2 igrate a !esign *rom $4,C /"il!er to Qsys/"il!er to Qsys •

• Lab 5 &mport a new componentLab 5 &mport a new component •

• Lab 6 Design a Qsys systemLab 6 Design a Qsys system •

• Lab 7 ,er*orm sim"lation *or a system optional3Lab 7 ,er*orm sim"lation *or a system optional3 •

• Lab 8 'se hierarchy to assemble the 9nal Qsys systemLab 8 'se hierarchy to assemble the 9nal Qsys system •

• Lab : 'se $ystem Console to Lab : 'se $ystem Console to !eb"g the system optional3!eb"g the system optional3

Lab Prerequisites

Lab Prerequisites

 The labs are b"n!l

 The labs are b"n!le! with s"pporting pr

e! with s"pporting pro+ect 9les *or each la

o+ect 9les *or each lab in the

b in the lab_qsys.zip

lab_qsys.zip archi#e.

 archi#e.

 The incl"!e! pro

 The incl"!e! pro+ect 9les ens"re that yo" !o

+ect 9les ens"re that yo" !o not ha#e to s"pply all c

not ha#e to s"pply all constraints or top%le#el

onstraints or top%le#el

co!e. ;

co!e. ;o" sho"l! start

o" sho"l! start each lab by opening

each lab by opening the pro+ect 9le *rom the

the pro+ect 9le *rom the appropriatel

appropriately

y

n"mbere! lab !irectory

n"mbere! lab !irectory. The

. The *"lly complete! !esign an!

*"lly complete! !esign an! programming 9les are also

programming 9les are also

pro#i!e!.

pro#i!e!.

 These labs re<"ir

 These labs re<"ire the *ollowing so*

e the *ollowing so*tware an! op

tware an! optional har!war

tional har!ware.

e.

Table 1: Required Softare and !ptional "ardare

Table 1: Required Softare and !ptional "ardare

R

Reeqquuiirreed d SSooffttaarree !p!pttiioonnaal l ""aarrddaarree •

• Q"art"s- && so*twareQ"art"s- && so*tware #ersion 11.0

#ersion 11.0 •

• o!el$im- Alterao!el$im- Altera E!ition #ersion 11.0 E!ition #ersion 11.0 • • lab_qsys.ziplab_qsys.zip !esigns !esigns •

• =ios=ios-- && Embe!!e! E#al"ation >it && Embe!!e! E#al"ation >it =EE>3

=EE>3 •

Lab Exercise Introduction

Lab Exercise Introduction

 These lab ex

 These lab exercises help yo" b

ercises help yo" become *amiliar with t

ecome *amiliar with the Altera

he Altera

 _{Qsys system integration}

 _{Qsys system integration}

tool by completing the

tool by completing the *ollowing ob+ecti#es

*ollowing ob+ecti#es

•

• /"il! a !esign with Qsys/"il! a !esign with Qsys •

• Create c"stom &, *or the Qsys libraryCreate c"stom &, *or the Qsys library •

• Design a Qsys system Design a Qsys system with hierarchywith hierarchy •

• $im"late the Qsys system with /"s "nctional o!els /s3$im"late the Qsys system with /"s "nctional o!els /s3 •

• Deb"g an! test the Qsys system with $ystem ConsoleDeb"g an! test the Qsys system with $ystem Console

 The exer

 The exercises incl"!e the *ollo

cises incl"!e the *ollowing labs

wing labs

•

• Lab 1 Explore an existing Qsys !esignLab 1 Explore an existing Qsys !esign •

• Lab 2 igrate a !esign *rom $4,C Lab 2 igrate a !esign *rom $4,C /"il!er to Qsys/"il!er to Qsys •

• Lab 5 &mport a new componentLab 5 &mport a new component •

• Lab 6 Design a Qsys systemLab 6 Design a Qsys system •

• Lab 7 ,er*orm sim"lation *or a system optional3Lab 7 ,er*orm sim"lation *or a system optional3 •

• Lab 8 'se hierarchy to assemble the 9nal Qsys systemLab 8 'se hierarchy to assemble the 9nal Qsys system •

• Lab : 'se $ystem Console to Lab : 'se $ystem Console to !eb"g the system optional3!eb"g the system optional3

Lab Prerequisites

Lab Prerequisites

 The labs are b"n!l

 The labs are b"n!le! with s"pporting pr

e! with s"pporting pro+ect 9les *or each la

o+ect 9les *or each lab in the

b in the lab_qsys.zip

lab_qsys.zip archi#e.

 archi#e.

 The incl"!e! pro

 The incl"!e! pro+ect 9les ens"re that yo" !o

+ect 9les ens"re that yo" !o not ha#e to s"pply all c

not ha#e to s"pply all constraints or top%le#el

onstraints or top%le#el

co!e. ;

co!e. ;o" sho"l! start

o" sho"l! start each lab by opening

each lab by opening the pro+ect 9le *rom the

the pro+ect 9le *rom the appropriatel

appropriately

y

n"mbere! lab !irectory

n"mbere! lab !irectory. The

. The *"lly complete! !esign an!

*"lly complete! !esign an! programming 9les are also

programming 9les are also

pro#i!e!.

pro#i!e!.

 These labs re<"ir

 These labs re<"ire the *ollowing so*

e the *ollowing so*tware an! op

tware an! optional har!war

tional har!ware.

e.

Table 1: Required Softare and !ptional "ardare

Table 1: Required Softare and !ptional "ardare

R

Reeqquuiirreed d SSooffttaarree !p!pttiioonnaal l ""aarrddaarree •

• Q"art"s- && so*twareQ"art"s- && so*tware #ersion 11.0

#ersion 11.0 •

• o!el$im- Alterao!el$im- Altera E!ition #ersion 11.0 E!ition #ersion 11.0 • • lab_qsys.ziplab_qsys.zip !esigns !esigns •

• =ios=ios-- && Embe!!e! E#al"ation >it && Embe!!e! E#al"ation >it =EE>3

=EE>3 •

#esi$n !%er%ie

#esi$n !%er%ie

 The lab ex

 The lab exercise "ses the !esig

ercise "ses the !esign ill"strate! in 

n ill"strate! in ig"re 1 to teach yo

ig"re 1 to teach yo" abo"t !esigning wit

" abo"t !esigning with

h

the Qsys system integration tool.

the Qsys system integration tool.

&i$ure 1: Top'Le%el #esi$n (loc) #ia$ra*

&i$ure 1: Top'Le%el #esi$n (loc) #ia$ra*

&n these labs yo"

&n these labs yo" !esign a system to analy?e the

!esign a system to analy?e the *re<"ency spectr"m o* an inp"t a"!io

*re<"ency spectr"m o* an inp"t a"!io

signal) generate a pict"re o* the *re<"ency spectr"m accor!ing to the res"lts) an! !isplay

signal) generate a pict"re o* the *re<"ency spectr"m accor!ing to the res"lts) an! !isplay

it on an

it on an LCD screen. All o*

LCD screen. All o* the !ata paths

the !ata paths "se A#alon- $treaming A

"se A#alon- $treaming A#alon%$T3 inter*aces.

#alon%$T3 inter*aces.

All the control signals "

All the control signals "se A#alon emory%appe! A

se A#alon emory%appe! A#alon%3 inter*aces. The !esign

#alon%3 inter*aces. The !esign

incl"!es the *ollowing ma+or components.

incl"!es the *ollowing ma+or components.

+udio ,ontroller

+udio ,ontroller

 The

 The

 bloc *ormats the !ata into A#alon%$T !ata. The a"!io signal comes in on the

 bloc *ormats the !ata into A#alon%$T !ata. The a"!io signal comes in on the

line%in port on the boar!. There is an

line%in port on the boar!. There is an a"!io ADC chip on the boar! which con#erts the

a"!io ADC chip on the boar! which con#erts the

a"!io signal to !igital !ata be*ore the signal enters the ,@A. The A"!io ADC chip on

a"!io signal to !igital !ata be*ore the signal enters the ,@A. The A"!io ADC chip on the

the

boar! can be con9g"re! thro"gh the &

boar! can be con9g"re! thro"gh the &

_{C inter*ace. The labs "se the &}

_{C inter*ace. The labs "se the &}

_{C controller to}

_{C controller to}

con#ert the A#alon% inter*ace into the &

con#ert the A#alon% inter*ace into the &

_{C control signal. The &}

_{C control signal. The &}

_{C controller con9g"res}

_{C controller con9g"res}

the a"!io chip when the boar! is powere! "p.

the a"!io chip when the boar! is powere! "p.

#ata +nalysis Syste*

#ata +nalysis Syste*

 This !ata analysis s"bsystem analy?

 This !ata analysis s"bsystem analy?es the inp"t a"!io !ata "sing

es the inp"t a"!io !ata "sing a 9lter array an! energ

a 9lter array an! energy

y

calc"lation. The same inp"t a"!io !ata is sent

calc"lation. The same inp"t a"!io !ata is sent into 18 9lters with the !ierent pass an!

into 18 9lters with the !ierent pass an!

stop *re<"encies.

stop *re<"encies. &i$ure -

&i$ure - ill"strates the *re<"ency response *or 18 9lters in

 ill"strates the *re<"ency response *or 18 9lters in which the B

which the B

axis is *re<"ency an! the ; axis

&i$ure -: &requency Response #ia$ra* for 1 &ilters

 The a"!io inp"t !ata is sample! at 6 >?. The labs "se 18 9lters with 60 taps each. 6

>? x 18 x 60  50.:2 ?. Th"s 50.:2 ? is the thro"ghp"t re<"irement o* the system.

 The lab !esign "ses the 6 ? cloc as the main cloc *or the calc"lation) which is higher

than the thro"ghp"t re<"irement o* the system. This means yo" can "se a single

m"ltiplier an! acc"m"lator to !esign this whole 9lter array. &i$ure / shows the o"tp"ts o*

the 18 9lters) where the B axis e<"als the time line an! the ; axis e<"als the !ata #al"e.

&i$ure /: Exa*ple #ata Results of &IR &ilters

 The

 bloc acc"m"lates the absol"te #al"e o* the 9lter res"lt an! sen!s the energy

!ata o"t as a pacet with 18 bits o* !ata in A#alon%$T *ormat) as shown in ig"re 6) where

&i$ure 0: Ener$y #ia$ra* for 1 &requency +reas

&i$ure 0 shows that the *re<"ency response area increases *rom le*t to right. A parallel

&F4 ,&43 connecte! to a p"sh b"tton on the boar! con9g"res the calc"lation perio! *or the

energy. ;o" can change the #al"e to 278) 1026) 60G8) or 1856 samples. The

 triggers when the b"tton is p"she!) an! con9g"res the register in the

bloc to set the sample n"mber. The

 bloc acc"m"lates the absol"te #al"e o* the

&H res"lts with samples accor!ing to the n"mber. or example) i* the sample n"mber is

speci9e! as 60G8) the

 bloc acc"m"lates 60G8 times an! o"tp"ts one res"lt.

Energy res"lts are sent o"t as streaming !ata. &i$ure 0 shows an example o* the energy

res"lt *or each o* the 18 9lters.

Ener$y-L,# (loc) 

 The

 bloc con#erts the energy signals into a graphical representation an!

sen!s the res"lts to the

 bloc. To sa#e reso"rces) the real pict"re is not

store! in the !esign.

 The on%boar! LCD has a resol"tion o* 60x00 pixels) !i#i!e! into 18 sections that each

represent the energy res"lt o* one 9lter. The energy res"lt is nine bits o* !ata an! any

!ata bigger than 60 is treate! as 603. or example) i* the energy res"lt is 100) all o* the

lines smaller than 100 are sent o"t in re! color. or all o* the lines greater than or e<"al to

100) the lines are sent o"t in bl"e color. This !isplays the entire energy !iagram with

minim"m reso"rce "sage. The

 bloc recei#es the !ata *rom the

 bloc

as a streaming inp"t) an! sen!s o"t the *rame as streaming !ata.

L,# ,ontroller

 The

 con#erts the #i!eo !ata into an LCD *ormat an! !ri#es the LCD

!isplay !irectly. The

 accepts 52%bit !ata. The

 changes

the 52 bits into 26 bits. The

 changes the !ata *rom parallel into

serial with the se<"ence o* H) @) / re!) green) bl"e3. The

generates the sync signal *or the LCD) an! controls the *rame rate o* the o"tp"t. There is a

control port on the LCD) that "ses the &

_{$ b"s. There is one}

 _{bloc in the}

controller

 to con#ert the A#alon% control signal into an &

_{$ b"s) an! "ses a}

Lab 1: Explore an Existin$ sys #esi$n

 This lab intro!"ces yo" to the Qsys @'& by exploring a complete !esign. The estimate!

time to complete this lab is 80 min"tes) incl"!ing optional boar! programming.

L,# ,ontroller Subsyste* !%er%ie

 This lab !escribes the LCD control system in Qsys) generation o* the Qsys system)

compilation o* the pro+ect with the Q"art"s && so*tware) an! optional !ownloa!ing o* the

the res"lt to the =EE> boar!. ig"re 7 shows the components in the LCD controller.

&i$ure 2: L,# ,ontroller (loc) #ia$ra*

 The LCD controller incl"!es the *ollowing components

•  The Energy2LCD bloc generates the image !isplaye! on the LCD. &t pro#i!es an image e#en witho"t any inp"t. &n this system) yo" can t reat the bloc as a pattern generator. This bloc sen!s 52%bit wi!e streaming !ata) representing parallel pixel !ata.

•  The Pixel Converter bloc con#erts the 52%bit inp"t into 26%bit H@/ #i!eo parallel !ata. •  The Data Format Adapter bloc con#erts the parallel !ata into serial H) @) / with an %bit

streaming o"tp"t. This satis9es the Video Sync Generator bloc !ata wi!th re<"irement. •  The Video Sync Generator generates the #i!eo sync signals) s"ch as the frame sync an!

line sync signals. This bloc also recei#es an! sen!s !ata *rom the Data Format Adapter bloc.

• A &4 is typically re<"ire! between the !ata *ormat con#erter an! the Video Sync

Generator to ens"re that the Video Sync Generator can control the LCD *rame rate. /"t in this !esign) since the Energy2LCD bloc can pro#i!e !ata whene#er necessary) the &4 is not nee!e!.

•  The I2S bloc con9g"res the LCD chip on%boar! base! on the &2$ b"s. The system can control or monitor stat"s o* the bloc thro"gh its A#alon% sla#e inter*ace. &n this lab) the bloc per*orms the initial con9g"ration. The A#alon% sla#e inter*ace is present in this lab only to show the capability o* the b"s an! a#ailable options.

3ie t4e L,# ,ontroller

 To #iew the LCD controller) *ollow these steps

L+(_1 Fsys_lab.qpf  pro+ect.

2. 4n the ile men") clic !pen an! select the lcd_ctrl_subsys.qsys Qsys 9le. Qsys re*reshes the libraries an! !isplays the system as shown in ig"re 8.

&i$ure  L,# ,ontroller Syste* in sys

5. He#iew the system to become *amiliar with the Qsys @'&. The le*t pane contains the ,o*ponent Library) an! the right pane shows the system connections in the Syste* ,ontents tab.

6. To 9lter the connections #iew base! on the Qsys%s"pporte! inter*ace types) clic the &ilter b"tton. Qsys s"pports A#alon%) A#alon%$T) cloc) an! reset inter*aces. &n a!!ition Qsys s"pports con!"it inter*aces *or non%stan!ar! gro"ps o* signals.

7. Clic the +ddress 6ap tab to show the a!!ress mapping in*ormation between all o* the A#alon% master an! A#alon% sla#e inter*aces. ;o" can also e!it the start a!!ress *or each sla#e inter*ace) as ill"strate! in ig"re :.

&i$ure 7: L,# ,ontroller Syste* in sys

8. Clic the ,loc) Settin$s tab to #iew all clocs in the !esign) as shown in ig"re . &n Qsys) clocs are inter*aces that are connecte! to components in the same manner as other

component inter*aces. ;o" can also "se the ,loc)  col"mn in the Syste* ,ontents tab to mae cloc connections.

&i$ure 8: ,loc) Settin$s Tab

:. Clic the Pro5ect Settin$s tab to show global in*ormation abo"t the system) incl"!ing a bloc !iagram showing the exporte! top%le#el inp"t an! o"tp"t inter*aces an! some other global settings.

. Clic the Syste* Inspector tab to inspect the system connections) incl"!ing the external signals list) the internal connections) an! all o* the s"bmo!"les in the system) as shown in ig"re G.

&i$ure 9: Syste* Inspector Tab

G. Clic the "#L Exa*ple tab to !isplay an example Ierilog DL or IDL instantiation o* the top%le#el !esign 9le that Qsys generates. ;o" can copy *rom this tab an! paste into yo"r top% le#el DL 9le when yo" are creating a !esign that instantiates a Qsys system.

10. Clic the eneration tab to generate co!e *or sim"lation an! synthesis "n!er a

s"b!irectory o* the speci9e! path. The sim"lation 9les are generate! in the si*ulation !irectory) incl"!ing the sim"lation mo!el 9les an! a Tcl 9le to set "p the sim"lation en#ironment in o!el$im. The Qsys testbench system is generate! in the testbenc4 !irectory. &* yo" enable the option to create a testbench sim"lation mo!el) the sim"lation

9les are generate! in the same !irectory. Qsys generates a simple testbench that pro#i!es only the cloc an! reset signal stim"l"s along with any sim"lation partner mo!"les speci9c by yo"r &,3) as well as a stan!ar! testbench that also incl"!es sim"lation / blocs *or all o* the exporte! A#alon inter*aces. 'se o* this testbench is !escribe! in a s"bse<"ent lab. ig"re 10 shows the eneration tab.

&i$ure 1;: eneration Tab

11. 4n the eneration tab) mae s"re that ,reate "#L <les for Synt4esis is t"rne! on) an! !isable all other options. /eca"se this step !oes not incl"!e sim"lation) mae s"re that the ,reate si*ulation *odel an! ,reate testbenc4 Qsys system options are set to =one. 12. Clic enerate to generate DL 9les *or the Qsys !esign. Clic ,lose when generation is

complete. The synthesis co!e is generate! at the speci9e! location. ;o" can #iew the 9les in the synthesis !irectory.

15. To a!! the Qsys%generate! !esign 9les to the Q"art"s && pro+ect) clic Settin$s on the Assignments men" in the Q"art"s && so*tware.

16. &n the ,ate$ory list) clic &iles an! a!! lcd_ctrl_subsys.qip to the pro+ect. Qsys "p!ates the .qip 9le each time yo" mo!i*y an! generate the system.

17. To compile the pro+ect) clic Start ,o*pilation on the ,rocessing men".

Lab -: 6i$rate a Syste* fro* S!P, (uilder to sys

 This lab teaches yo" how to tae a!#antage o* the Qsys a!#ance! system integration

*eat"res by migrating a system create! with AlteraJs legacy $4,C /"il!er to Qsys. The

L+(_- !irectory o* the lab_qsys.zip archi#e contains the s"pporting 9les *or this lab. The

estimate! time to complete this lab is 50 min"tes.

,on%ert t4e S!P, (uilder Pro5ect

 The 9les *or this lab incl"!e an example $4,C /"il!er a"!io controller !esign that yo" can

migrate to Qsys. This example is a #ery simple !esign that incl"!es a ,LL that generates a

6%? cloc !omain base! on the 70%? inp"t cloc. The !ata streaming "ses the 6%

? cloc) an! the &

_{C con9g"ration logic "ses the 70%? cloc. The &}

_{C con9g"res the}

A"!io AD chip on the boar!) an! is controlle! by the

 bloc. The

 bloc accepts the a"!io !ata *rom the AD chip) gro"ps it into the A#alon%$T

inter*ace) an! sen!s it o"t thro"gh the so"rce inter*ace. ig"re 11 ill"strates the $4,C

/"il!er a"!io controller !esign.

&i$ure 11: +udio ,ontroller #ia$ra* for S!P, (uilder Syste*

 ;o" m"st 9rst prepare the $4,C /"il!er pro+ect prior to migration. To prepare the sample

$4,C /"il!er pro+ect *or migration) *ollow these steps

1. &n the Q"art"s && so*tware) clic !pen on the ile men" an! select the

L+(_->audio_controller.sopc 9le. He+ect the prompt to la"nch Qsys an! remain in $4,C b"il!er *or this section o* the lab.

2. To complete the !esign an! a#oi! errors in $4,C /"il!er) a!! an a!!itional A#alon%$T sin / bloc an! connect it to the so"rce inter*ace o* the AUDIO_IF _{bloc. &n Qsys) s"ch} "nconnecte! inter*aces generate only a warning an! system generation is not pre#ente!. 5. $a#e the system an! close $4,C /"il!er.

Export t4e S!P, (uilder #esi$n to sys

 To export the $4,C /"il!er !esign to Qsys) *ollow these steps

1. Heopen the FL+(_->audio_controller.sopc 9le) allowing the 9le to open in Qsys when prompte!.

2. Khen prompte!) enable the option to clean up S!P, (uilder <les. Qsys generates the top%le#el co!e with the same name as the $4,C /"il!er pro+ect "n!er a !ierent location. Khile $4,C /"il!er exports all o* the ,LL signals to the top le#el. Qsys pro#i!es more exibility *or system integration. or example) while Qsys exports areset_conduit) locked_conduit) an! phasedone_conduit inter*aces as &F4 ports or signals) only the Mloce!N signal m"st be exporte! to the top le#el.

5. Clic in the Export col"mn *or the areset_conduit an! phasedone_conduit rows) an! !elete the exporte! inter*ace name so these inter*aces are not exporte!. This is how yo" !e9ne which inter*aces sho"l! be exporte! as &F4 signals o* the system.

6. $elect an! !elete the "nnee!e! c0 cloc bri!ge3 bloc.

7. $a#e the 9le. The !esign sho"l! now appear as shown in ig"re 12. &i$ure 1-: +udio ,ontroller sys Syste*

8. Clic the eneration tab an! clic enerate to create the synthesis 9les *or the !esign. :. &n the Q"art"s && so*tware) clic Start ,o*pilation on the ,rocessing men".

. A*ter compilation is complete) "se the Q"art"s && ,rogrammer to !ownloa! the .sof  to the =EE> boar!.

4nce these steps are complete yo" can "se Qsys to generate the synthesis 9les *or the

Audio Controller

 bloc) a!! the generate! audio_controller.qip to the Q"art"s &&

pro+ect) an! compile the !esign in the Q"art"s && so*tware) as !escribe! below.

#onload ,on<$uration #ata

 To !ownloa! con9g"ration !ata) *ollow these steps

1. Connect the !ownloa! cable to the =EE> boar!. ;o" m"st 9rst install the !ri#er i* yo" ha#e not !one so.

2. Downloa! the !esign to the boar! with the Q"art"s && ,rogrammer.

5. ae the *ollowing connections to the three a"!io +acs on the top o* the boar! Table -: Required Softare and !ptional "ardare

,onnect &ro* ,onnect To

,C a"!io o"tp"t /l"e line%in port o* the =EE> boar! Earphone cable +ac @reen line%o"t o* the =EE> boar!

/eca"se Qsys can per*orm reset synchroni?ation) yo" can choose to connect all resets in a

single global reset !omain by selecting ,reate lobal Reset =etor)  on the $ystem

men". &* yo"r !esign re<"ires more than one reset !omain) yo" can implement yo" own

reset logic an! connecti#ity.

Lab /: I*port a =e ,o*ponent

 ;o" can create a re"sable) c"stom &, component by importing DL co!e to the Qsys

Component E!itor. This lab shows yo" how to create a c"stom re"sable &, bloc *or "se in

Qsys. The L+(_/ !irectory o* the lab_qsys.zip archi#e contains the s"pporting 9les *or

this lab. The estimate! time to complete this lab is 67 min"tes.

 The L+(_/ !irectory pro#i!es the DL co!e 9les *or the

 bloc calc"lation. The

Energy

 bloc accepts !ata *rom the A#alon%$T sin inter*ace) an! sen!s the res"lt o"t

thro"gh the A#alon%$T so"rce inter*ace. This bloc contains an A#alon% sla#e inter*ace

*or control. Table 5 shows the register mapping *or the

 bloc

Table /: Ener$y (loc) +ddress 6ap

+ddress +ccess Re$ister

0x00 O 0x1* Hea! 4nly The energy res"lt *or each *re<"ency area. 0x20 KriteFHea! The calc"lation length *or the energy

calc"lation. or example i* the !ata is 206) the Energy bloc acc"m"lates 206 samples o* inp"t as the o"tp"t.

 To create a new Qsys component by importing DL co!e) per*orm the *ollowing steps

1. &n the Qsys ,o*ponent Library) !o"ble clic =e ,o*ponent. The Component E!itor appears.

2. Clic the "#L &iles tab.

5. Clic +dd an! a!! the ener$y.%) res_ra*.%) an! ra*_b).% 9les *rom the L+(_/ !irectory to the "#L &iles list.

6. or each 9le) mae s"re that the Synt4 an! Si* options are enable!.

7. T"rn on the Top option *or ener$y.% to !esignate it as the top%le#el 9le. =ote that memory initiali?ation 9les nee! to be incl"!e! into this 9le list i* they are nee!e!. Qsys copies all o* the &, 9les into the s"bmo!"les !irectory) th"s any 9les necessary *or synthesis or

sim"lation m"st be incl"!e!.

8. To !e9ne the inter*ace signals) clic the Si$nals tab. Qsys recogni?es the cloc signal as a cloc inter*ace a"tomatically. ;o" may nee! to !e9ne the signals *or other inter*aces. &* the correct inter*ace type is not liste!) yo" can !e9ne a new inter*ace on the Interface tab. :. To !e9ne the rst_n signal as a resetPsin inter*ace) clic the Interface col"mn an! select

ne Reset Input.

. De9ne the signals in ig"re 15 *or the cloc) reset inp"t) A#alon sla#e) A#alon%$T sin) an! A#alon%$T so"rce inter*aces. The inter*aces yo" !e9ne now appear on the Interfaces tab.

&i$ure 1/: Si$nal #e<nitions in sys ,o*ponent Editor

G. Clic the Interfaces tab.

10. Clic Re*o%e Interfaces ?it4 =o Si$nals.

11. or each inter*ace) speci*y clock *or +ssociated ,loc) ) an! reset_sink *or +ssociated Reset. =ote that reset inter*aces are !ierent between Qsys an! $4,C /"il!er. ;o" can !e9ne both reset inp"t an! reset o"tp"t inter*aces in Qsys.

12. or the A#alon%$T so"rce an! sin inter*aces) speci*y 1 as the #ata bits per sy*bol. The Energy bloc recei#es the !ata *rom &H an! o"tp"ts the res"lt to the next stage. There*ore these inter*aces are 18 bits wi!e.

15. To #iew any DL parameters associate! with the inter*aces) clic the "#L Para*eters tab. &* the DL co!e incl"!es any parameters) the Component E!itor generates a @'& *or "se in setting these #al"es !"ring instantiation. This lab incl"!es the OUTPUT_MSB parameter in the ener$y.% 9le.

16. Clic the Library Info tab. &n #isplay na*e) type Energy an! !o not mo!i*y the #al"e o* 3ersion. &n the roup box) speci*y &+E ,erti<cation Lab.

17. Con9rm that there are no error or warning messages) an! then clic &inis4 in the Component E!itor.

Lab 0: #esi$n a sys Syste*

 ;o" can create yo"r own Qsys system *rom scratch. This lab shows yo" how to create the

new Qsys system shown in ig"re 16. The L+(_0 !irectory o* the lab_qsys.zip archi#e

contains the s"pporting 9les *or this lab. The estimate! time to complete this lab is 50

min"tes.

&i$ure 10: #ata +nalysis Syste* (loc) #ia$ra*

,reate a =e sys #esi$n

 To create a new Qsys !esign) per*orm the *ollowing steps

1. &n the Q"art"s && so*tware) open the L+(_0>quartus_lab.qpf  pro+ect.

2. 4n the Tools men") clic sys. Qsys !isplays a new system with only a single cloc so"rce. 5. $a#e the new system as data_analysis.

#e<ne an IP ,o*ponent

 ;o" m"st a!! *o"r &, blocs to the system an! mae the connections. To a!! the &, blocs

to the system) *ollow these steps

1. &n the Qsys ,o*ponent Library) !o"ble%clic Perip4erals @ 6icrocontroller

Perip4erals @ PI! AParallel I>!B. The parameter e!itor !isplays the properties o* the &, core. The ,&4 &, core is pro#i!e! with Qsys *or general p"rpose &F4 signals. &n this lab) yo" simply connect it with the p"sh b"tton on the boar!.

&i$ure 12: PI! Para*eters

5. Clic &inis4 to generate the component.

6. Clic Sa%e an! rename the system as data_analysis.

7. &n the Qsys Syste* ,ontents tab) right%clic the PI! component yo" !e9ne! an! rename the ,&4 instance to as push_buttons.

+dd !t4er IP ,o*ponents

 This lab incl"!es an &+E ,erti<cation Lab gro"p in the Qsys ,o*ponent Library. This

gro"p incl"!es all o* the &, cores necessary *or this lab. To a!! &, cores *rom this gro"p to

yo"r system) *ollow these steps

&IR

1. 'n!er the &+E ,erti<cation Lab gro"p in the Qsys ,o*ponent Library) !o"ble%clic the &IR component. The parameter e!itor appears.

data_analysis_state_*ac4ine

 The !ataPanalysisPstatePmachine component is re<"ire! in the system to accept the

interr"pt signal *rom the ,&4 an! con9g"re the

 bloc. To !e9ne the

!ataPanalysisPstatePmachine component) *ollow these steps

1. 'n!er the &+E ,erti<cation Lab gro"p in the Qsys ,o*ponent Library) !o"ble%clic the data_analysis_state_*ac4ine component. The parameter e!itor appears.

2. $peci*y the *ollowing #al"es ,+L,CL+TE_=C6; 278 ,+L,CL+TE_=C61 1026 ,+L,CL+TE_=C6- 60G8 ,+L,CL+TE_=C6/ 1856

 The state machine switches between these *o"r n"mbers) an! writes the n"mber into the

Energy

 bloc when the p"sh b"tton is acti#e. There are two master inter*aces in this state

machine) an! yo" "se the a#alonPmaster inter*ace to control the ,&4 an! accept the

interr"pt. ;o" "se the a#alonPmasterP1 inter*ace to write the calc"lation n"mber into the

Energy

 bloc.

Export Interfaces

 The 9rPin inter*ace o* the

 bloc !ri#es the !ataPin *or the !ata path. This is an A#alon%

$T sin inter*ace. To export appropriate inter*aces) *ollow these steps

1. 4n the Qsys Syste* ,ontents tab) clic the Export col"mn *or the !ataPin inter*ace an! type 9rPin as the name o* the exporte! inter*ace. 9rPo"t is connecte! to the energyPin inter*ace in the Energy bloc.

2. 4n the Qsys Syste* ,ontents tab) clic the Export col"mn *or the energyP0 inter*ace an! type energy_out as the name o* the exporte! inter*ace.

5. 4n the Qsys Syste* ,ontents tab) clic the Export col"mn *or the p"shPb"ttons inter*ace an! type push_buttons_external_connection as the name o* the exporte! inter*ace.

6a)e ,onnections

 To mae connections between the components) *ollow these steps

1. 4n the Syste* ,ontents tab) connect all cloc an! reset signals to the cloc o"tp"t an! reset o"tp"t *rom the cloc so"rce

a. To connect the clocs) speci*y the cloc signal name in the ,loc)  col"mn.

b. To connect the resets) clic ,reate lobal Reset =etor)  on the $ystem men". 2. Clic in the ,onnections col"mn to 9ll in the blac !ot *or each connection shown in ig"re

18. 'se the "p an! !own arrows in the toolbar to change the or!er o* components in the system.

&i$ure 1: #ata +nalysis Syste* ,onnections in sys

5. Clic the eneration tab.

6. Clic enerate to create the DL !esign 9les *or synthesis.

 This lab completes the basic system !esign. &n the next labs yo" sim"late this !esign an!

per*orm in%system !eb"g with the $ystem Console. ;o" connect this system with the other

s"bsystem to create the top%le#el Qsys !esign.

 Lab 2: Si*ulate t4e #ata +nalysis Syste* AoptionalB

 ;o" can sim"late the !ata analysis system. This lab shows how to "se the Altera A#alon

Ieri9cation /s to #eri*y the Qsys system *rom Lab 6. The L+(_2 !irectory o* the

lab_qsys.zip archi#e contains the s"pporting 9les *or this lab. The estimate! time to

complete this lab is 67 min"tes.

&n this lab) yo" "se Ierilog DL to highlight the /s an! a"tomate! testbench

generation. The !ataPanalysis !esign is the !esign "n!er test D'T3) the

 bloc is

!ri#en by an A#alon%$T so"rce / component) an! the !ata *rom the

 bloc is

#eri9e! by an A#alon%$T sin / component.

&* yo"r !esign is base! on IDL) yo" !o not ha#e to "se a Qsys%generate! testbench with

A#alon /s. ;o" can create yo"r own sim"lation en#ironment an! generate IDL

sim"lation mo!el 9les in Qsys.

 This lab incl"!es the *ollowing sections

• Create A#alon stan!ar! /s *or yo"r D'T • ,repare a test program that calls / A,&s •  $tart a sim"lation

,reate +%alon standard (&6s for your #CT

 To create A#alon stan!ar! /s *or yo"r D'T) *ollow these steps

1. &n the Q"art"s && so*tware) open the L+(_2>quartus_lab.qpf  pro+ect. 2. 4n the Tools men") clic sys.

5. 4n the ile men") clic !pen an! select the complete! data_analysis.qsys 9le.

6. He#iew the *ollowing exported interfaces shown in ig"re 1:

• cl • reset

• p"shPb"ttonsPexternalPconnection • 9rPin

• &i$ure 17: #ata +nalysis Syste* ,onnections in sys

7. Clic the eneration tab.

8. or ,reate testbenc4 sys syste*) select StandardD (&6s for standard +%alon interfaces.

:. or ,reate testbenc4 si*ulation *odel) select =one.

. 'n!er Synt4esis) t"rn o all options. ig"re 1 shows the correct settings. G. Clic enerate. Qsys generates a testbench system *or the !esign "n!er test. &i$ure 18: eneration Settin$s for sys Testbenc4 Syste*

10. rom the L+(_2data_analysistestbenc4 !irectory) open the data_analysis_tb.qsys 9le to change /s component settings or rename / components) i* nee!e!.

 The Qsys%generate! testbench a"tomatically incl"!es matche! /s *or all

exporte! inter*aces o* the D'T as shown in ig"re 1G.

&i$ure 19: 6atc4ed (&6s for all Exported Interfaces of t4e #CT

Qsys inserts clPb*m) resetPb*m) 9rPinPb*m) energyPo"tPb*m an! a con!"it b*m *or

this D'T. The A#alon%$T so"rce or sin / component incl"!es the *ollowing *o"r

parts relate! to A#alon%$T protocol parameters. &* yo" a!! /s man"ally) yo" nee!

to a!+"st them to meet yo"r re<"irement.

• ,ort enables • ,ort wi!ths

•  Timing attrib"tes • Channel attrib"tes

11. A*ter re#iewing the testbench) clic the eneration tab. 12. or ,reate si*ulation *odel) select 3erilo$.

15. or ,reate testbenc4 sys syste*) select =one. 16. 'n!er Synt4esis) t"rn o all options.

17. Clic enerate. Qsys generates the testbench system sim"lation mo!els in the L+(_2data_analysistestbenc4data_analysis_tbsi*ulation !irectory.

Prepare a test pro$ra* t4at calls (&6 +PIs

 ;o" can generate the sim"lation mo!el *or the Qsys testbench system at the same time

that yo" create the system by t"rning on ,reate testbenc4 si*ulation *odel.

owe#er) *or !emonstration p"rposes this lab shows yo" how to create the mo!els in two

steps so yo" can control the instance names or a!+"st settings to mae it easier *or yo" to

write yo"r own test program *or the /s) as ill"strate! in ig"re 20.

&i$ure -;: eneration for Si*ulation 6odel

Qsys generates the sim"lation mo!els an! a o!el$im sim"lation script

*si*_setup.tcl3) which compiles the re<"ire! 9les *or sim"lation an! sets "p comman!s

to loa! the sim"lation in the o!el$im sim"lator.

 This lab section "ses the pro#i!e! test_pro$ra*.s% external test program to call /

A,&s that pro#i!e sim"lation stim"l"s. The pro#i!e! load_si*.tcl sim"lation script

compiles the top%le#el sim"lation 9le an! test program) an! calls the *si*_setup.tcl

Qsys%generate! script to compile the re<"ire! 9les.

Copy the sim"lation 9les load_si*.tcl) test_pro$ra*.s%) top.s%) a%e.do3 *rom the

sim"lation 9les *ol!er into the

L+(_2data_analysistestbenc4data_analysis_tbsi*ulation !irectory.

1. To "n!erstan! how to "se the / A,&s) open an! #iew the test_pro$ra*.s%. Test programs sho"l! be implemente! in $ystemIerilog. The testPprogram implements the *ollowing *"nctions

• &nitiali?es /s

• Calls A,&s to A#alon%$T so"rce /

• Constr"cts stim"l"s A#alon%$T transactions • ,"shes transactions

• Calls A,&s to A#alon%$T sin / • onitors signalPtransactionPrecei#e! • ,ops transactions to recei#e the !ata

or !etails on the / A,&s) please re*er to

a#ailable at httpFFwww.altera.comFliterat"reF"gF"gPa#alonP#eri9cationPip.p!* .

2. La"nch the o!el$im Altera E!ition so*tware.

5. 4n the Compile men") clic ,o*pile !ptions an! t"rn on Cse Syste*3erilo$. 6. T"rn o the Cse %opt Fo option) as shown in ig"re 21.

7. rom the ile men") change to the

L+(_2data_analysistestbenc4data_analysis_tbsi*ulation !irectory. 8. To spee! "p the sim"lation process) open the

L+(_2data_analysistestbenc4data_analysis_tbsi*ulationsub*odulesener$ y.% 9le an! change the #al"e 60G8 to 712 on line 121) as shown in ig"re 22.

&i$ure --: ,4an$es to Ener$y.%.

:. rom the Tools men") go to Tcl '@ Execute *acro) an! exec"te load_si*.tcl. . H"n the sim"lation *or 12ms with the run 1- *s comman!.

G. 4bser#e the wa#e res"lts. As yo" can see *rom the sim"lation) the res"lt *or the 9rst pacet is

2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0R) as shown in ig"re 25. &i$ure -/: Si*ulation ?a%e #ia$ra*

Lab : Cse "ierarc4y to +sse*ble t4e &inal sys syste*

 ;o" can "se hierarchy *eat"res in Qsys to assemble the top le#el system. This lab shows

yo" how to !esign a top%le#el Qsys system by combining m"ltiple Qsys s"bsystems. The

L+(_ !irectory o* the lab_qsys.zip archi#e contains the s"pporting 9les *or this lab. The

estimate! time to complete this lab is G0 min"tes.

 The "ses the *ollowing components

• LCD Controller system the !esign yo" explore! in Lab 13

• A"!io Controller system the !esign yo" con#erte! *rom $4,C /"il!er in Lab 23 • Data Analysis system the !esign yo" ma!e in Lab 6 3

• Cloc controller

Re%ie and +d5ust t4e ,loc) and Reset Structure

 To re#iew the cloc an! reset str"ct"re) *ollow these steps

1. &n the Q"art"s && so*tware) open the L+(_>quartus_lab.qpf  pro+ect. 2. 4n the Tools men") clic sys.

5. 'se the !pen comman! on the ile men" to open the *ollowing Qsys pro+ects Lcd_ctrl_subsys

+udio_in_subsys

#ata_analysis_subsys ,loc)_subsys

6. 4pen the cloc)_subsys.qsys pro+ect to re#iew the cloc an! reset str"ct"re o* the !esign) as ill"strate! in ig"re 26.

&i$ure -0: ,loc) ,ontroller Syste*

'se this system to re#iew the str"ct"re o* clocs an! resets. 'se a reset bri!ge to

bring the reset into the system) an! "se a cloc so"rce to bring the cloc in. 'se the

,LL to generate three internal cloc !omains. The

 is exporte! on boar!

as the #i!eo chip cloc. The

 "ses

. The a"!io controller

an! !ata analysis systems "se

.

7. He#iew the other three systems. /eca"se the !esign *or this lab has an in!epen!ent cloc system) the ,LL an! reset control part in the Audio bloc an! the LCD controller are

remo#e!. This is the only !ierence between the s"bsystems here an! the systems in pre#io"s labs.

8. 4n the Qsys ile men") clic =e Syste* an! sa#e the new !esign as system.

:. 4n the Syste* ,ontents tab) change the name o* the clk_0 Cloc $o"rce instance to clk_in) an! set the exporte! Cloc &np"t inter*ace name to clk_in.

+dd t4e Reset (rid$e

1. rom the ,o*ponent Library) !o"ble%clic the Reset (rid$e to !e9ne the global reset bloc that creates the reset connection. $peci*y the *ollowing o ptions *or this component a. T"rn on +cti%e Lo Reset.

b. &n the Sync4ronous Ed$es list) select =one.

2. &n the Export col"mn) speci*y the export o* the inPreset inter*ace with the name o* reset_n an! connect the o"tPreset Heset 4"tp"t inter*ace with the clk_in_reset Heset &np"t

inter*ace o* the clk_in bloc.

+dd t4e ,loc) Subsyste*

1. rom the ,o*ponent Library) !o"ble%clic the Pro5ect '@ Syste* '@ cloc)_subsys component to a!! it to the system. There are no parameters a#ailable when instantiating s"bsystems.

7. Export the #i!eoPcl an! the pllPloce! inter*aces with the !e*a"lt names. Clocs an! resets are exporte! by !e*a"lt when instantiate!. ;o" can clic on the Export col"mn to !elete the contents when the signal sho"l! be connecte! internally instea! o* being exporte!.

8. A!! audio_in_subsys into the system an! name the instance audio_in.

:. Connect audio_clk_in with the audio_clk_clk *rom the clock_generate bloc. . Connect config_clk with the clk_in signal o* the clk inter*ace.

G. Connect the correspon!ing reset inter*aces *or each cloc.

10. &n the Export col"mn) export a"!ioPi*P0Pa"!ioPexport inter*ace as audio_export. 11. &n the Export col"mn) export i2cPa"!ioPcon!"itPen! as i2c_audio.

+dd t4e #ata +nalysis Subsyste*

1. rom the ,o*ponent Library) !o"ble%clic the Pro5ect '@ Syste* '@ data_analysis_subsys component to a!! it to the system.

2. Change the s"bsystem instance name to data_analysis.

5. Connect the cloc so"rce to audio_clk_clk an! connect the correspon!ing reset. 6. Export p"shPb"ttonPexternalPconnection as push_buttons.

7. Connect the 9rPin inter*ace with the a"!ioPi*P0Pa"!ioPst inter*ace *rom the audio_in bloc.

+dd t4e En$ery-L,# Subsyste*

1. rom the ,o*ponent Library) !o"ble%clic the &+E ,erti<cation Lab '@ Ener$y-L,# component to a!! it to the system. This is the bloc to con#ert the energy res"lt to be the LCD #i!eo pict"res.

2. Hename the Energy2LCD bloc as Energy2LCD_inst. 5. Connect core_clk with the lcd_clk.

6. Connect sink_clk with audio_clk.

7. Connect the correspon!ing reset inter*aces.

8. Connect the stPsin inter*ace with the energy_out inter*ace *rom the data_analysis bloc.

+dd t4e L,# ,ontroller Subsyste*

1. rom the ,o*ponent Library) !o"ble%clic the Syste* '@ lcd_ctrl_subsys component to a!! it to the system.

2. Hename the lcd_ctrl_subsys bloc instance as lcd_ctrl. 5. Connect lcd_clk with lcd_clk *rom the ,LL.

6. Connect lcd_i2s_clk with clk_in o*  clk.

7. Export the lc!P#i!eoPse<"encerPsync inter*ace as lcd_video_sequencer_sync. 8. Export the lc!Pi2s inter*ace as lcd_i2s.

:. Connect the lc!PpixelPcon#erterPin inter*ace with the stPso"rce inter*ace *rom the Energy2LCD bloc.

+dd t4e GT+ to +%alon 6aster (rid$e

1. rom the ,o*ponent Library) !o"ble%clic the (rid$es and +daptors '@ 6e*ory 6apped %S GT+ to +%alon 6aster (rid$e component to a!! it to the system. 2. Hename the bri!ge as jtag P master.

5. Connect the cloc to clk_in o*  clk an! the reset to the clk_in port o* clk_reset.

&i$ure -2: Top'Le%el ,loc) Structure

6. To connect the master inter*aces o* this bloc with all the sla#e inter*aces it can access) right%clic the master inter*ace an! #iew the connections) as ill"strate! in ig"re 28. &i$ure -: ,onnection of t4e 6aster Interface

7. Change the base a!!ress o* A#alon sla#e inter*aces as shown in Table 6. ;o" can #iew all the a!!resses on the +ddress 6ap tab.

Table 0: (ase +ddress of +%alon *aster in Top Le%el

Instance =a*e Interface =a*e Interface (ase +ddress a"!ioPin a"!ioPi*P0Ps1 0x00000000

a"!ioPin i2cPa"!ioPs1 0x00000100 lc!Pctrl lc!Pi2sPcon9gPs1 0x00000200 clocPgenerate pllPpllPsla#e 0x00000500

ig"re 2: shows the main system connections in the $ystem Contents tab.

&i$ure -7: #ata Pat4 #esi$n at Top Le%el

 The *ollowing tables list the exporte! signals an! connections *or the cloc an! reset.

Table 2: Exported Si$nals for Top

Instance =a*e Interface =a*e Exported =a*e @lobalPreset &nPreset resetPn

ClocPin ClPin clPin

ClocPgenerate ,llPloce! clocPgeneratePpllPloce! Ii!eoPcl clocPgenerateP#i!eoPcl A"!ioPin A"!ioPi*P0Pa"!ioPexport a"!ioPexport

&2cPa"!ioPcon!"itPen! i2cPa"!io DataPanalysis ,"shPb"ttonsPexternalPconnection p"shPb"ttons

Lc!Pctrl Lc!P#i!eoPse<"encerPsync lc!P#i!eoPse<"encerPsync

Table : ,loc) and Reset Si$nals

,loc) or Reset out ,loc) or Reset in @lobalPreset.o"tPreset clPin.clPinPreset ClocPgenerate.resetPn ClPin.clPreset tagPmaster.clPreset A"!ioPin.con9gPclPreset Lc!Pctrl.lc!Pi2sPclPreset ClocPgenerate.A"!ioPclPclPreset A"!ioPin.A"!ioPclPinPreset DataPanalysis.ClPinPclPinPreset Energy2lc!Pinst.sinPreset ClocPgenerate.lc!PclPclPreset Energy2LCDPinst.corePreset Lc!Pctrl.lc!PclPclPinPreset ClPin.cl ClocPgenerate.clPin  tagPmaster.clPin A"!ioPin.con9gPcl Lc!Pctrl.lc!Pi2sPcl ClocPgenerate.a"!ioPclPcl A"!ioPin.a"!ioPclPin DataPanalysis.clPin Energy2LCDPinst.sinPcl ClocPgenerate.lc!PclPcl Energy2LCDPinst.corePcl Lc!Pctrl.lc!Pcl

enerate t4e Syste*

Kith all o* the system connections complete) yo" are rea!y to generate the system. To generate the system) *ollow these steps

1. ae s"re to re#iew an! correct any errors !isplaye! in the messages box. 4n the eneration tab) clic enerate to create the synthesis 9les *or this system.

2. He#iew the synthesis path o* the system 9les yo" ha#e create!. &n the Q"art"s && so*tware) clic +dd>Re*o%e &iles in Pro5ect to a!! the syste*.qip 9le into the 9le list.

5. &n the Q"art"s && so*tware) open the sys_lab co!e 9le) an! open the syste*.% 9le create! by Qsys.

6. He#iew the top%le#el instance. Ens"re that there are no missing or incorrect signal names. Cloc an! reset signal names m"st be correct in the !esign *or the sim"lation to *"nction correctly.

7. 4n the ,rocessing men") clic Start ,o*pilation. The compilation may re<"ire se#eral min"tes to complete.

8. 'se the Q"art"s && ,rogrammer to !ownloa! the !esign to the =EE>.

:. Connect the a"!io cable between the ,C an! the =EE> boar! an! play some m"sic or so"n!s *rom yo"r connecte! ,C an! #eri*y the !isplay on the LCD screen. The acc"racy o* the lab res"lts may not be realistic. &* the bars are not <"ite clear on the screen) yo" can a!+"st the #ol"me o* the so"n!s in yo"r machine. Alternati#ely) yo" can a!+"st the *resh *re<"ency o* the !ata. The !ata #al"e range changes as well.

Lab 7: Cse Syste* ,onsole to #ebu$ t4e Syste* AoptionalB

 This lab shows yo" how to "se $ystem Console to !eb"g the system as shown in ig"re 2.

$ystem Console per*orms low%le#el har!ware !eb"gging o* Qsys systems. 'se the $ystem

Console to !eb"g systems that incl"!e &, cores instantiate! in yo"r Qsys system) as well

as *or initial bring%"p o* yo"r printe! circ"it boar!) an! *or low%le#el testing. The L+(_7

!irectory o* the lab_qsys.zip archi#e contains the s"pporting 9les *or this lab. The

estimate! time to complete this lab is 80 min"tes.

&i$ure -8: Syste* ,onsole (loc) #ia$ra*

+dd Syste* ,onsole ,o*ponents

 To !eb"g the !ataPanalysis s"bsystem with $ystem Console) *ollow these steps

1. &n the Q"art"s && so*tware) open the L+(_7>quartus_lab.qpf  pro+ect. 2. 4n the Tools men") clic sys.

5. 'se the !pen comman! on the 9le men" to open data_analysis_subsys.qsys

&n this lab) yo" a!! two components to the system *or !eb"gging. 4ne component

is

) which consists o* three A#alon inter*aces one A#alon%$T

so"rce) one A#alon%$T sin an! one A#alon% sla#e inter*ace. An A#alon%$T sin

inter*ace recei#es the !ata stream *rom the A"!io inter*ace( the maxim"m absol"te

#al"e in the !ata stream is sa#e! in an internal register which is mappe! into an

A#alon sla#e a!!ress space an! cleare! a*ter it is rea!. The !ata stream is sent to

the

 mo!"le thro"gh an A#alon%$T so"rce inter*ace. =either the so"rce nor sin

inter*ace incl"!e $tart o* ,acet $4,3 an! En! o* ,acet E4,3 signals.

 The other component is

) which is similar to the

 component) except that the A#alon%$T inter*ace incl"!es $4, an! E4,

signals. This component can recei#e !ata pacets *rom the

 an!

 mo!"le

an! sen! them to the next instance in the !esign. An A#alon sla#e inter*ace

connects with a TA@ to A#alon aster /ri!ge instance. This maes internal registers

accessible thro"gh the $ystem Console.

 The

 an!

 components co"l! be inserte!

into the A#alon%$T !ata path an! not in"ence the !ata processing o* the *"ll

6. $elect the exporte! con!"it fir_in *rom theFIR bloc) an! !elete the exporte! signal. 7. rom the &+E ,erti<cation Lab gro"p) a!! the ST Data LogicTap _component.

8. Change the name o* the ST Data LogicTap component to data_in. :. &n the Export col"mn) export the stPsin inter*ace as fir_in.

. rom the &+E ,erti<cation Lab gro"p) a!! two instances o* the ST Packet LogicTap component.

G. Change the two instance name o* one ST Packet LogicTap to fir2energy an! energy_out.

10. Delete the exporte! energy_out con!"it *rom the energy_0 component.

11. &n the Export col"mn) export the stPso"rce inter*ace o* energy_out asenergy_out.

12. Clic the &ilter b"tton an! select +%alon'ST Interface as the 9lter con!ition. 'se the 6o%e Cp or 6o%e #on b"tton to a!+"st the location o* the instances. Connect the A#alon% $T inter*aces as shown in ig"re 2G.

&i$ure -9: Syste* ,onnection of #ata +nalysis

15. Clic the &ilter b"tton an! select +%alon'66 Interface as 9lter con!ition.

16. rom the ,o*ponent Library) !o"ble%clic the (rid$es and +daptors '@ 6e*ory 6apped '@ GT+ to +%alon 6aster (rid$e component to a!! it to the system. 17. Hename the bri!ge as master_0.

18. Clic 6o%e Cp to mo#e this instance to the top position as shown in 9g"re 50.

1:. Connect the master inter*ace o*master_0 to the sla#e inter*ace o* data_in) fir2energy) energy_0) an! energy_out as shown in ig"re 50.

&i$ure /;: #ata +nalysis #esi$n it4 Syste* ,onsole #ebu$ (loc)s

1. 4n the Qsys $ystem men") clic +ssi$n (ase +ddresses to remo#e a!!ress o#erlap error. 1G. ae s"re that the a!!resses in the system match those in ig"re 50.

20. Clic the &ilter b"tton an! select ,loc) and Reset Interfaces as the 9lter con!ition. 21. Connect the cloc inter*aces to the clk_in inp"t o* the clk bloc. Connect the resetPsin

an! masterPclPreset inter*aces to the clk_in inp"t o* clk_reset. 22. 4n the Qsys ile men") clic Sa%e.

25. 4n the ile men" clic !pen an! open syste*.qsys

26. Clic the eneration tab an! clic enerate to create the synthesis 9les *or the !esign. 27. &n the Q"art"s && so*tware) clic Start ,o*pilation on the ,rocessing men".

28. A*ter compilation is complete) "se the Q"art"s && ,rogrammer to !ownloa! the .sof  to the =EE> boar!.

2:. Hename the .sof  to reser#e it *or later "sage. or example) yo" may rename it sys_lab_*sb8.sof .

#ebu$ it4 Syste* ,onsole

 To "se $ystem Console to !eb"g the system) *ollow these steps

1. To open $ystem Console) clic Syste* ,onsole *rom the Tools men". 2. To list all masters in the !esign) type the *ollowing comman!

get_service_paths master

ig"re 51 shows an example o* the res"lting o"tp"t. &i$ure /1: Exa*ple Transcript

 The get_service_paths comman! always ret"rns a list) e#en i* the list has a single item. Conse<"ently) yo" m"st in!ex into the list "sing the lindex comman!. &n this example) the 9rst element o* the list is master_0. Ial"e ?ero o* the list is the jtag_master mo!"le locate! in the Qsys system top le#el.

5. To speci*y the path *or the master_0 master ser#ice) type the *ollowing comman! i* master_0 is the 9rst element in the list

set jtag_master_1 [lindex [get_service_paths master] 1]  Type the *ollowing comman! i* master_0 is the 9rst element in the list

set jtag_master_1 [lindex [get_service_paths master] 0]

A*ter the comman! r"ns) the transcript *rom the interacti#e session shown in ig"re

52 appears.

&i$ure /-: Exa*ple Transcript

 The *ollowing tables list the a!!ress map o* each sla#e mo!"le to



Table 7: Ener$y_; +ddress 6appin$ (ase +ddress !Hset

+ddress

+ccess #escription

0x0 0x0 U 0x1* Hea! 4nly appe! to internal !ata memory space. Each 18%bit hal* wor! stores one energy res"lt o* each *re<"ency area. The energy res"lt is one G%bits !ata. igh :%bits o* hal*  wor! are 9xe! to 0.

0x20 HFK The calc"lation length *or the energy calc"lation. or example i* the !ata is 206) Energy bloc acc"m"lates 206 samples o* inp"t as the o"tp"t.

0x22 U 0x5* Heser#e!

Table 8: #ata_in bloc) +ddress 6appin$ (ase +ddress !Hset

+ddress

+ccess #escription

0x60 0x0 Hea! 4nly The maxim"m absol"te #al"e in the !ata stream

Table 9: <r-ener$y bloc) +ddress 6appin$ (ase +ddress !Hset

+ddress

+ccess #escription

0x0 0x0 Hea! 4nly The maxim"m absol"te #al"e in the !ata stream

Table 1;: ener$y_out bloc) +ddress 6appin$ (ase +ddress !Hset

+ddress

+ccess #escription

0x80 0x0 Hea! 4nly The maxim"m absol"te #al"e in the !ata stream

6. To rea! the internal register content o* data_in) type the *ollowing comman!

master_read_16 $jtag_master_1 0x40 0x1

ig"re 55 shows the transcript *rom this comman!.

&i$ure //: Exa*ple Transcript

7. 'se the ', an! D4K= arrow eys on yo"r comp"ter to scroll thro"gh the comman! history. A!+"st the #ol"me o* the inp"t a"!io an! rea! bac the maxim"m #al"e repeate!.

8. The secon! arg"ment o* the comman! in $tep 6 is the base a!!ress o* the internal register.  To change the a!!ress to rea! the contents o* these registers) type the *ollowing comman!

master_read_16 $jtag_master_1 0x0 0x10

ig"re 56 shows the transcript *rom this comman!.

&i$ure /0: Exa*ple Transcript

$ystem Console might report that all #ali! bits ha#e a #al"e o* one. &n the LCD

!isplay) all histograms reach the top o* the screen. This means the register has

o#erowe! an! the c"rrent

 parameter is not s"itable. ;o" m"st change

the

 parameter o* the

 mo!"le to eliminate the o#erow.

:. Clic !pen on the ile men" an! open data_analysis_subsys.qsys

. Do"ble clic ener$y_; in the $ystem Contents tab. The parameter e!itor appears. G. $et the 4'T,'TP$/ parameter to -0.

10. Clic &inis4 to close the parameter e!itor. 11. $a#e the s"bsystem.

12. Clic !pen on the ile men" an! open syste*.qsys.

15. Clic the eneration tab an! clic enerate to create the synthesis 9les *or the !esign. 16. &n the Q"art"s && so*tware) clic Start ,o*pilation on the ,rocessing men" to compile the

Q"art"s && pro+ect.

17. A*ter compilation is complete) close $ystem Console.

18. 'se the Q"art"s && ,rogrammer to !ownloa! the generate! .sof  to the =EE> boar!. 1:. 4n the Tools men") clic Syste* ,onsole.

1. Type the comman!s shown in ig"re 57. &i$ure /2: Syste* ,onsole ,o**ands

$ystem Console reports that the high%en! bits o* registers !o not ha#e a #al"e o* one. The OUTPUT_MSB parameter is now an appropriate #al"e. The !isplay o* LCD shows that the histograms !o not reach the top o* the screen.

1G. Type the *ollowing comman! to rea! the calc"lation length *or the energy calc"lation

master_read_16 $jtag_master_1 0x20 0x1

20. Type the *ollowing comman! to change the calc"lation length to 0x2000 1G2 in Decimal3

master_write_16 $jtag_master_1 0x20 0x2000

21. A*ter the #al"e is change! s"ccess*"lly) watch the LCD !isplay. The histogram changes slower than pre#io"sly. ig"re 58 shows the transcript *rom this interacti#e session &i$ure /: Exa*ple Transcript

22. Close this instance o* $ystem Console.

25. Clic Syste* ,onsole on the Tools men" to reopen system console.

26. To r"n the das4board_exa*ple.tcl script 9le) type the *ollowing comman! source dashboard_example.tcl.

ig"re 5: shows the !ashboar! create! by this script. &i$ure /7: sys #as4board Exa*ple

 The das4board_exa*ple.tcl 9le rea!s bac #al"es o* registers liste! in Tables :%10. or

18 ban!s) the !ashboar! !isplays 18 bars accor!ing to the register #al"e o* each ban!.

 The real%time register #al"es in

)

) an!

 are !isplaye! in

real ti*e %alue gro"p. The !ashboar! recor!s an! !isplays the maximal #al"es in the

*axi*al %alue gro"p. Clic reset *axi*al to reset history res"lt an! restart recor!ing.

 The !ashboar! !isplays the register #al"es in hex *ormat. Khen

 is bigger

then 60) the LED behin! lights in re!. This warns yo" that the parameter in the !esign is

not s"itable. ;o" can complete the *ollowing steps to learn more abo"t how this wors.

1. Close $ystem Console.

2. 's the Q"art"s && ,rogrammer to !ownloa! the sys_lab_*sb8.sof  9le to the =EE>. 5. 4n the Tools men") clic) Syste* ,onsole.