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HSP051-4M10. 4-line ESD protection for high speed lines. Applications. Description. Features. Benefits. Complies with following standards

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This is information on a product in full production.

November 2014 DocID024952 Rev 4 1/12

HSP051-4M10

4-line ESD protection for high speed lines

Datasheet

production data

Figure 1. Functional schematic (top view)

Features

• Flow-through routing to keep signal integrity

• Ultralarge bandwidth: 10 GHz

• Ultralow capacitance:

– 0.2 pF (I/O to I/O) – 0.35 pF (I/O to GND)

• Very Low dynamic resistance: 0.48 Ω

• 100 Ω differential impedance

• Low leakage current: 100 nA at 25 °C

• Extended operating junction temperature range: -40 °C to 150 °C

• Thin package: 0.5 mm max.

• RoHS compliant

Benefits

• High ESD protection level

• High integration

• Suitable for high density boards

Complies with following standards

• MIL-STD 883G Method 3015-7 Class 3B:

– 8 kV

• IEC 61000-4-2 level 4:

– 8 kV (contact discharge) – 15 kV (air discharge)

Applications

The HSP051-4M10 is designed to protect against electrostatic discharge on sub micron technology circuits driving:

• HDMI 2.0 and 1.4

• USB 3.1 and USB3.0

• Digital Video Interface

• Display Port

• Serial ATA

Description

The HSP051-4M10 is a 4-channel ESD array with a rail to rail architecture designed specifically for the protection of high speed differential lines.

The ultralow variation of the capacitance ensures very low influence on signal-skew. The large bandwidth make it compatible with HDMI2.0.

4k/2k (=5.94 Gbps) and USB3.1 (= 10 Gbps).

The device is packaged in µQFN 2.5 mm x 1 mm with a 500 µm pitch.

µQFN-10L (2.5 X 1.0 mm) HSP051-4M10

I/O 1

I/O 2

GND

I/O 3

I/O 4

Internally not connected

GND

Internally not connected 1

2

4

5 6

8 9 10

3

7

www.st.com

This datasheet has been downloaded fromhttp://www.digchip.comat thispage

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Characteristics HSP051-4M10

1 Characteristics

Table 1. Absolute maximum ratings Tamb = 25 °C

Symbol Parameter Value Unit

VPP Peak pulse voltage IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge

8

25 kV

Tj Operating junction temperature range -40 to +150 °C

Tstg Storage temperature range -65 to +150 °C

TL Maximum lead temperature for soldering during 10 s 260 °C

Table 2. Electrical characteristics Tamb = 25 °C

Symbol Test conditions Min. Typ. Max. Unit

VBR IR = 1 mA 4.5 5.8 V

IRM VRM = 3.6 V 10 100 nA

VCL IPP = 1 A, 8/20 µs 10 V

VCL IEC 61000-4-2, +8 kV contact (IPP = 16 A), measured at 30 ns 13 V

Rd Dynamic resistance, pulse duration 100 ns I/O to GND 0.48

GND to I/O 0.96 Ω

CI/O - I/O VI/O = 0 V, F = 200 MHz to 9 GHz 0.2 0.3 pF

CI/O - GND VI/O = 0 V F = 200 MHz to 2.5 GHz 0.4 0.55 pF

F = 2.5 GHz to 9 GHz 0.35 0.45 pF

fC -3dB 10 GHz

Zdiff Time domain reflectometry: tr = 200 ps (10 - 90%), Z0 = 100 Ω 85 100 115 Ω

Figure 2. Leakage current versus junction temperature (typical values)

Figure 3. S21 attenuation measurement

IR (nA)

1 10 100

25 50 75 100 125 150

Tj (°C)

S21 (db)

100k 1M 10M 100M 1G 10G

-3 -2.5 -2 -1.5 -1 -0.5 0

0 V 3.6 V 2.5 V

F (Hz)

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DocID024952 Rev 4 3/12

HSP051-4M10 Characteristics

12

Figure 4. Eye diagram - HDMI mask at 3.35 Gbps per channel(1)(without HSP051-4M10)

Figure 5. Eye diagram - HDMI mask at 3.35 Gbps per channel(1) (with HSP051-4M10)

1. HDMI specification conditions. This information can be provided for other applications. Please contact your local ST office.

Figure 6. Eye diagram - HDMI 2.0 mask at 5.94 Gbps per channel (without HSP051-4M10)

Figure 7. Eye diagram - HDMI 2.0 mask at 5.94 Gbps per channel (with HSP051-4M10)

Figure 8. Eye diagram - USB 3.0 mask at 5.0 Gbps per channel (without HSP051-4M10)

Figure 9. Eye diagram - USB 3.0 mask at 5.0 Gbps per channel (with HSP051-4M10)

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Characteristics HSP051-4M10

Figure 10. Eye diagram - USB 3.1 mask at 10.0 Gbps per channel (without HSP051-4M10)

Figure 11. Eye diagram - USB 3.1 mask at 10.0 Gbps per channel (with HSP051-4M10)

Figure 12. ESD response to IEC 61000-4-2 (+8 kV contact discharge)

Figure 13. ESD response to IEC 61000-4- 2 (-8 kV contact discharge)

50 V / Div

20 ns / Div V : Peak clamping voltageCL

V :clamping voltage at 30 nsCL

V :clamping voltage at 60 nsCL

V :clamping voltage at 100 nsCL

1 2 3 4

10 V 11 V 4

13 V 3 2 184 V 1

50 V / Div

-147 V

1 2 -13 V

-5 V 3

4 -2 V

V : Peak clamping voltageCL

V :clamping voltage @ 30 nsCL

V :clamping voltage @ 60 nsCL

V :clamping voltage @ 100 nsCL

12 34

20 ns / Div

Figure 14. TLP measurement (pulse duration 100 ns)

Figure 15. TDR measurement IPP (A)

0 2 4 6 8 10 12 14 16 18 20

0 5 10 15 20

VCL (V) GND to I/O

I/O to GND

(5)

DocID024952 Rev 4 5/12

HSP051-4M10 Package information

12

2 Package information

• Epoxy meets UL94, V0

• Lead-free packages

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Figure 16. µQFN-10L dimension definitions

A A1

A2 PIN 1 ID L

R 0.125 D b1

E

e b 1

10 6

5

Seating plane

(6)

Package information HSP051-4M10

Table 3. µQFN-10L dimension values

Ref.

Dimensions

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.40 0.47 0.50 0.018 0.018 0.020

A1 0.00 0.00 0.05 0.00 0.000 0.002

A2 0.13 0.005

b 0.15 0.20 0.25 0.006 0.008 0.009

b1 0.35 0.40 0.45 0.014 0.016 0.041

D 2.40 2.50 2.60 0.094 0.098 0.102

E 0.90 1.00 1.10 0.035 0.039 0.043

e 0.50 0.206

L 0.33 0.38 0.43 0.012 0.015 0.017

aaa 0.08 0.003

bbb 0.10 0.004

Figure 17. Footprint recommendations (dimensions in mm)

Figure 18. Marking

0.20 0.40 0.50

1.40

2.20

0.58 0.58

1.40

0.40 0.20

2.20 0.50

H 1 M

(7)

DocID024952 Rev 4 7/12

HSP051-4M10 Package information

12

Figure 19. µQFN-10L tape and reel specification

Dot identifying Pin A1 location

User direction of unreeling All dimensions are typical values in mm

4.0

4.0 2.0

8.0 1.755.5

Ø 1.55

0.55

1.35 0.25

2.75 H1M H1M H1M

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Recommendation on PCB assembly HSP051-4M10

3 Recommendation on PCB assembly

Figure 20. Recommended stencil window position

3.1 Solder paste

1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004.

2. “No clean” solder paste recommended.

3. Offers a high tack force to resist component displacement during PCB movement.

4. Use solder paste with fine particles: powder particle size 20-45 µm.

3.2 Placement

1. Manual positioning is not recommended.

2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering.

3. Standard tolerance of ± 0.05 mm is recommended.

4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force

0.55

1.37

0.38 0.19

2.19 0.50

0.55 0.27

All dimensions are in mm Stencil thisckness 100 µm

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DocID024952 Rev 4 9/12

HSP051-4M10 Recommendation on PCB assembly

12

can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.

5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.

6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.

3.3 PCB design

1. To control the solder paste amount, the closed via is recommended instead of open vias.

2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by

asymmetrical solder paste amount due to the solder flow away.

Figure 21. Printed circuit board layout recommendations

Via to GND Via to

GND

500 µm

Footprint pad PCB tracks

1

5 6

10

(10)

Recommendation on PCB assembly HSP051-4M10

3.4 Reflow profile

Figure 22. ST ECOPACK® recommended soldering reflow profile for PCB mounting

Note: Minimize air convection currents in the reflow oven to avoid component movement.

Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020.

250

0 50 100 150 200

240 210 180 150 120 90 60

30 270 300

-6 °C/s 240-245 °C

2 - 3 °C/s Temperature (°C)

-2 °C/s

-3 °C/s

Time (s) 0.9 °C/s

60 sec (90 max)

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DocID024952 Rev 4 11/12

HSP051-4M10 Ordering information

12

4 Ordering information

Figure 23. Ordering information scheme

5 Revision history

Table 4. Ordering information

Order code Marking Package Weight Base qty Delivery mode

HSP051-4M10 H1M µQFN-10L 3.27 mg 3000 Tape and reel

HSP 05 1 - 4 M10

High speed line protection Breakdown voltage Version

Number of lines Package µQFN-10L

Table 5. Document revision history

Date Revision Changes

29-Jul-2013 1 Initial release.

15-Oct-2013 2 Updated status to production data.

17-Jun-2014 3 Updated Figure 19.

14-Nov-2014 4 Updated Features, Applications and Description. Updated Table 1 and Table 2. Added Figure 6 to Figure 11.

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HSP051-4M10

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2014 STMicroelectronics – All rights reserved

References

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