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Programming Models for Reconfigurable Application Accelerators

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Figure

Figure 1. Schematics of two generic master-worker accelerators. (a) PCI or PCIe. (b) HyperTransport.
Figure 2. Schematic of a generic message passing accelerator.
Figure 3. Schematic of a generic shared memory accelerator.
Figure 4. Graphs illustrating the scalability of the bandwidth and latency for four interconnect types.
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