VN3205 Quad FET array

VN3205

D2 G2 S2 N/C

D1 S1 G1

D3 G3 S3 N/C

D4 S4 G4

Features

Free from secondary breakdown Low power drive requirement Ease of paralleling

Low C_ISS and fast switching speeds Excellent thermal stability

Integral source-drain diode

High input impedance and high gain

Applications

Power supply circuits

Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.)

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N-Channel Enhancement-Mode

Vertical DMOS FETs

Ordering Information

Device Package Options BVDSS/BVDGS

(V)

R_DS(ON)

max (Ω)

V_GS(th)

max (V)

TO-92 14-Lead_PDIP TO-243AA_(SOT-89) Die*

VN3205 VN3205N3-G VN3205P-G VN3205N8-G VN3205ND 50 0.3 2.4

-G indicates package is RoHS compliant (‘Green’) * MIL visual screening available.

Absolute Maximum Ratings

Parameter Value

Drain-to-source voltage BV_DSS

Drain-to-gate voltage BV_DGS

Gate-to-source voltage ±20V

Operating and storage temperature -55°C to +150°C

Soldering temperature* +300°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.

Pin Configurations

TO-92 (N3) TO-243AA (SOT-89) (N8) GATE

SOURCE DRAIN

GATE

SOURCE DRAIN DRAIN

General Description

This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown.

VN3205

Thermal Characteristics

(A)

ID

(pulsed) (A)

Power Dissipation

@TC = 25OC

(W)

θjc

(O_C/W)

θja

(O_C/W)

IDR†

(A) IDRM(A)

TO-92 1.2 8.0 1.0 125 170 1.2 8.0

14-Lead PDIP 1.5 8.0 3.0† _41.6† _83.3† _{1.5 8.0}

TO-243AA 1.5 8.0 1.6(TA = 25O) 15 78‡ 1.5 8.0

Notes:

* ID (continuous) is limited by max rated TJ, TA = 25OC. † Total for package.

‡ Mounted on FR5 board, 25mm x 25mm x 1.57mm.

Product Markings

TO-92 (N3)

14-Lead PDIP (P)

YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID*

= “Green” Packaging

*May be part of top marking

Top Marking

Bottom Marking YYWW VN3205P

LLLLLLLLLL

CCCCCCCCCCC AAA

YY = Year Sealed WW = Week Sealed

= “Green” Packaging

SiVN 3 2 0 5 Y Y W W

VN2LW W = Code for week sealed _{= “Green” Packaging}

Electrical Characteristics

Sym Parameter Min Typ Max Units Conditions

BV_DSS Drain-to-source breakdown voltage 50 - - V V_GS = 0V, I_D = 10mA

V_GS(th) Gate threshold voltage 0.8 - 2.4 V V_GS = V_DS, I_D = 10mA ΔV_GS(th) Change in V_GS(th) with temperature - -4.3 -5.5 mV/O_{C V}

GS = VDS, ID = 10mA

I_GSS Gate body leakage current - 1.0 100 nA V_GS = ±20V, V_DS = 0V

I_DSS Zero gate voltage drain current

- - 10 µA VGS = 0V,

V_DS = Max Rating

- - 1.0 mA VDS = 0.8 Max Rating,

V_GS = 0V, T_A = 125O_C

I_D(ON) On-state drain current 3.0 14 - A V_GS = 10V, V_DS = 5.0V

R_DS(ON) Static drain-to-source_{on-state resistance}

TO-92 and PDIP - - 0.45

Ω

V_GS = 4.5V, I_D = 1.5A

TO-243AA - - 0.45 V_GS = 4.5V, I_D = 0.75A

TO-92 and PDIP - - 0.3 V_GS = 10V, I_D = 3.0A

TO-243AA - - 0.3 V_GS = 10V, I_D = 1.5A

ΔR_DS(ON) Change in R_DS(ON) with temperature - 0.85 1.2 %/O_{C V}

GS = 10V, ID = 3.0A

G_FS Forward transconductance 1.0 1.5 - mho V_DS = 25V, I_D = 2.0A

TO-243AA (SOT-89) (N8)

Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or

VN3205

Electrical Characteristics

Sym Parameter Min Typ Max Units Conditions

C_ISS Input capacitance - 220 300

pF VVGS_DS = 25V, = 0V, f = 1.0MHz

C_OSS Common source output capacitance - 70 120

C_RSS Reverse transfer capacitance - 20 30

t_d(ON) Turn-on delay time - - 10

ns VI_DDD = 2.0A, = 25V, R_GEN = 10Ω

t_r Rise time - - 15

t_d(OFF) Turn-off delay time - - 25

t_f Fall time - - 25

V_SD Diode forward voltage drop - - 1.6 V V_GS = 0V, I_SD = 1.5A

t_rr Reverse recovery time - 300 - ns V_GS = 0V, I_SD = 1.0A

Notes:

All D.C. parameters 100% tested at 25O_{C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)} All A.C. parameters sample tested.

1. 2.

Switching Waveforms and Test Circuit

90%

10%

90% 90%

10% 10%

PULSE GENERATOR

V_DD R_L

OUTPUT

D.U.T.

t(ON)

td(ON)

t(OFF)

td(OFF)

tr

INPUT INPUT

OUTPUT 10V

VDD

R_GEN

0V 0V

VN3205

Typical Performance Curves

20 16 12 8 4 0

0 1 10 100

10 1.0 0.1 .01 1.0 0.8 0.6 0.4 0.2 0

0.001 0.01 0.1 1.0 10 5 4 3 2 1 0

0 2 4

TA = -55°C

0 10 20 30 40 50

4V 3V

0 2 4 6 8 10

125°C

6 8 10

10V 8V 6V 20 16 12 8 4 0 4V 3V 10V 8V 6V TO-92 (pulsed) P-DIP (pulsed) TO-243AA (DC) TO-92 (DC) P-DIP (DC) VGS VGS

VDS = 25V

TO-243AA TA = 25°C PD = 1.6W

TO-243AA (pulsed)

TC= 25°C TO-92

P_D = 1W T_C = 25°C 25°C

0 50 100 150

2.0 1.6 1.2 0.8 0.4 0 125 75 25 P-DIP TO-243AA (TA = 25° C)

TO-92 3.2

2.8

2.4

Saturation Characteristics

Maximum Rated Safe Operating Area Thermal Response Characteristics

Thermal Resistance (normalized)

Transconductance vs. Drain Current Power Dissipation vs. Case Temperature

Output Characteristics

ID

(amperes)

VDS (volts)

PD

(watts)

T_C (O_C)

I_D (amperes)

ID

(amperes)

V_DS (volts)

ID

(amperes)

GFS

(seimens)

VN3205

Typical Performance Curves

300

0 10 20 30 40

100 400

200

0

0 2 4 6 8 10

10

8

6

4

2

0

-50 0 50 100 150

1.1

1.0

1.0

0.8

0.6

0.4

0.2

0

1.2

1.1

1.0

0.9

0.8

0.7

10

8

6

4

2

0 1 2 3 4 5

-50 0 50 100 150

325 pF VDS= 40V

VDS= 10V

V_GS = 4.5V

VGS = 10V

T = -55°CA

V_DS= 25V

125°C

0 4 8 12 16 20

f = 1MHz

CISS

COSS

CRSS

0.9

215 pF

1.6

1.4

1.2

1.0

0.8

0.6

VGS(th)@ 1mA

25°C

0

RDS(ON) @ 10V, 3A

Gate Drive Dynamic Characteristics

Q_G (nanocoulombs) VGS(th)

(normalized

)

RDS(ON)

(normalized

)

V_(th) and R_DS Variation with Temperature On-Resistance vs. Drain Current BV_DSS Variation with Temperature

BV

DSS

(normalized)

Transfer Characteristics

Capacitance vs. Drain-to-Source Voltage

C (picofarads

)

I_D (amperes) T_J (O_C)

RDSS(ON

)

(ohms)

ID

(amperes

)

V_{GS (volts)}

V_DS (volts)

VGS

(volts)

VN3205

3-Lead TO-92 Package Outline (N3)

Symbol A b c D E E1 e e1 L

Dimensions (inches)

MIN .170 .014† _.014† _{.175 .125 .080 .095 .045 .500}

NOM - - -

-MAX .210 .022† _.022† _{.205 .165 .105 .105 .055 .610*}

JEDEC Registration TO-92.

* This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale.

Supertex Doc.#: DSPD-3TO92N3, Version E041009.

Seating Plane

1

2

3

Front View

Side View

Bottom View

E1 E

D

e1

L

e

c 1 2 3

b

VN3205

3-Lead TO-243AA (SOT-89) Package Outline (N8)

Symbol A b b1 C D D1 E E1 e e1 H L

Dimensions (mm)

MIN 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.00†

1.50

BSC 3.00BSC

3.94 0.89

NOM - - -

-MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 4.25 1.20

JEDEC Registration TO-243, Variation AA, Issue C, July 1986. † This dimension differs from the JEDEC drawing

Drawings not to scale.

Supertex Doc. #: DSPD-3TO243AAN8, Version E051509.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.

VN3205

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)

Symbol A A1 A2 b b1 D D1 E E1 e eA eB L

Dimension (inches)

MIN .130* .015 .115 .014 .045 .735 .065† _.290† _.240

.100

BSC BSC.300

.300* .115

NOM - - .130 .018 .060 .750 - .310 .250 - .130

MAX .210 .035* .195 .023† _{.070 .810}† _{.085* .325 .280 .430 .150}

JEDEC Registration MS-001, Variation AA, Issue D, June, 1993. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale.

Supertex Doc. #: DSPD-14DIPP, Version B041009. Note:

A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.

1.

Note 1 (Index Area)

14

1

D

L A1

A A2 Seating_Plane

e

E1

D1 D1

E

A

A

Side View

Top View

View A - A

eA eB

b b1

View B

View B

14-Lead PDIP (.300in Row Spacing) Package Outline (P)