Nanoelectronic COupled problems solutions - nanoCOPS: modelling, multirate, model order reduction, uncertainty quantification, fast fault simulation

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ter Maten et al.Journal of Mathematics in Industry (2017) 7:2 DOI 10.1186/s13362-016-0025-5

E S S AY

Open Access

Nanoelectronic COupled problems

solutions - nanoCOPS: modelling, multirate,

model order reduction, uncertainty

quantiﬁcation, fast fault simulation

E Jan W ter Maten

1*

_{, Piotr A Putek}

1,2

_{, Michael Günther}

1

_{, Roland Pulch}

2

_{, Caren Tischendorf}

3

_,

Christian Strohm

3

_{, Wim Schoenmaker}

4

_{, Peter Meuris}

4

_{, Bart De Smedt}

4

_{, Peter Benner}

5

_{, Lihong Feng}

5

_,

Nicodemus Banagaaya

5

_{, Yao Yue}

5

_{, Rick Janssen}

6

_{, Jos J Dohmen}

6

_{, Bratislav Tasi´c}

6

_{, Frederik Deleu}

7

_,

Renaud Gillon

7

_{, Aarnout Wieers}

7

_{, Hans-Georg Brachtendorf}

8

_{, Kai Bittner}

8

_{, Tomáš Kratochvíl}

9

_{, Jiˇrí Petˇrzela}

9

_,

Roman Sotner

9

_{, Tomáš Götthans}

9

_{, Jiˇrí Dˇrínovský}

9

_{, Sebastian Schöps}

10

_{, David J Duque Guerra}

10

_,

Thorben Casper

10

_{, Herbert De Gersem}

10

_{, Ulrich Römer}

10

_{, Pascal Reynier}

11

_{, Patrice Barroul}

11

_,

Denis Masliah

11

_{and Benoît Rousseau}

11

*_{Correspondence:}

[email protected] 1_{Bergische Universität Wuppertal,} Gauß-Straße 20, Wuppertal, 42119, Germany

Full list of author information is available at the end of the article

Abstract

The FP7 project nanoCOPS derives new methods for simulation during development of designs of integrated products. It covers advanced simulation techniques for electromagnetics with feedback couplings to electronic circuits, heat and stress. It is inspired by interest from semiconductor industry and by a simulation tool vendor in electronic design automation. The project is on-going and the paper presents the outcomes achieved after the ﬁrst half of the project duration.

Keywords: multirate; model order reduction; co-simulation; uncertainty quantiﬁcation; power-MOS devices; RF-circuitry; bond wires; coupled problems; multiphysics; fault simulation

1 Introduction

Designs in nanoelectronics often lead to large-size simulation problems and include strong feedback couplings. Industry demands the provisions of variability to guarantee quality and yield. It also requires the incorporation of higher abstraction levels to allow for sys-tem simulation in order to shorten the design cycles, while at the same time preserving accuracy. The nanoCOPS FP project addresses the simulation of two technically and commercially important problem classes identiﬁed by our industrial partners (NXP Semi-conductors, ON Semiconductor, ACCO Semiconductor, and MAGWEL):

• Power-MOS devices, with applications in energy harvesting, that involve couplings between electromagnetics (EM), heat and stress, and

• RF-circuitryin wireless communication, which involves EM-circuit-heat coupling and multirate behaviour, together with analogue-digital signals.

To meet market demands, the scientiﬁc challenges are to:

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ter Maten et al.Journal of Mathematics in Industry (2017) 7:2 Page 2 of 19

• create eﬃcient and robust simulation techniques for strongly coupled systems, that exploit the diﬀerent dynamics of sub-systems within multiphysics problems and that allow designers to predict reliability and ageing;

• include a variability capability such that robust design and optimization, worst case analysis, and yield estimation with tiny failure probabilities are possible (including large deviations like -sigma);

• reduce the complexity of the sub-systems while ensuring that the operational and coupling parameters can still be varied and that the reduced models oﬀer higher abstraction models that are eﬃcient to simulate.

Achieving solutions to these challenges has considerable industrial impact. The overall

objectiveof nanoCOPS is to advance a methodology for circuit-and-system-level mod-elling and simulation based on best practice rules to deal with coupled electromagnetic

ﬁeld-circuit-heat problemsas well as coupled electro-thermal-stress problems that

emerge in nanoelectronic designs. The new methods developed are robust and allow for strong feedback coupling when integrating systems to increase the performance of both existing devices and when integrating systems to produce new devices.

First outcomes have been reported in [, ]. The project is on-going and the paper presents the outcomes achieved after the ﬁrst half of the project duration. Recently, at the DATE- conference in Dresden, Germany, we gave dedicated presentations to de-signers and to engineers with backgrounds in mathematics and in electronics [–]. On the project website http://www.fp-nanocops.eu/ special videos have been made available. Here also more publications can be found. The current paper addresses mathematicians and points out how mathematics as essential ingredient for innovation is transfered for successful use in industry.

With the new techniques it is possible to eﬃciently analyze the eﬀects due to variability. Our methods are designed to solve reliability questions resulting from

manufacturabil-ity. They facilitate robust design as well as enable worst case analysis. They can also be used to study eﬀects due to ageing. Ageing causes variations in parameters over a long-term period, which cannot be predicted exactly and thus are typically uncertain. The chal-lenges for an Integrated Circuit (IC) are that each device has its own electrical and thermal conditions, which are changing over time (due to ageing, for example). Here, each device has its own required life-time.

Novel Model Order Reduction techniques, developed here for the fast repeated simula-tion of the coupled problems under considerasimula-tion, are applicable to both coupled systems and parameterized sub-systems. As such they are an essential ingredient for the Uncer-tainty Quantiﬁcation.

In summary, our solutions are

• advanced co-simulation/multirate/monolithic techniques, combined with envelope/wavelet approaches;

• new generalized techniques in Uncertainty Quantiﬁcation (UQ) for coupled problems, tuned to the statistical demands from manufacturability;

• enhanced, parametric Model Order Reduction techniques for coupled problems and for UQ.

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Table 1 Partners in nanoCOPS

Abbr. Partner

BUW Bergische Universität Wuppertal, Germany (coordinator) HUB Humboldt Unversität zu Berlin, Germany

TUD Technische Universität Darmstadt, Germany UGW Ernst-Moritz-Arndt-Universität Greifswald, Germany

FHO FH OÖ Forschungs- und Entwicklungs GmbH, Hagenberg im Mühlkreis, Upper Austria, Austria KUL Katholieke Universiteit Leuven, Belgium

BUT Vysoké u˘cení technické v Brn ˘e, Brno University of Technology, Czech Republic MPG Max Planck Institute for Dynamics of Complex Technical Systems, Magdeburg, Germany NXP NXP Semiconductors Netherland B.V., Eindhoven, The Netherlands

ONN ON Semiconductor Belgium, Oudenaarde, Belgium MAG MAGWEL NV, Leuven, Belgium

ACC ACCO Semiconductor, Louveciennes, France

measurements and supply material data as well as process data. A thorough comparison to

measurementson real devices is being made to demonstrate the industrial applicability. Our consortium brings together extensive R&D experience in nanoelectronic IC simu-lation and complementary areas of expertise. It includes seven universities, one research institute, two large-scale semiconductor companies, and two SMEs, see Table .

2 Progress and results

In this section we give an impression of outcomes achieved in the ﬁrst half of the project duration. We refer with the abbreviations in Table  to the various project partners.

2.1 Simulation environment

Electronic devices consist of a large number of components. Many parts are accurately described by a circuit model, whereas semiconductor parts and configurations suffering from electromagnetic interference necessitate the use of field models. The overall be-haviour of the device needs to be simulated by a field-circuit coupled method. Improve-ments on such coupled techniques indirectly lead to more reliable and better integrated devices. In order to be able to incorporate the mutual electromagnetic influence of neigh-boring elements (e.g., cross talking), one needs refined models based on a sufficiently exact discretization of the full Maxwell equations. An interface model for such refined models was derived that can be used for lumped circuit net lists.

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Figure 1 Coupled modelling.Set up for modelling coupled problems involving electromagnetics and circuit equations. Emphasis was made to cast outcomes in terms of Diﬀerential-Algebraic Equations.

2.2 Bondwire modelling and simulation

Nowadays integrated circuits (ICs) are important components of daily life. Moreover, the ever tightening specifications imposed on modern integrated circuits (ICs) by the semiconductor roadmap demand more energy-efficient chips which become smaller and smaller in size. Bond-wires are commonly used to connect the chip and the pins during device assembling. These wires are heated up due to Joule effects and their temperature. Figure  shows a diagram of a classic IC lead-frame package. TUD and ONN have focused an improved electro-thermal formula that is the basis for a bondwire calculator for ONN []. Bondwire temperature can increase substantially since the electric power is supplied through the wires. If the wires cannot properly dissipate this power, then permanent dam-age will occur to the wires and surrounding material. A mathematical formula has been developed that improves the prediction of this heating compared to known models from literature [].

Figure  depicts a simpliﬁed thermal problem upon which the model is built. The rectan-gular shape of the package compound is retained and suitable boundary conditions (BCs) are used; () adiabatic on the rightmost wall except on the wire portion. This facilitates the inclusion of the lead into the model; () iso-thermal on the leftmost and bottom walls amounting to the chip and die-attach temperatures; () convective on lateral and upper walls; () thermal radiation on the wire surface. The temperature dependence of the wire’s thermal and electrical conductivities is also included. The heat equation is solved by means of anad-hoclinearization which involves the compound heat equation and its heat kernel [], viz.

Tw(y,t)∼=To+

ακθw(y,t) +  ακ

– 

ακ

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Figure 2 Coupled simulation.Set up for simulating coupled problems involving electromagnetics and circuit equations. Here there is integration between a circuit simulator (MECS) and an EM-solver. Note that the MAGWEL software provides contributions to speciﬁc equations as well as associated Jacobian values.

Figure 3 Bond wire.Classic IC lead-frame package.

Figure 4 Bond wire.Bond-wire heat transfer problem.

Above,Twis the wire temperature,Tois the reference (ambient) temperature,ακ is the

temperature coeﬃcient of the wire thermal conductivity, andθwis an auxiliary variable.

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esti-ter Maten et al.Journal of Mathematics in Industry (2017) 7:2 Page 6 of 19

Figure 5 Bond wire.Au-wire current capacities for several diameters and a ﬁxed length. The plotted temperature is at the wire mid-point, where the hottest point is expected.

mated current capacity (temperature vs current amplitude) for a gold wire after  ms. The formula retains important geometrical parameters deﬁning the package, which adds high ﬂexibility. This reduces the over-design of the wires during fabrication. The evaluation of this formula is computationally inexpensive such that time-consuming D simulation can be avoided. However, a coupling of the bondwire model to a D simulator is necessary if the integration in the overall system behaviour should be simulated. Thus, TUD also implemented a nonlinear in-house simulation code based on the Finite Integration Tech-nique (FIT) to analyze the coupling before transferring the concept to partner MAG [].

ONNaims to use the algorithm within a GUI (Graphical User Interface).

ONNand BUT made measurements of DC and dynamical fusing of bondwires [].

ONNfabricated test chips (SOIC package so far), where the individual bondwires with diﬀerent lengths, diameters and materials have been encapsulated. BUT prepared a com-plete methodology and experimental setup to do such investigations.

The setup (hardware tester and MATLAB GUI) allows measurements of all six bond-wires in one IC package. The tester consists of the  independent channels, the  driving stages, the  Kelvin probe sensing stages, the demultiplexing core for the driving stages (speciﬁcation of address of the bondwire) and the multiplexing core for the Kelvin probe sensing stages.

The block structure, the single channel operation and photographs of the ﬁnal hardware solution are shown in Figure , Figure  and Figure . The frequency limitation of the measurement setup is about  kHz (limits of the used MOS power-switches and PCI card). The software part of the project consists of two executable MATLAB scripts with a GUI. MATLAB software is also used for the generation of testing sequences and signals that drive the tester. Finally, the measurements have been used to validate the bondwire formula.

2.3 Electro-thermal coupled simulation

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large-ter Maten et al.Journal of Mathematics in Industry (2017) 7:2 Page 7 of 19

Figure 6 Bond wire.Final hardware solution of the bondwire tester prototype: overall block structure.

scale (millimeter) structures and the small-scale (sub-micron) of the finger architecture in a single simulation. The computation deals with the coupling of the electrical response and with the thermal response in first-principle field solving. Figure  illustrates today’s capabilities [].

2.4 Multirate simulations

In coupled problems one often encounters multiscale differences (in space) and large vari-ations in dynamics in time-domain: multirate effects []. In this book especially partitions in space with different dynamics lead to couplings between subsets of DAEs. A careful formulation of the coupling is key in being able to guarantee convergent dynamical itera-tions in a co-simulation. In [] the partition between physical quantities (electromagnet-ics, heat) was exploited to study this convergence.

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Figure 7 Bond wire.Final hardware solution of the bondwire tester prototype: single channel principle.

is a severe bottleneck for PLL simulation and for the multirate technique in general. In de-riving Figure , adaptive methods were employed for the diﬀerent stages of the divider. Table  shows the drastic improvement of the run time using adaptivity. No commercial circuit simulator provides this facility yet.

2.5 Parametric model order reduction

MPGand MAG developed efficient parametric/parameterized Model Order Reduction (pMOR) methods and techniques for fast simulation of electro-thermal coupled models [, ] and for fast Uncertainty Quantification [] of nanoelectronic, electro-thermal models with random variables or stochastic processes. Given the system matrices at dif-ferent values of the parameters or realizations of random variables, we extract system ma-trices which are independent of the parameters (random variables), so that parametric models can be constructed, and the parameters (random variables) symbolically appear in the model. Reduced-order models of the large-scale parametric models are obtained us-ing parametric model order reduction techniques. For general complex geometries, like in Figure , an accurate, physical model in the form of heat transfer partial differential equations is required. The electrical transport is controlled by Ohm’s law and the current continuity equation in conductive material

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Figure 8 Bond wire.Final hardware solution of the bondwire tester prototype: ﬁnal version of the PCB.

Figure 9 Power MOS transistor.Analysis of a power MOS (left ﬁgure) resulting into an asymmetric current density due to thermally induced conductance variations in the metallic interconnect (right ﬁgure).

The generated-energy transport is controlled by Joule’s law

∂U

∂t = –∇ ·Q+, Q= –κ(T)∇T, U=CV

T–T∗. () Of particular interest is the local heat generation, which is given by

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Figure 10 Divider block diagram.A divider block diagram for a PLL (phase lock loop) in the 5.6GHz ISM band (industrial, scientiﬁc and medical (ISM) radio band).

Figure 11 Multirate solution.The solutions show time-varying multirate behaviour, which was eﬃciently solved by the implementation of FHO.

Table 2 Performance summary multirate simulation

Single grid Multiple grids

Number of equations 130,000 85,000 Nonzeros in Jacobian 5×106 _2.5_×₁₀6 Assembly of linear system 4 s 2 s

Linear solve 8 s 4 s

Envelope analysis 5 h 37 min

Figure 12 A thermal package model(provided by MAG).

Hereκ(T) is the heat diﬀusion,CVis the constant-volume heat capacitance of the material,

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large-ter Maten et al.Journal of Mathematics in Industry (2017) 7:2 Page 11 of 19

scale system of ODEs in the form of

Edx(t)

dt =Ax(t) +x(t)

T_F_x₍_t_{) +}_Bu₍_t_), _()

where xis the state vector including the nodal voltages and nodal temperatures vary-ing with time. The tensor F∈Rn×n×n_{represents the non-linear character of the heat}

source. Roughly speaking,Fcan be considered as a D array ofnmatrices. Each matrix is inRn×n_{. The matrix}_E_∈_Rn×n_{is a capacity matrix for both the electrical and the}

ther-mal part, and the matrixA∈Rn×n_{is the conductivity matrix for both the electrical and}

the thermal part. Linear parametric models in state-space-form were constructed based on the discrete data provided by MAG, resulting from a ﬁnite-integration technique (FIT). As an example we consider a parametric thermal package model, see Figure . When con-sidering meshes that are topologically equivalent for diﬀerent package thicknessesp, the parametric dependence of the matrices as well as the matrices in the tensorF will take the form as

M(p) =M+pM+



pM. ()

The second term in () originates from the linear dependence of dual areas corresponding to the cell edges perpendicular to the thickness, whereas the third term originates from dual areas associated to cell edges tangential to the thickness orientation.

If the parameterpsymbolically appears in the model, the system in () becomes a para-metric model,

E(p)dx(t,p)

dt =A(p)x(t,p) +x(t,p)

T_F₍_p₎_x₍_t_,_p_{) +}_B₍_p₎_u₍_t_), _()

where the matrixE(p),A(p),B(p) and each matrix inF(p) are in the form ofM(p). Some mathematical calculations are needed to extract the parametric system from the system in (). However, the calculations are independent of the dimension of the matrices in (), which makes the calculation very cheap and ﬂexible [].

Using a robust parametric model order reduction algorithm in [], a reduced paramet-ric model () with the same parametparamet-ric structure as the full parametparamet-ric model, in (), but with much fewer equations, has been derived

ˆ

E(p)dz(t,p)

dt =Aˆ(p)z(t,p) +z(t,p)

T_Fˆ₍_p₎_z₍_t_,_p_{) +}_Bˆ₍_p₎_u₍_t_). _()

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Figure 13 Simulation results after Model Order Reduction.Full order model state spacen= 8549, ROM state spacer= 58, amount of inputs 34 and outputs 68. Temperature as computed by the ROM.

Figure 14 Power-MOS device(the back contact is not shown).

an eﬃcient method: BDSM-ET [], which uses the superposition principle to construct a ROM with block-wise sparsity. The size of the ROM isr= , and thus almost two orders of magnitude smaller than the Full Order Model (FOM). A most important feature is that the ROM is also much sparser than the ROM obtained using the standard method. With an error less than –_{, the thermal part of the ROM has been used together with}

Spectre, and validated to be eﬃcient.

In developing pMOR methods for fast UQ of nanoelectronic, electro-thermal models with random variables or stochastic processes, we applied pMOR techniques to a Power-MOS device (Figure ), provided by MAG, and obtained a parametric reduced order model (pROM) that is of high accuracy over a very large parameter range. We have em-bedded the parametric reduced model into the Stochastic Collocation Method [], which proved to be both eﬃcient and accurate.

Figure  displays the Power-MOS chip. Figure  shows the heating of the chip. We built an order- pROM for the order- FOM of the electrical part, and an order- pROM for the order- FOM of the thermal part. Figure  and Figure  depict the evolution of the ‘maximal relative error at the outputs’, which is deﬁned as the maximal relative error at all outputs. When the system starts, the maximal relative error is high because the sys-tem is hardly heated up (exact values close to zero) and the thermal parts are dominated by modelling error and numerical error. However, as time elapses, the maximal relative error goes down to the order of –and therefore, the dominant physical properties are accurately captured over a large parameter range.

2.6 Uncertainty quantiﬁcation

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Figure 15 Power-MOS device.Heat ﬂux density on the back contact at timet= 10–6_s.

Figure 16 Rel. error at source.The evolution of the maximal relative error of the outputs for diﬀerent values of the electrical conductivityσ= 10, 1011S/cm.

Figure 17 Rel. error at back contact.The evolution of the maximal relative error of the outputs for diﬀerent values of the electrical conductivityσ= 10, 1011_S/cm.

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Figure 18 Power transistor.Power Transistor optimized to reduce power hotspots while taking geometrical variations into account.

stochastic Partial Diﬀerential Equations (PDEs). Its solution enables to investigate the propagation of uncertainties through a -D model, which aﬀect yield and performance of a power transistor. In particular as parametersp(ω) = [σ(ω),W(ω),Cυ(ω),VD(ω),VS(ω)]

are taken, in which the conductivity of the Metal layer,σ, the thickness of the Metal,

W, and the thermal capacitance of the Via,Cυ, and the drain and source contacts are

considered, see also Figure . Hereωvaries over some event space and the probability distributions of the parameters are predetermined. The PDEs are equipped with random Dirichlet boundary conditions that describe the potentials at the drain and source pads.

To reduce the current density overshoots in the area of the contact layer of the power device, as basic random-dependent cost functional

F(υ) =w

D

Qe

υ,V(υ)dx+w

hV(υ)dγ, ()

was taken, where the dissipation powerQeis analyzed in the area of Metal layer D⊂R,

and the source voltage termhis represented by the random Dirichlet boundary condition in the area of the source and drain pads⊂R. The variableυis deﬁned asυ= (x,p(ω)), whereas the weightswandwrefer to known a priori information about objectives.

For the robust optimization one considers a PDE-constrained minimization problem

min

υ E

F(υ)+η

VarF(υ), ()

whereη=  was taken. The Stochastic Collocation Method, based on Polynomial Chaos Expansion (PCE) [, ], provided a response surface model to estimate the expectation

E[F(υ)] and the standard deviation√Var[F(υ)]. Combining with a Topological Derivative Method, we could reduce hot spot phenomena in a robust sense, see Figure . The op-timization results for a relevant nanoelectronics problem demonstrate that the proposed method is robust and eﬃcient [].

We ﬁnally remark that our implementations are also able to identify dominant parameter contributions to the variance when varying parameters [].

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Figure 19 Power transistor.The pictures give a temperature distribution in the Metal3 layer and the Contact Layer for the structure after optimization (joint work by UGW, BUW, MAG).

industry because it is much faster than Monte Carlo. Our UQ implementation exploits sparse grid techniques and can easily deal with up to  independent parameters.

2.7 Fast fault simulation

NXP, BUW and TU Eindhoven developed a special algorithm for fast fault simulation in NXP’s in-house circuit simulator Pstar. NXP’s simulator is the best in the world for this functionality [, ]. Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, ‘golden’, design of an electronic cir-cuit. When considering faults from the point of view of parameter variations this is well in the range of large deviations. In [] the faulty elements are represented by adding linear conductivities to the circuit. The approach also works for analyzing the eﬀect of additional linear capacitors. However, the main interest is in adding linear conductivities: thuspuvT_x₍_t_,_p_{), where}_p_{= /}_R_{, with resistance}_R_{, and given vectors}_u_,_v_{, to the system of}

circuit equations of which the solution becomesx(t,p). By fault simulation we simulate all situations: a huge number of new connections of pairs of vectors (u,v) and each with many diﬀerent values ofp, up to the regime of large deviations, for the newly added el-ement and comparing the resultx(t,p) at speciﬁc time points with the ‘golden’ solution

˜

x(t) =x(t, ) of the fault-free circuit, corresponding withp= . If the deviation between

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Figure 20 Fast fault imulation.Speed up in fast fault simulation for the TJA1021 chip.

The results are stored in a database. This database is of help to first externally diag-nose a faulty IC and to identify the candidate circuit submodels where the fault may have happened. After that the IC can be studied further internally. This can help to improve next productions. Moreover, the collection of simulations can also be helpful as a priori check before layouting. NXP can identify locations on a chip that are probably affected by tiny manufacturing accuracies, which case faulty behaviour at predefined time points for measurements.

Inclusion of sensitivity analysis brought speeds up in CPU time of a factor  or more. See Figure  for an indicative result. Later invoking of faults gave an additional order of magnitude in speed up. By this reduction of simulation time candidate faults could be detected that would have been impossible otherwise because of excessive CPU time [].

Note that essentially one is looking to the weak spots in the circuit. In our approach the manufacturing process is the immediate cause of the problem. However it can also show up later, due to effects of ageing of the design, or by stress effects due to heating. It is also related to other network problems, e.g., in analyzing traffic behaviour in a city when suddenly a road is blocked, or when a new connection pops up. Our approach can be extended to energy distribution networks, sewage systems, and even to networks that are not constant of size in time.

This algorithm also oﬀers interesting ingredients to combine with Uncertainty Quan-tiﬁcation.

2.8 Test examples, measurements

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boards. They served for step by step study, for comparison to measurements and for val-idation of the enhanced MAGWEL software, in close cooperation with BUT, NXP and

ONN.

As simple example, we mention here test chips that include passive structures (induc-tances, capaci(induc-tances, baluns, resonators). These structures, that are easily measurable, are used to validate further EM extraction and model reduction. Simulated results are com-pared to measurements, EM solver extraction and then with extraction plus netlist reduc-tion in terms of accuracy, memory usage and time simulareduc-tion.

3 Conclusion

The unique combination of the nanoCOPS consortium allows to already report the fol-lowing intermediate, innovative highlights halfway the project, to which all partners have contributed.

• The coupling interface with the MAGWEL software has been improved, tested and is operational.

• Successful large-scale EM-heat simulation was achieved. • Grid-adaptive multirate circuit simulation was established.

• Model Order Reduction was successfully applied to coupled EM-heat problems. • Accurate bond wire modelling for fast usage at industry was demonstrated and was

validated by measurements.

• Uncertainty Quantiﬁcation was applied to variations of material parameters and geometry and was used in robust topology optimization. Apart from the topics, this at best demonstrates the robustness of the integrated software - to achieve optimization one addresses all parts of the codes.

• Innovative methods for improving yield as well as to identify faults were derived. • Advanced measurements environments have been set up both at academia and at

industry.

• Outcomes have been presented at conferences. Joint papers have been published in various journals.

• Interaction between academia and industrial partners addressed a broad range: test examples, new algorithms, implementations, practical use of new methods, ways to improve measurements.

The focus in the second half of the project is on further validation and demonstra-tion of the methods by applying them to the broad range of IC building blocks. To-gether with the industry partners methodologies are deﬁned how best to use the meth-ods. All three industrial partners started work on reliability and the impact of age-ing. Also steps to yield optimization have been developed. Techniques with adjoint approaches are currently introduced. Also inverse problems are addressed. Presen-tations will be given at SCEE-, Scientiﬁc Computing in Electrical Engineering, http://wwwdev.ricam.oeaw.ac.at/events/conferences/scee/.

Competing interests

The authors declare that they have no competing interests.

Authors’ contributions

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Author details

1_{Bergische Universität Wuppertal, Gauß-Straße 20, Wuppertal, 42119, Germany.}2_{Ernst-Moritz-Arndt-Universität} Greifswald, Walther-Rathenau-Straße 47, Greifswald, 17487, Germany.3_{Humboldt Universität zu Berlin, Unter den} Linden 6, Berlin, 10099, Germany.4_{MAGWEL NV, Vital Decosterstraat 44 bus 27, Leuven, 3000, Belgium.}5_{Max Planck} Institut für Dynamik komplexer technischer Systeme, Sandtorstr. 1, Magdeburg, 39106, Germany. 6_{NXP Semiconductors,} High Tech Campus 46, Eindhoven, 5656 AE, The Netherlands.7_{ON Semiconductor Belgium BVBA, Westerring 15,} Oudenaarde, 9700, Belgium. 8_{Fachhochschule Oberösterreich, Softwarepark 11, Hagenberg im Mühlkreis, 4232, Austria.} 9_{Vysoké u˘cení technické v Brn˘e, Brno University of Technology, Purky ˇnova 464/118, Královo Pole, Brno, 61200, Czech} Republic.10_{Technische Universität Darmstadt, Dolivostraße 15 & Schloßgartenstraße 8, Darmstadt, 64293, Germany.} 11_{ACCO Semiconductor, 36-38 Rue de la Princesse, Louveciennes, 78430, France.}

Acknowledgements

This FP7 Collaborative Project nanoCOPS is supported by the European Union in the FP7-ICT-2013-11 Programme under Grant Agreement Number 619166 (Project nanoCOPS - nanoelectronic COupled Problems Solutions). For further details see http://www.fp7-nanocops.eu/.

Received: 10 February 2016 Accepted: 20 June 2016

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