Lab Report 1

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COURSE ELECTRONICS

DEPARTMENT OF MECHANICAL ENGINEERING FACULTY OF ENGINEERING

CODE KJS 3233

TITLE OF EXPERIMENT COMBINATIONAL LOGIC CIRCUIT

EXPERIMENT NO. 1

NAME OF STUDENT MOHD HADRI ARIF BIN SABAIN

MATRICS NO. 4143004811

LECTURER NAME NUR JULIA NAZIM BULYA NAZIM DATE OF SUBMISSION COURSE LEARNING OUTCOME MARKS COMMENTS 25th APRIL 2017

Attendance Yes/No Marks

Given MarksMax Format

Results Discussion Conclusion

Total

CLO 5: Demonstrate laboratory experiment for digital electronics and microprocessor by using technical skills and engineering tools (PLO10).

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CONTENTS OF TABLE

Table 1: Table of pre-lab answers . 2

Table 2: AND GATE truth table 9

Table 3: OR GATE truth table 9

Table 4: NOT GATE truth table 10

Table 5: NAND GATE truth table 11

Table 6: NOR GATE truth table 11

Table 7: EXCLUSIVE OR GATE truth table 12

Table 8: Truth table for OR GATE with inverter inputs 13 Table 9: Truth table for cascaded 3 -Inputs OR GATE 14 Table 10: Truth table for 3-Input majority GATE 15

Table 11: Result Task (Homework) 17

Table 12: Result Task (Homework) 18

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CONTENTS OF FIGURES

Figure 1:74SL08 CONNECTION ... 3 Figure 2:74LS32 CONNECTION ... 3 Figure 3:74LS04 CONNECTION ... 4 Figure 4:74LS00 CONNECTION ... 5 Figure 5:74LS02 CONNECTION ... 5 Figure 6:74LS86 CONNECTION ... 6

Figure 7: OR GATE WITH INVERTER INPUTS... 7

Figure 8: CASCADED 3-Input OR GATES ... 7

Figure 9: 3-INPUT MAJORITY GATE CIRCUIT ... 8

Figure 10: 74LS08 GATE EXPERIMENT ... 8

Figure 16: OR GATE WITH INVERTER INPUTS... 13

Figure 17: CASCADED 3-INPUT OR GATES ... 14

Figure 18: 3-INPUT MAJORITY GATE CIRCUIT ... 15

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1.0 INTRODUCTION

In this experiment, familiarity with the elementary logic gates and their

usage for designing and implementing logic circuits are introduced. In this

experiment, conventional methods will be used, IC’s will be plugged on

a breadboard and connected with wires. In a binary digital system, infor

mation is represented by the combination of ONE’s and ZERO’s. Each

of these signal levels are indeed two non-overlapping ranges of voltages.

There are two ways to assign the Boolean 0 and 1 values to these

two voltage ranges: positive logic and negative logic interpretation. In

positive logic, the HIGH (H) voltage level is assigned as “1” whereas the

LOW (L) level is assigned as “0”. A logic gate (AND, OR, NAND, etc.)

is defined based on it is input-output characteristic, which is determined

by its internal structure.

2.0 OBJECTIVES

The objectives of this experiment is:

i. Wire up various digital logic gates on a breadboard and examine their

truth tables.

ii. Construct a 3-Input Majority Gate using NAND gates.

3.0 EQUIPMENT/APPARATUS

i. Digital Trainer

ii. Breadboard

iii. Components (74LS00, 74LS04, 74LS08, 74LS10, 74LS32, 74LS86,

74LS02)

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4.0 PRE-LAB DIAGNOSTIC TEST

QUESTION ANSWER

Write the Boolean expression for a

two input AND gate Y=AB

When both inputs are HIGH,

output will be 1-High

Write the Boolean expression

for two-input OR gate Y=A+B

If inputs A and B are both LOW,

output will be 0- Low

Write the Boolean expression for

a two-input NAND gate Y=AB

When both inputs are HIGH,

output from NAND gate will be 0- Low

Write the Boolean expression for a

two-input NOR logic gate Y=A+B

Input A is LOW and input B is HIGH,

output Y of the gate will be 0-Low

When both inputs are LOW,

output Y of the NOR gate will be 1-High Write the Boolean expression for a

two-input XOR gate Y=AB+AB

If both inputs HIGH,

output Y from the XOR gate will be 0- Low Write the Boolean expression for

a three-input XOR gate Y=ABC+ABC+ABC+ABC

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5.0 PROCEDURES 5.1 PART I

5.1.1 74LS08 GATE EXPERIMENT

Figure 1: 74SL08 Connection

1. Observe Figure 1 (marked 74LS08), plug the IC the digital trainer. Connect the INPUT “A”, “B” to Data Switch SW1, SW2. Connect the output “Y” to LED display.

2. Change Data Switches SW1, SW2 to turn the LED light on or off (that means the OUTPUT is “1” or “0”) observe the relationship between input & output, and then record it in Table 2.

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1. Observe Figure 2 (marked 74LS32), plug the IC the digital trainer. Connect the INPUT “A”, “B” to Data Switch SW1, SW2 respectively. Connect the output “Y” to LED display.

2. Change Data Switches SW1, SW2 from “0” to “1” and back to “0”, then observe the input and output situations, record them in Table 3.

Figure 3: 74LS04 Connection

1. Referring to Figure 3, which is marked 74LS04, plug this IC in the breadboard of digital trainer.

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2. Change Data Switches SW1, SW2 to turn the LED light on or off (that means the OUTPUT is “1” or “0”, observe the relationship between input and output, and then record it in Table 5.

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5.2 PART II

5.2.1 OR GATE WITH INVERTER INPUTS

Figure 7: OR Gate With Inverter Inputs

Prepare a circuit schematic diagram of the circuit shown in Figure 7. The two inputs, A and B will connect to toggle switches and the output F will connect to an LED on the digital trainer.

5.2.2 CASCADED 3-INPUT OR GATES

Figure 8: Cascaded 3-Input OR Gates

Prepare a circuit schematic diagram of the circuit shown in Figure 8. The three input, A, B and C will connect to toggle switches and output F will connect to an LED on the digital trainer. Complete the truth table.

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5.3 PART III

5.3.1 3-INPUT MAJORITY GATE CIRCUIT

Figure 9: 3-Input Majority Gate Circuit

A majority gate is a digital circuit whose output is equal to 1 if the majority of input are 1’s. The output is 0 otherwise. Prepare a circuit schematic diagram of 3-input majority gate circuit shown in Figure 4a. The three inputs, A, B and C will connect to toggle switches and the output F will connect to an LED on the digital trainer. Complete the truth table. (For Triple NAND Gate refer to appendix.)

6.0 RESULTS 6.1 PART I

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Boolean Expression: Y =AB

Table 2: AND Gate Truth Table

6.1.2 74LS32 GATE EXPERIMENT

Figure 11: 74LS32 Gate Experiment

Boolean

Expression:

Y

=A+B

Table

3:

OR

Gate

Truth

Table

INPUT A 0 0 1 1 B Y 0 0 0 0 1 1 0 1 OUTPUT INPUT A 0 0 1 1 B Y 0 0 1 1 1 1 0 1 OUTPUT

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Figure 12: 74LS04 Gate Experiment Boolean Expression: Y = A

Table 4: NOT Gate Truth Table

Figure 13: 74LS00 Gate Experiment INPUT A 0 0 Y 0 1 OUTPUT

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Boolean Expression: Y =AB

Table 5: NAND Gate Truth Table

6.1.5 74LS02 GATE EXPERIMENT

Figure 14: 74LS02 Gate Experiment

Boolean Expression: Y =A+B

Table 6: NOR Gate Truth Table INPUT A 0 0 1 1 B Y 0 1 1 1 0 1 0 1 OUTPUT INPUT A 0 0 1 1 B Y 0 1 0 0 0 1 0 1 OUTPUT

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6.1.6 74LS86 GATE EXPERIMENT

Figure 15: 74LS86 Gate Experiment

Boolean Expression: Y=AB+AB

Table 7: EXCLUSIVE OR Gate Truth Table INPUT A 0 0 1 1 B Y 0 0 1 1 0 1 0 1 OUTPUT

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6.2 PART II

6.2.1 OR GATE WITH INVERTER INPUTS

Figure 16: OR GATE WITH INVERTER INPUTS

Table 8: Truth table for OR GATE with inverter inputs INPUT A 0 0 1 1 B Y 0 1 1 1 0 1 0 1 OUTPUT

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6.2.2 CASCADED 3-INPUT OR GATES

Figure 17: Cascaded 3-Input OR Gates

INPUT A 1 0 1 0 1 0 0 B 0 C F 0 1 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 OUTPUT

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6.3 PART III

6.3.1 3-INPUT MAJORITY GATE CIRCUIT

Figure 18: 3-Input Majority Gate Circuit

Table 10: Truth Table For 3-Input Majority Gate INPUT A 1 0 1 0 1 0 1 0 B 0 C F 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 1 1 1 1 OUTPUT

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7.1 RESULT (HOMEWORK) LOGIC FUNCTION INVERTER AND AND TRUTH TABLE A A A B B 0 0 0 0 0 1 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 1 1 OUTPUT OUTPUT OUTPUT CONNECTION FIGURE 17

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7.1.2 RESULT (HOMEWORK) LOGIC FUNCTION NOR XOR TRUTH

TABLE CONNECTION FIGURE

A B 0 0 1 0 1 1 1 0 1 0 0 0 OUTPUT A B 0 0 0 0 1 1 1 0 1 1 1 0 OUTPUT

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8.0 APPENDIX

Lab Report 1

TABLE OF CONTENTS

CONTENTS OF TABLE

CONTENTS OF FIGURES

1.0 INTRODUCTION

In this experiment, familiarity with the elementary logic gates and their

usage for designing and implementing logic circuits are introduced. In this

experiment, conventional methods will be used, IC’s will be plugged on

a breadboard and connected with wires. In a binary digital system, infor

mation is represented by the combination of ONE’s and ZERO’s. Each

of these signal levels are indeed two non-overlapping ranges of voltages.

There are two ways to assign the Boolean 0 and 1 values to these

two voltage ranges: positive logic and negative logic interpretation. In

positive logic, the HIGH (H) voltage level is assigned as “1” whereas the

LOW (L) level is assigned as “0”. A logic gate (AND, OR, NAND, etc.)

is defined based on it is input-output characteristic, which is determined

by its internal structure.

2.0 OBJECTIVES

The objectives of this experiment is:

i. Wire up various digital logic gates on a breadboard and examine their

truth tables.

ii. Construct a 3-Input Majority Gate using NAND gates.

3.0 EQUIPMENT/APPARATUS

i. Digital Trainer

ii. Breadboard

iii. Components (74LS00, 74LS04, 74LS08, 74LS10, 74LS32, 74LS86,

74LS02)

4.0 PRE-LAB DIAGNOSTIC TEST

Boolean Expression: Y =AB

Table 2: AND Gate Truth Table

6.1.2 74LS32 GATE EXPERIMENT

Figure 11: 74LS32 Gate Experiment

Boolean

Expression:

Y

=A+B

Table

3:

OR

Gate

Truth

Table

Boolean Expression: Y =AB

Table 5: NAND Gate Truth Table

6.1.5 74LS02 GATE EXPERIMENT

6.1.6 74LS86 GATE EXPERIMENT