Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and Simulink targeting ASIC/FGPA. Previously Worked as logic design engineer in
RAFAEL-Leshem and Extricom Ltd., on design for XILINX/Altera FPGAs.
Implementing HW/SW Model Based
Design In MATLAB And Simulink
Targeting XILINX Zynq-7000 Soc
Eli Levi , B.Sc.EE. ([email protected])
MATLAB & Simulink Application Engineering
HDL Code Generation and Verification, FPGA workflow Systematics Limited
Agenda:
• Sneak-peek into the Demo
• ZYNQ design challenges
• Making ZYNQ programming easier
• Model-Based Design
• Integrated HW / SW design flow
• Live Demo
Sneak Peek into the Demo
So, what are we going to have by the end of this session?
• An FPGA fabric based shifting L.E.D ‘s, controlled by an Embedded ARM core via the AXI interface
• FPGA In the Loop, Processor in the loop.
Agenda:
• Sneak-peek into the Demo
• Zynq design challenges
• Making Zynq programming easier
• Model-Based Design
• Integrated HW / SW design flow
• Live Demo
Zynq Design Challenge
ARM Processor C-Code Software Interface FPGA HDL Code HardwareZynq Design Challenge - ARM
Properties:
• Typically programmed in C
• Often runs a Linux-based operating system • Well-established workflows exist
Challenges:
• FPGA Designers are not familiar with processor programming • What should run on the processor vs. the FPGA?
ARM Processor
C-Code Software
Zynq Design Challenge - FPGA
FPGA HDL Code Hardware
Properties:
• Typically programmed in VHDL/Verilog • Established workflows exist
Challenges:
• DSP/Processor programmers are not familiar with FPGA Design • What should run on the FPGA vs. the processor?
Zynq Design Challenge - Interface
Interface
Properties:
• Zynq uses “standard” AXI interface between FPGA and ARM
Challenges:
• No established rules for hooking up the interface
Zynq Design Challenge – Solution?
So, how can we address these challenges and get our project onto Zynq quickly?
• Model-Based Design provides a single environment from requirements to prototype
• A guided workflow for hardware and
software development INTEGRATION
IMPLEMENTATION DESIGN T E S T & V E R IFI C A T ION RESEARCH REQUIREMENTS ARM FPGA VHDL, Verilog C, C++ Environment Models Physical Components Algorithms
Agenda:
• Sneak-peek into the Demo
• Zynq design challenges
• Making Zynq programming easier
• Model-Based Design
• Integrated HW / SW design flow
• Live Demo
Integration, Test & Certification
Traditional Design of a HW/SW System
Research & Requirements
Hardware Requirements Design Realization Testing Software Requirements Design Realization Testing The problem:
Model-Based Design
• Automate regression testing
• Detect design errors
• Support certification and standards
• Generate efficient code
• Explore and optimize
implementation tradeoffs
• Model multi-domain systems
• Explore and optimize system behavior in floating point and fixed point
• Collaborate across teams and continents INTEGRATION IMPLEMENTATION DESIGN TE ST & VERIFI CA TI O N RESEARCH REQUIREMENTS ARM FPGA VHDL, Verilog C, C++ Environment Models Physical Components Algorithms
Zynq Design Challenges
• FPGA Designers not familiar with programming processors • DSP/Processor programmers not familiar with FPGAs
• What should run on the FPGA vs. what should run on the ARM?
• No established rules for hooking up the interface between FPGA and ARM processor ARM Processor C-Code Software Interface FPGA HDL Code Hardware
High-Level Zynq Design Flow
User defines partitioning
MathWorks automates code
and interface-model
generation
MathWorks automates the build and download through
the Xilinx tools
INTEGRATION IMPLEMENTATION DESIGN TE ST & VERIFI CA TI O N RESEARCH REQUIREMENTS ARM FPGA VHDL, Verilog C, C++ Environment Models Physical Components Algorithms
Agenda:
• Sneak-peek into the Demo
• Zynq design challenges
• Making Zynq programming easier
• Model-Based Design
• Integrated HW / SW design flow
• Live Demo
Integrated HW / SW design flow
HDL IP Core Generation
MATLAB® andSimulink®
Algorithm and System Design
Simulink Model
SW
HW
Programmable Logic IP Core
Algorithm from MATLAB/ Simulink AXI Lite Accessible Registers AXI4-Stream Video In
AXI4-Stream Video Out
External Ports
HDL IP Core Generation
HDL IP Core Generation
MATLAB® andSimulink®
Algorithm and System Design
Embedded System Integration Zynq Platform FPGA Bitstream Programmable Logic IP Core
Algorithm from MATLAB/ Simulink AXI Lite Accessible Registers AXI4-Stream Video In
AXI4-Stream Video Out
External Ports
Xilinx Embedded System Project
A X I 4 - L i t e Processing System
Programmable Logic IP Core
Algorithm from MATLAB / Simulink AXI Lite Accessible Registers AXI Video DMA
AXI4-Stream Video In
AXI4-Stream Video Out
External Ports Embedded System
Integration
HDL IP Core Generation
MATLAB® andSimulink®
Algorithm and System Design
Embedded System Integration Zynq Platform FPGA Bitstream SW Interface Model Generation SW Build Simulink Model SW HW SW Interface Model SW SW I/O Driver Blocks SW Interface Model Generation
HDL IP Core Generation
MATLAB® andSimulink®
Algorithm and System Design
Embedded System Integration SW Interface Model Generation Zynq Platform SW Build FPGA Bitstream External Mode PIL Real-time Parameter
Tuning and Verification – External Mode
– Processor-in-the-loop
More probe and debug
capability in the future
Zynq HW/SW Co-design Workflow Summary
Embedded System Project Simulink Model
SW HW
Design Generation IP Core
FPGA IP Core Algorithm from MATLAB / Simulink AXI Lite Accessible Registers External Ports A X I 4 - L i t e B u s Processor Em bedded S y st em Int egrat ion FPGA IP Core Algorithm from MATLAB / Simulink AXI Lite Accessible Registers External Ports Generate SW Interface Model SW Interface Model SW SW I / O Driver Blocks FPGA Bitstream SW Build
Agenda:
• Sneak-peek into the Demo
• Zynq design challenges
• Making Zynq programming easier
• Model-Based Design
• Integrated HW / SW design flow
• Live Demo
Questions ?
[email protected]
03-7660111
www.systematics.co.il
Group:
MATLAB & Simulink users in Israel
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