DCT700 ph0

5 5 4 4 3 3 2 2 1 1 D D C C B B A A

1

DCT.SCH. Top level connections

6

DCT700 Phase 0 Main Board Schematic

POR.SCH Power On Reset

Ref

2

APVD

DIGITAL.SCH Hierarchical Grouping

3

QUAKE_RP_DIGITAL.SCH QUAKE_RP Digital I/O

AFE.SCH. Analog front end.

PLATFORM_FLASH & SRAM.SCH

Rev. .00

100

THIS DOCUMENT CONTAINS PROPRIETARY DATA AND IS INTENDED ONLY TO CONVEY INFORMATION TO CUSTOMERS, PROSPRECTIVE CUSMERS, AND VENDORS. IT SHALL NOT BE COPIED, REPRODUCED, COMMUNICATED TO OTHERS, OR USED AS A BASIS FOR THE MANUFACTURE OR SALE OF APPARATUS WITHOUT THE WRITTEN PERMISSION OF GENERAL INSTRUMENT CORPORATION.

REVISION

14

2

2. Each page in the schematics is assigned a set of reference designators (Ref)

11

INCORP

200

DDR_SDRAM.SCH

1100

Revision History

A

SECURITY.SCH MC1.7, Battery, and TVPC

700/800

Initial Proto Rev.

1

NUMBER

.00

900

QUAKE_RP_ANALOG.SCH 7114 Analog I/O

REVISION

.00

.00

DCT700 Phase 0 Title Sheet

B

Sheet

Schematic

8

ECO

1

.00

.00

.00

2

1. These schematics are grouped heirachically by function

A

Notes :

D

.00

.00

Rev.

Description

PCB Requirements

12

Place all terminating resistors as close to source as possible. The series terminating resistors will

have a value of 0, 33, or 51 Ohms.

C

DESCRIPTI

O

N

.00

This reference is the starting designator for all parts on the page

MODIFICATION RECORDS

328-039-001

4

1

1

13

9

4

.00

C

400

7

Table of Contents

VIDEO_AUDIO.SCH Baseband / Remod Output

200/400

300

.00

4

3

D

1

1

10

.00

B

5

.00

REV

.00

3

ANALOG.SCH Hierarchical Analog Grouping

TUNER_UPSTREAM.SCH Tuner, Upstream Amp & Diplexer

500/600

PWR.SCH Power Distribution

REV.1

DMR SD_284 , DMR SD_286 , DMR SD_287, DMR SD_288, DMR SD_289, DMR SD_290, DMR SD_291, DMR SD_292, DMR

_{SD_293, DMR SD_294, DMR BCST_1, DMR BCST_2, DMR SD_295, DMR SD_297}

REV.2

DMR SD_299, DMR SD_301, DMR SD_303, DMR SD_304

REV.3

DMR SD_307-1, DMR SD_311-1, DMR SD_309, DMR SD_312, DMR BCST_3, DMR BCST_4

10V -65% YES YES <1% 10V YES NO -2% -2% Applied Voltage -2% YES 10V Y5V 0805 -3% X5R 1206 X5R 1206 1.2V NO -10% YES 10V X6S 1206 X5R 1206 -10% X7R 1206 -15% 5V NO Y5V 0805 Y5V 0805

For power supply bypass applications (not AC signals).

10V X6S 1206 YES X5R 1206 -15% YES 3.3V X7R 1206 6.3V X6S 0805 YES -28% Y5V 0805 X7R 1206 6.3V X6S 0805 6.3V YES NO -2% 10V YES Cap change at applied voltage. YES 6.3V Voltage Rating Acceptable for use? X7R 1206 -20% 2.5V 10V 6.3V 10V -85% Dielectric Material & Size

Acceptable Dielectric Material for 10 uF Multilayer Chip Capacitors.

10V -75% YES 6.3V <1% 10V

REV.4

DMR SD_317,DS_321,BCST_021,SD_326,SD_330,SD_332,SD_335,SD_341,SD_342,BCST_022

REV.A

Release for mass production(REV.A=REV.4)

A

C03128

2

R e leas e f o r m a ss produc tion of Phas e 1

Matt

Chiang

9-24-03'

Raph Chang

9-24-03'

A A

SCHEMATIC,MAIN,DCT700 P0

Atlanta, Georgia, U.S.A. Taipei, Taiwan R.O.C.

1 14

Friday, September 26, 2003 864684-049

Title

Document Number Rev

Date: Sheet of

File Name DCT_2

5 5 4 4 3 3 2 2 1 1 D D C C B B A A YELLOW - POWER RED - MESSAGE

D4

R15

R16

R17

R18

MIM-5383H4

SFH5110-38

INSTALL INSTALL INSTALL DNI INSTALL DNI DNI DNI

See option

Table 3

Table 3

A

DCT.SCH

Atlanta, Georgia, U.S.A. Taipei, Taiwan R.O.C.

2 14

Friday, September 26, 2003 <Variant Name>

864684-049 Title

Document Number Rev

Date: Sheet of File Name POWER Sheet_05 VDC_IN ANALOG Sheet_04 LINE_OUT_RIGHT LINE_OUT_LEFT COMP_OUT REMOD_OUT CH3/4_SEL DIGITAL Sheet_03 WRPROT_1 WRPROT_3 CH3/4_SEL IR_IN MANF_RXD MANF_TXD MSG_LED PWR_LED HARD_RESETB MSG_LED MSG_LEDB PWR_LED PWR_LEDB DIAG_TXD DIAG_RXD MANF_RXD MANF_TXD HARD_RESETB COMP_OUT LINE_OUT_LEFT LINE_OUT_RIGHT CH3/4_SEL WRPROT_GND IR_IN WRPROT_1 WRPROT_3 D A D D D +3.3V +5V D D D D D D D +5V +3.3V D R12 330_s J4 conn_f_female_007 185243-007-99 1 3 2 TP4 TESTPIN TP10 R18 0_s Q4 2sc2712 1 3 2 TP3 TESTPIN TP5 TESTPIN R6 3.3K_s S1 QUAKE_SHIELD 1 2 3 4 5 6 GN D GN D GN D GN D GN D GN D R11 4.7K_s D4 gp1um281yk 2 1 3 4 5 V CC(G ND) V O UT GND(VCC) MTG1 MTG2 TP6 TESTPIN D2 hlmp_1401 2 1 R17 0_s S T J6 hsp_241v1y 1 3 2 D3 led 2 1 R15 0_s TP7 TESTPIN TP1 TESTPIN R3 100_s TP9 Q1 2sc2712 1 3 2 Q3 2sc2712 1 3 2 TP2 TESTPIN R7 10K_s R16 0_s R10 330_s TP8 J3 conn_power_jack1 1 2 3 C1 0.1U_s R8 1K_s R5 1K_s 2T 1T S J5 hsp_242v2 2 3 1 Q2 2sc2712 1 3 2 R2 3.3K_s R13 4.7K_s R14 4.7K_s D1 mmbd4148 1 3 J1 header_3_pins 1 2 3 R4 1K_s

5 5 4 4 3 3 2 2 1 1 D D C C B B A A A

DIGITAL.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

3 14

Friday, September 26, 2003

C _864684-049

Title

Document Number Rev

Date: Sheet of File Name Size POR Sheet_06 POR_IRQB POR_RESETB HARD_RESETB EJTAG_RESETB DDR_SDRAM_1 Sheet_09 SD_DATA_[15:0] SD_ADDR_[12:0] SD_UDM SD_LDM SD_UDQS_1 SD_LDQS_0 SD_WEB SD_RASB SD_CASB SD_CSB_0 SD_CLK SD_CLKB SD_BA_0 SD_BA_1 SD_CLKE SECURITY_1 Sheet_10 PKT_DATA PKT_SYNC PKT_CLK POR_RAM_ENB SYS_RESETB MC_SPI_CSB WRPROT_1 WRPROT_3 INFO_DATA INFO_SYNC INFO_CLK SRAM_VBATT MC_IRQB SPI_MISO SPI_MOSI MC_CLK27 MC_CLK40 SPI_CLK POR_RESETB

PLATFORM_FLASH & SRAM_1

Sheet_08 EBI_DATA_[15:0] EBI_ADDR_[24:0] EBI_RDB SRAM_VBATT POR_RAM_ENB SYS_RESETB FLASH1_CSB ROM_CSB SRAMLB_CSB SRAMUB_CSB EBI_R/WB SEL_FLASH1/ROMB QUAKE_RP_ DIGITAL_1 Sheet_07 EBI_DATA_[15:0] EBI_ADDR_[24:0] EBI_RDB SD_ADDR_[12:0] SD_DATA_[15:0] SD_UDM SD_LDM SD_UDQS_1 SD_LDQS_0 SD_WEB SD_RASB SD_CASB SD_CSB_0 SD_CLK SD_CLKB SPI_MOSI SPI_CLK MC_SPI_CSB SPI_MISO EJTAG_RESETB POR_RESETB POR_IRQB ROM_CSB FLASH1_CSB SRAMLB_CSB SRAMUB_CSB MANF_RXD MANF_TXD INFO_CLK INFO_DATA INFO_SYNC EBI_R/WB SD_BA_0 SD_BA_1 MC_IRQB IR_IN PKT_CLK PKT_DATA PKT_SYNC MC_CLK27 MC_CLK40 SYS_RESETB CH3/4_SEL MSG_LED PWR_LED SD_CLKE SEL_FLASH1/ROMB POR_RESETB SYS_RESETB SRAM_VBATT POR_RAM_ENB WRPROT_3 WRPROT_1 HARD_RESETB SYS_RESETB SD_CSB_0 EBI_ADDR_[24:0] SPI_MISO SPI_CLK SD_CASB SD_LDM SD_BA_0 SRAMUB_CSB SD_DATA_[15:0] EBI_RDB IR_IN SPI_MOSI CH3/4_SEL EBI_R/WB INFO_SYNC ROM_CSB SD_CLK PWR_LED SYS_RESETB MC_IRQB SD_CLKB EBI_DATA_[15:0] SD_RASB SD_ADDR_[12:0] MC_SPI_CSB SD_CLKE FLASH1_CSB POR_IRQB INFO_CLK SRAMLB_CSB SD_UDM MC_CLK40 MC_CLK27 POR_RESETB MSG_LED SD_BA_1 INFO_DATA EJTAG_RESETB SD_WEB SD_LDQS_0 SD_UDQS_1 SEL_FLASH1/ROMB WRPROT_3 IR_IN WRPROT_1 CH3/4_SEL PWR_LED MSG_LED MANF_RXDMANF_TXD HARD_RESETB

A A B B C C D D E E 4 4 3 3 2 2 1 1 A

ANALOG.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

4 14

Friday, September 26, 2003

C _864684-049

Title

Document Number Rev

Date: Sheet of File Name Size TUNER_UPSTREAM.SCH Sheet_14 TX_DAC+ TX_DAC-TX_OEN US_CTL_DATA US_CTL_CLK US_CTL_CSB TUNER_SDA TUNER_SCLK QAM_IF-OOB_TAP QAM_IF+ QAM_AGCT QUAKE_RP_ANALOG Sheet_11 DIG_COMPOSITE AUDIO_LEFT_POS AUDIO_LEFT_NEG AUDIO_RIGHT_POS AUDIO_RIGHT_NEG OOB_AGC OOB_VCO_POS OOB_VCO_NEG IB_IF_NEG IB_IF_POS OOB_IF_NEG OOB_IF_POS QAM_AGCI TX_DAC+ TX_OEN TX_DAC-US_CTL_DATA US_CTL_CLK US_CTL_CSB TUNER_SDA TUNER_SCLK QAM_AGCT AFE Sheet_13 OOB_AGC QAM_AGCI IB_IF_POS IB_IF_NEG OOB_IF_NEG OOB_VCO_POS OOB_VCO_NEG OOB_IF_POS QAM_IF-OOB_TAP QAM_IF+ VIDEO_AUDIO.SCH Sheet_12 DIG_COMPOSITE COMP_OUT AUDIO_RIGHT_POS LINE_OUT_RIGHT AUDIO_RIGHT_NEG REMOD_OUT AUDIO_LEFT_NEG LINE_OUT_LEFT AUDIO_LEFT_POS CH3/4_SEL OOB_TAP REMOD_OUT COMP_OUT CH3/4_SEL LINE_OUT_LEFT LINE_OUT_RIGHT QAM_IF+ AUDIO_LEFT_POS OOB_IF_NEG DIG_COMPOSITE IB_IF_POS AUDIO_RIGHT_POS AUDIO_LEFT_NEG AUDIO_RIGHT_NEG OOB_AGC OOB_IF_POS OOB_VCO_POS IB_IF_NEG OOB_VCO_NEG TX_DAC-TX_DAC+ US_CTL_CSB TX_OEN QAM_IF-OOB_TAP TUNER_SDA US_CTL_DATA US_CTL_CLK TUNER_SCLK QAM_AGCI QAM_AGCT COMP_OUT LINE_OUT_RIGHT LINE_OUT_LEFT REMOD_OUT CH3/4_SEL

A A B B C C D D E E 4 4 3 3 2 2 1 1 112004-014

+2.5V Voltage Regulator (50 mA nominal)

-5V Charge Pump (20 mA max)

488524-001

+3.4V LDO Voltage Regulator

506626-001 138194-000

Reverse voltage

protection

138194-000

+1.25V DC-DC Converter

1% Low ESR 502130-001

Overcurrent

protection

Low ESR

Input DC Power Filter and

Protection

501238-001

Low ESR 503458-001

Collector tab of 2SD2118

must be heat sinked to

copper on PCB.

VOUT = VFB*(1+R1/R2)

VFB = 1.242V nominal

VOUT = 1.242V*(1 +

1K/47K) = 1.268V

VOUT = VFB*(1+R1/R2)

VFB = 2.5V nominal

VOUT = 2.5V*(1 +

1K/2.8K) = 3.393V

EMI Filter

1%

Surge

Protection

See table page 1. 6.3V X5R 1206 467639-001 See table 1

467639-001 6.3V X5R 1206 See table page 1. 467639-001

6.3V X5R 1206 See table page 1.

See table 1 See table 1

506626-001 1% 1% See table 1

+5V DC-DC Converter

138194-000

Low ESR Low ESR

501238-001 See table 1

VOUT = VFB*(1+R1/R2)

VFB = 1.242V nominal

VOUT = 1.242V*(1 +

10K/3.24K) = 5.075V

C113 C101, C102 C105, C106 United Chemi-Con KMF25VB471M10X16 507629-001 0.19 ohms KZE16VB471M10X12 496616-001 0.053 ohms C121 = 1000pF KZE25VB471M10X16 496616-002 0.038 ohms KMF25VB471M10X16 507629-001 0.19 ohms United Chemi-Con KMF16VB471M10X12 507630-001 0.25 ohms KZE series Do not use. Do not use. United Chemi-Con

KMF16VB471M10X12 507630-001 0.25 ohms C121 = 1000pF KMF25VB471M10X16 507629-001 0.19 ohms C121 = 1000pF

Reference Designator

Vendor and PN Motorola MCN ESR max. at 20 deg C

and 100 kHz

Notes

Table 1

A

PWR.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

5 14

Friday, September 26, 2003

C 864684-049

Title

Document Number Rev

Date: Sheet of File Name Size D +5V +5V D D +12V_UNREG D D D D D D +12V_UNREG +5V +12V_UNREG D +1.2V +12V_UNREG D -5V +2.5V +2.5VREF +3.3V +3.3V D D D +12V_UNREG +5V D D +12V_UNREG D U103F 74vhc14dt 13 12 F100 fuse2a D100 mbrs340 2 1 C103 1000P_s C104 100P_s R110 1K_s C109 10U_c C108 10U_c R106 100K_s R105 17.4K_s 1% C111 1000P_s R114 20_s C110 100P_s Q102 2SD2118 1 4 3 C118 0.1U_s 1 2 D104 1smb20a 2 1 L101 22uh_1_9a + C105 470uf_21 1 2 R111 2.8K_s U103D 74vhc14dt 9 8 R100 1K_s Q101 FDC640P 1 2 3 4 5 6 DRAIN DRAIN GATE SOURCE DRAIN DRAIN R108 1K_s C121 1000P_s Q104 2sa1162 1 2 3 C117 0.1U_s 1 2 C116 10U_c + C106 470uf_21 1 2 R103 10K_s U103B 74vhc14dt 3 4 + C115 100uf_07 1 2 + C113 470uf_22 1 2 Q103 mmbt2222a 1 3 2 R109 20_s R112 100_s R113 0_s C107 1000P_s C122 180P_s L102 32uh_2a D102 mbr0520lt 2 1 U100 LM3485 495633-001-26 1 2 3 4 5 6 7 8 ISENSE GND NC FB ADJ PWRGND PGATE VIN R101 47K_s D105 mbrs340 2 1 U103E 74vhc14dt 11 10 D103 mbr0520lt 2 1 + C102 470uf_21 1 2 C114 0.1U_s R104 3.24K_s U103C 74vhc14dt 5 6 C100 100P_s U101 LM3485 495633-001-26 1 2 3 4 5 6 7 8 ISENSE GND NC FB ADJ PWRGND PGATE VIN D101 mbrs340 2 1 R107 1K_s + C101 470uf_21 1 2 L100 22uh_1_9a C112 0.1U_s R102 17.4K_s 1% U104 TL431CD 6 1 8 3 2 7 C120 1000P_s Q100 FDC640P 1 2 3 4 5 6 DRAIN DRAIN GATE SOURCE DRAIN DRAIN U103A 74vhc14dt 14 7 1 2 VDC_IN

A A B B C C D D E E 4 4 3 3 2 2 1 1 128008-010 1%

3.3V Voltage Monitor

1.2V Voltage Monitor

128008-010

Power UP threshold = 1.125 V nom.

Power DOWN threshold = 1.113 V

nom.

Power UP threshold = 8.536V nom.

Power DOWN threshold = 6.889V nom.

Power UP threshold = 2.989 V nom.

Power DOWN threshold = 2.894 V

nom.

128008-010 1%

1%

DC Input Power Supply Voltage Monitor

128008-010

A

POR.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

6 14

Friday, September 26, 2003

C 864684-049

Title

Document Number Rev

Date: Sheet of File Name Size PG1 +2.5VREF +2.5VREF PG2 +2.5VREF +2.5VREF +12V_UNREG +12V_UNREG D +12V_UNREG +3.3V +1.2V D D +3.3V D +3.3V +2.5VREF D +3.3V D +12V_UNREG -+ U150C LM339AD 9 8 14 3 12 R161 20K_s R165 8.06K_s 1% R153 100K_s -+ U150D LM339AD 11 10 13 3 12 R154 47.5K_s -+ U150B LM339AD 5 4 2 3 12 C150 4700P_s 1 2 D151 bat54alt1 3 2 1 R157 3.3K_s -+ U150A LM339AD 7 6 1 3 12 C151 0.1U_s R162 100K_s R159 3.3K_s U151 TL431CD ₆ 1 8 3 2 7 R151 3.3K_s R164 10K_s 1% R160 3.3K_s R156 10K_s R158 100K_s R155 20K_s D150 bat54alt1 3 2 1 R152 10K_s R166 3.3K_s R163 1K_s R150 10K_s HARD_RESETB EJTAG_RESETB POR_IRQB POR_RESETB

EBI_CSB_6 EBI_CSB_8 EBI_CSB_7

27MHz QUAKE has internal PU

for EXTI[4:0]. QUAKE has internal

PD for GPIO[23:00].

LK_SEL[3:0] are outputs. LK_SEL4 has internal PD.

QUAKE has internal PD for LK_LD[7:0]

QUAKE has internal PD for LK_KD[3:0]

QUAKE has internal PU for SCI_RXD[3:0]

QUAKE has internal PU for USB inputs.

QUAKE has internal PD for GPT_INCAP[2:0], GPT_PWMA & GPT_PWMB.

QUAKE has internal PU for SPI_PCS[3:0]. QUAKE has internal PD/PU for TDI,

TCK, TMS & TRST_N. TDO is output

Ground guard these components and all associated traces, including traces to Quake and connect ground guard to digital ground. Place ground vias every 0.25 inches.

Ground guard these components and all associated traces, including traces to QUAKE and connect ground guard to analog ground. Place ground vias every 0.25 inches.

35.84 MHz XO

27 MHz VCXO

DNI

BER Test Header

GPIO_11 is dedicated for F/W to determine the number of DRAM chips installed

on a QUAKE platform.

Default is 1 chip = pull down, for 2 chips a pullup is required

A

QUAKE_DIGITAL.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

7 14

Friday, September 26, 2003

C _864684-049

Title

Document Number Rev

Date: Sheet of File Name Size EJTAG_TDO MC_CLK27 EBI_DATA_14 EBI_DATA_8 EBI_DATA_5 EJTAG_TDI EBI_ADDR_22 EJTAG_TMS SD_DATA_2 EBI_ADDR_23 EBI_ADDR_9 EBI_DATA_9 EBI_DATA_2 SD_DATA_12 SD_ADDR_11 EBI_ADDR_1 EBI_DATA_6 SD_DATA_15 EBI_ADDR_21 EBI_ADDR_15 EBI_ADDR_10 EBI_DATA_12 CLK27_O SD_ADDR_10 SD_ADDR_3 EBI_ADDR_14 EBI_DATA_4 EBI_DATA_1 SD_DATA_11 SD_ADDR_8 EBI_ADDR_18 EBI_ADDR_2 EBI_DATA_13 SD_ADDR_12 SD_DATA_8 SD_DATA_7 SD_DATA_6 EBI_ADDR_7 CLK27_OUT SD_ADDR_9 EBI_ADDR_24 EBI_ADDR_17 EBI_ADDR_8 EBI_ADDR_4 EBI_ADDR_0 SD_DATA_5 SD_DATA_1 SD_DATA_0 EBI_DATA_7 CLK27_I SD_ADDR_7 EJTAG_TCK EBI_DATA_15 SD_DATA_14 SD_DATA_3 SD_ADDR_2 SD_ADDR_0 EBI_DATA_10 CLK27_PCR_DAC SD_ADDR_6 EBI_ADDR_5 SD_DATA_9 SD_ADDR_4 EBI_ADDR_16 EBI_ADDR_6 SD_DATA_10 SD_ADDR_1 EBI_ADDR_13 EBI_DATA_11 EBI_DATA_0 SD_ADDR_5 EBI_ADDR_11 EBI_ADDR_3 EBI_DATA_3 SD_DATA_13 SD_DATA_4 EBI_ADDR_12 EBI_ADDR_20 EBI_ADDR_19 CLK27_PCR_DAC PHY_XTALO PHY_XTALI EJTAG_TRSTB SEL_FLASH1/ROMB PHY_XTALO PHY_XTALI CLK27_I CLK27_O INFO_CLK INFO_DATA MC_CLK40 INFO_SYNC INFO_SYNC INFO_CLK INFO_DATA MC_CLK40 CLK40_OUT D +3.3V D +3.3V D D D D D D A A A +3.3V D R221 100_s C222 47P_s 1 2 J201 header_6_pins 1 2 3 4 5 6 R220 100K_s TP203 R202 33_s Y210 35_84mhz_sm R227 4.7K_s L210 2.7uH_c_1210 R225 4.7K_s C223 1000P_s 1 2 R204 33_s R201 33_s D220 1sv322 2 1 TP206 C210 68P_s R210 47K_s Y220 27mhz 1 2 C221 0.01U_s 1 2 TP207 R203 33_s R224 4.7K_s C212 15P_s RP200 33_4_s 1 2 3 4 5 6 7 8 C220 22P_s 1 2 R223 100K_s TP204 R226 4.7K_s R200 33_s C225 0.1U_s 1 2 TP230 TP205 C211 15P_s R222 51_s J200 header_7pins_2rows 2 4 6 8 10 1 3 5 7 9 11 13 12 14 C224 0.1U_s 1 2

QUAKE Digital

I

/

O

U200D Quake T4 U1 U3 B13 A13 C11 B11 D13 C13 A12 D11 AB2 AB4 AC2 AD1 AE1 AE2 AD3 AF3 AC4 AE3 AF2 AF1 AD2 AC3 AC1 AB3 AB1 AA4 AA3 AA2 AA1 Y4 W4 W5 C15 AE21 AC20 B10 D15 AF21 AD20 A10 AD23 D10 AD15 AE20 AF20 AD19 AE19 AC18 AF18 AC17 AD17 AE17 AF17 AF16 AE16 AD16 AF19 AD18 AE18 AC19 W1 W2 W3 L4 L3 L2 A15 A19 C19 B15 B19 AF23 AE23 V2 V4 V3 D23 C25 AC16 A11 D12 B12 AD26 AD4 M1 R2 U5 T5 R5 P5 V25 V24 V23 W26 W25 W24 W23 AC21 AC15 C10 V26 U23 B22 R3 A22 D21 Y1 Y3 Y2 M2 M3 M4 R1 P4 P3 P2 P1 N4 N3 N2 N1 AD21 U2 AC23 AF4 AE15 C26 A26 B24 B25 AE4 C12 E12 AF24 AE24 AA25 Y25 Y24 AA24 AA26 Y26 Y23 AA22 Y22 AC26 AB23 AC25 AC24 AB26 AB24 AA23 AB25 B21 D20 A21 C21 E20 SPI_MISO SPI_MOSI SPI_SCK USB_A_DATAP USB_A_DATAN USB_A_PWR_ON_N USB_A_PWR_ERR_N USB_B_DATAP USB_B_DATAN USB_B_PWR_ON_N USB_B_PWR_ERR_N ATA_DATA00 ATA_DATA01 ATA_DATA02 ATA_DATA03 ATA_DATA04 ATA_DATA05 ATA_DATA06 ATA_DATA07 ATA_DATA08 ATA_DATA09 ATA_DATA10 ATA_DATA11 ATA_DATA12 ATA_DATA13 ATA_DATA14 ATA_DATA15 ATA_DRQ ATA_IOW ATA_IOR ATA_IOCHRDY ATA_DACK ATA_INTRQ ATA_CS0 ATA_CS1 SCI_RXD0 SCI_RXD1 SCI_RXD2 SCI_RXD3 SCI_TXD0 SCI_TXD1 SCI_TXD2 SCI_TXD3 GPT_INCAP0 GPT_INCAP1 GPT_INCAP2 LK_SEL0 LK_SEL1 LK_SEL2 LK_SEL3 LK_SEL4 (656_IN_CLK) LK_LD0 (656IN_D0) LK_LD1 (656IN_D1) LK_LD2 (656IN_D2) LK_LD3 (656IN_D3) LK_LD4 (656IN_D4) LK_LD5 (656IN_D5) LK_LD6 (656IN_D6) LK_LD7 (656IN_D7) LK_KD0 LK_KD1 LK_KD2 LK_KD3 MCI_PKTCLK MCI_PKTSYN MCI_PKTDAT MENC_PKTCLK MENC_PKTSYN MENC_PKTDAT HSI_DATA0 HSI_PKTDAT HSI_PKTCLK HSI_DATA1 HSI_PKTSYN I2C_SCL I2C_SDA MCO_PKTCLK MCO_PKTDAT MCO_PKTSYN DO_POD_CLK (CRX) DO_POD_DATA (DRX) IR_IN IR_OUT SFTM_PWRCLKP SFTM_DIB_DATAP GPIO00 GPIO01 GPIO02 GPIO03 GPIO04 GPIO05 GPIO06 GPIO07 GPIO08 GPIO09 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 ATA_DA0 ATA_DA1 ATA_DA2 AUD_I2SO_DATA AUD_I2SO_LRCLK AUD_I2SO_CLK CCIR656_B00 CCIR656_B01 CCIR656_B02 CCIR656_B03 CCIR656_B04 CCIR656_B05 CCIR656_B06 CCIR656_B07 CCIR656_BCLK GPT_PWMA SPI_PCS0 SPI_PCS1 SPI_PCS2 GPT_PWMB UO_POD_Q (QTX) UO_POD_I (ITX) UO_POD_C (CTX) UO_POD_E (ETX) SPI_PCS3 SFTM_DIB_DATAN SFTM_PWRCLKN DMX_DBG_TXD DMX_DBG_RXD CCIR656_A06 CCIR656_A01 CCIR656_A02 CCIR656_A07 CCIR656_A05 CCIR656_A00 CCIR656_A03 CCIR656_A08 CCIR656_A04 CCIR656_A13 CCIR656_A12 CCIR656_A14 CCIR656_A15 CCIR656_A09 CCIR656_A11 CCIR656_ACLK CCIR656_A10 AUD_COMP_CLK AUD_COMP_LRCLK AUD_COMP_DATA AUD_MCLK AUD_REQ_N R205 33_s

QUAKE Digital

C

P

U200B Quake A9 C4 C3 C2 C1 D4 D3 D2 D1 E4 E3 A8 B8 A7 B7 C7 A6 B6 C6 A5 B5 A4 B4 A3 B9 B3 D9 A2 A1 C5 B2 B1 K1 K2 H5 D8 E1 E2 D6 T2 R4 T3 K3 K4 J5 C9 D5 E5 F5 C8 G5 D7 T1 AD8 AE8 AF6 AE6 AD6 AF5 AE5 AC5 AD5 AC6 AB7 AC7 AD7 AB8 AF7 AE7 AE14 AF14 AE13 AF13 AF12 AE12 AF11 AE11 AC11 AD11 AC12 AD12 AD13 AC13 AD14 AC14 AF8 AE9 AF9 AD10 AB10 AF10 AC10 AD25 AE25 AF26 AD24 AE26 AF15 AC22 L26 K22 A20 B20 D19 U4 V1 AC8 F4 F3 F2 F1 G4 G3 G2 G1 H4 H3 H2 H1 J4 J3 J2 J1 AE10 AB11 L1 AB9 AC9 AD9 AF25 CP_BOOTSEL_CS0_N CP_ADDR00 CP_ADDR01 CP_ADDR02 CP_ADDR03 CP_ADDR04 CP_ADDR05 CP_ADDR06 CP_ADDR07 CP_ADDR08 CP_ADDR09 CP_ADDR10 CP_ADDR11 CP_ADDR12 CP_ADDR13 CP_ADDR14 CP_ADDR15 CP_ADDR16 CP_ADDR17 CP_ADDR18 CP_ADDR19 CP_ADDR20 CP_ADDR21 CP_ADDR22 CP_ADDR23 CP_ADDR24 CP_ADDR25 CP_CS_N0 CP_CS_N1 CP_CS_N2 CP_CS_N3 CP_CS_N4 CP_CS_N5 CP_CS_N6 CP_CS_N7 CP_CS_N8 CP_R_WN CP_RD_N CP_DSACK_N SYS_RSTI_N NMI_N EXTI0 EXTI1 EXTI2 EXTI3 EXTI4 CP_CLK27_OUT CP_SIZE0 CP_SIZE1 CP_ADDR_STRB_N CP_BERR_N CP_DATA_STRB_N SYS_RSTO_N MI_CS_N0 MI_CS_N1 MI_MADDR00 MI_MADDR01 MI_MADDR02 MI_MADDR03 MI_MADDR04 MI_MADDR05 MI_MADDR06 MI_MADDR07 MI_MADDR08 MI_MADDR09 MI_MADDR10 MI_MADDR11 MI_BANK_O0 MI_BANK_O1 MI_MDBUS00 MI_MDBUS01 MI_MDBUS02 MI_MDBUS03 MI_MDBUS04 MI_MDBUS05 MI_MDBUS06 MI_MDBUS07 MI_MDBUS08 MI_MDBUS09 MI_MDBUS10 MI_MDBUS11 MI_MDBUS12 MI_MDBUS13 MI_MDBUS14 MI_MDBUS15 MI_RAS_N MI_CAS_N MI_WE_N MI_WMASK0 MI_WMASK1 MI_DQS0 MI_DQS1 TRST_N TMS TCK TDI TDO OUTENB_N TCC QFE_XTI QFE_XTO CLK27_VCXO_I CLK27_VCXO_O PCRDAC CLK27_OUT CLK54_OUT MI_MADDR12 CP_DATA00 CP_DATA01 CP_DATA02 CP_DATA03 CP_DATA04 CP_DATA05 CP_DATA06 CP_DATA07 CP_DATA08 CP_DATA09 CP_DATA10 CP_DATA11 CP_DATA12 CP_DATA13 CP_DATA14 CP_DATA15 MI_DQS2 MI_DQS3 CP_CLK40_OUT MI_CKE MI_CLK MI_CLK_N EJTAG_SEL_N EBI_R/WB EBI_RDB SD_BA_1 SD_RASB SD_CASB SD_BA_0 SD_WEB SD_CSB_0 POR_RESETB MANF_RXD MANF_TXD FLASH1_CSB ROM_CSB IR_IN EBI_ADDR_[24:0] SRAMLB_CSB EBI_DATA_[15:0] SRAMUB_CSB PKT_SYNC PKT_CLK PKT_DATA SPI_CLK SPI_MOSI SPI_MISO MC_SPI_CSB EJTAG_RESETB MC_CLK27 MC_IRQB SD_DATA_[15:0] SD_ADDR_[12:0] CH3/4_SEL SD_UDQS_1 SD_UDM SD_CLK POR_IRQB SD_CLKB SD_LDQS_0 SD_CLKE SYS_RESETB SD_LDM MSG_LED PWR_LED SEL_FLASH1/ROMB INFO_CLK INFO_SYNC INFO_DATA MC_CLK40

5 5 4 4 3 3 2 2 1 1 D D C C B B A A

RESET CONFIGURATION:

cp_data00 RC: ebi_config Bit

cp_data01 RC: boot_config Bit

cp_data02 RC: Memory Clock Speed Select Bus Bit 0

cp_data03 RC: Memory Clock Speed Select Bus Bit 1

cp_data04 RC: MIPS Clock Speed Select Bus Bit 0

cp_data05 RC: MIPS Clock Speed Select Bus Bit 1

cp_data06 RC: MIPS Clock Speed Select Bus Bit 2

cp_data07 RC: USB Normal Clock Source Select

cp_data08 RC: Internal clk27 Alternate Source Select

cp_data09 RC: MIPS After Reset Delay Enable

cp_data10 RC: Staggered Reset Off Select

cp_data11 RC: Slip ckt control

cp_data12 RC: PLL By-Pass Select

DNI DNI DNI

SRAM

EBI_DATA_[15..13] to be used by F/W to detect HW configurations.

EBI_DATA_[15..13] 111 = Quake Installed EBI_DATA_[15..13] 000 = Quake RP Installed

TYPE/VENDOR

BOOT BLOCK FLASH

SIZE

Intel_ GE28F320C3BD70 ST_M28W320ECB70_ZB1

BOOT BLOCK(U300)

uBGA package

only

TABLE 1: MEMORY OPTIONS

32 MBIT

DDR SDRAM SPEED SETTING

121.5MHz => EBI_DATA_[3:2] = 10

162MHz => EBI_DATA_[6..4] = 010

MIPS SPEED SETTING

DNI DNI DNI DNI DNI

The

placement of

C302 should

be near the

E1 and F5 of

U300.

The

placement

of C303

should be

near the

D6 and E1

of U301.

FLE-121-01-G-DV-A (SAMTEC)

ROM Socket

Daughter card

interface

DNI: (Install only for the Proto,

EPR and PPR)

Layout Note: Remapping connector

signals is allowed for layout

optimization if necessary.

NOTE: All test pads

should be placed at the

bottom layer

A

PLATFORM_FLASH & SRAM.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

8 14

Friday, September 26, 2003

C _864684-049

Title

Document Number Rev

Date: Sheet of File Name Size EBI_DATA_5 EBI_DATA_7 EBI_DATA_6 EBI_DATA_0 EBI_DATA_8 EBI_DATA_14 EBI_DATA_13 EBI_DATA_15 EBI_ADDR_12 EBI_ADDR_13 SRAM_VBATT EBI_ADDR_5 EBI_ADDR_15 POR_RAM_ENB EBI_ADDR_4 EBI_ADDR_14 EBI_ADDR_17 SRAMUB_CSB EBI_ADDR_7 EBI_ADDR_6 EBI_ADDR_16 EBI_ADDR_3 EBI_ADDR_1 EBI_ADDR_2 EBI_ADDR_9 EBI_ADDR_11 EBI_R/WB EBI_RDB SRAMLB_CSB EBI_ADDR_8 EBI_ADDR_10 EBI_DATA_1 EBI_DATA_2 EBI_DATA_3 EBI_DATA_4 EBI_DATA_10 EBI_DATA_11 EBI_DATA_12 EBI_DATA_9 EBI_DATA_0 EBI_DATA_1 EBI_DATA_2 EBI_DATA_3 EBI_DATA_4 EBI_DATA_5 EBI_DATA_6 EBI_DATA_7 EBI_DATA_8 EBI_DATA_9 EBI_DATA_10 EBI_DATA_11 EBI_DATA_12 EBI_DATA_13 EBI_DATA_14 EBI_DATA_15 EBI_R/WB SYS_RESETB FLASH1_CSB EBI_RDB SRAM_CSB EBI_DATA_14 EBI_DATA_12 EBI_ADDR_3 EBI_ADDR_11 EBI_DATA_7 EBI_DATA_8 EBI_DATA_15 EBI_ADDR_9 EBI_ADDR_2 EBI_ADDR_19 EBI_ADDR_8 EBI_ADDR_12 EBI_DATA_9 EBI_DATA_10 EBI_ADDR_1 EBI_DATA_2 SEL_FLASH1/ROMB EBI_DATA_3 EBI_ADDR_14 EBI_ADDR_5 EBI_ADDR_17 EBI_ADDR_7 EBI_DATA_1 EBI_ADDR_6 EBI_ADDR_13 EBI_ADDR_18 EBI_ADDR_10 EBI_DATA_6 EBI_ADDR_16 EBI_RDB EBI_DATA_11 EBI_DATA_13 EBI_DATA_5 EBI_ADDR_4 EBI_ADDR_15 EBI_DATA_4 EBI_ADDR_20 ROM_CSB EBI_ADDR_9 EBI_ADDR_2 EBI_ADDR_19 EBI_ADDR_20 EBI_ADDR_22 EBI_ADDR_23 EBI_ADDR_3 EBI_ADDR_16 EBI_ADDR_13 EBI_ADDR_7 EBI_ADDR_8 EBI_ADDR_17 EBI_ADDR_24 EBI_ADDR_10 EBI_ADDR_14 EBI_ADDR_11 EBI_ADDR_4 EBI_ADDR_21 EBI_ADDR_12 EBI_ADDR_6 EBI_ADDR_5 EBI_ADDR_15 EBI_ADDR_18 EBI_ADDR_1 EBI_DATA_1 EBI_DATA_13 EBI_DATA_6 EBI_DATA_0 EBI_DATA_14 EBI_DATA_12 EBI_DATA_2 EBI_DATA_4 EBI_DATA_8 EBI_DATA_5 EBI_DATA_11 EBI_DATA_3 EBI_DATA_15 EBI_DATA_10 EBI_DATA_9 EBI_DATA_7 EBI_DATA_0 D +3.3V D D D +3.3V D +3.3V D D TP303 TP345 1 U300 Intel_GE28F320C3BD70 xxxxxx-xxx-xx D8 C8 B8 C7 A8 B7 C6 A7 A3 C3 B2 A2 C2 A1 B1 C1 D1 B6 B5 A6 C5 E7 F7 D5 E5 F4 D3 E3 F2 D6 E6 F6 D4 E4 F3 D2 E2 D7 F8 B4 B3 A5 A4 F5 E1 E8 F1 C4 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CE/ OE/ RP/ WE/ WP/ VPP VCC VCCQ GND GND A21 TP302 1 RP301 10000_4 1 2 3 4 5 6 7 8 R314 10K_s TP332 1 TP335 1 R300 10K_s TP317 1 TP338 1 C302 0.01U_s 1 2 TP306 1 C303 0.01U_s 1 2 TP313 1 1 TP341 TP310 1 TP304 1 TP330 TP316 1 TP333 1 R317 10K_s TP301 TP336 1 TP339 1 R315 10K_s R307 10K_s R308 10K_s TP342 1 TP351 1 TP352 R306 10K_s R319 10K_s TP307 1 TP343 1 TP315 1 TP350 1 TP312 1 TP344 1 RP300 10000_4 1 2 3 4 5 6 7 8 R303 10K_s U301 CY62137VLL 481396-001-69 B4 B3 A5 A4 A3 E1 D6 G4 F3 F4 E4 D3 C3 C4 D4 H2 H3 H4 H5 G3 D1 E6 C5 C6 D5 E5 F5 F6 G6 B1 C1 C2 D2 E2 F2 F1 G1 A2 G5 A1 B2 A6 B5 B6 H1 H6 G2 E3 A4 A3 A2 A1 A0 V CC1 V CC2 A13 A14 A15 A16 nc17 A5 A6 A7 A8 A9 A10 A11 A12 GND1 GND2 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 /OE /WE /LB /UB ncCS2 /CS1 I/O0 nc1 nc2 nc3 nc4 Q300 2sc2712 1 3 2 TP308 1 C300 0.1U_s 1 2 TP331 1 R311 10K_s C301 0.1U_s 1 2 TP319 1 R313 10K_s R312 10K_s R318 10K_s TP334 1 TP311 1 TP337 1 R302 10K_s R310 10K_s R304 10K_s R301 1K_s R309 10K_s TP340 1 TP305 1 TP318 ₁ R305 10K_s R316 10K_s TP320 1 TP309 1 TP314 1 J300

hdr42_21x2_50_sm

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 SRAMLB_CSB SRAM_VBATT SRAMUB_CSB POR_RAM_ENB FLASH1_CSB EBI_RDB SYS_RESETB EBI_R/WB EBI_DATA_[15:0] SEL_FLASH1/ROMB ROM_CSB EBI_ADDR_[24:1]

5 5 4 4 3 3 2 2 1 1 D D C C B B A A

16 MBYTES UNIFIED DDR_SDRAM

Place caps near U202 (DDR_SDRAM)

1%

1%

MICRON - MT46V8M16TG-6T

1. DDR_DATA[15:0] lines and strobes should be the shortest (and most direct) trace lengths as possible.

2. CK & CKB traces again should be the shortest possible lengths, with CK & CKB being adjacent to each other on ALL layers.

3. DDR_ADDR[15:0], & control signals are not as critical as layout items 1 and 2.

4. NO data or data strobe traces should exceed 2 inches in length. (The 2 inches includes traces to and from series termination

resistors) Less critical signals should be less than 3 inches. Clock traces can be up to 3 inches, but should be as short as possible.

Route DQS and clock pair signal traces FIRST when laying out the board.

5. Trace length variations are as follows:

Data, DQS signal traces have no more than 0.5 inch variation

Address, DQM, control signal traces have no more than 1.0 inch variation

Clock traces should be as closely matched as possible.

6. Clock traces should be on same layer(s) and should be spaced 5 mils from each other, with other signal traces spaced 10 mils away.

7. Number of vias for data and DQS lines should be restricted to maximum of 2 per signal trace. Other signals should be restricted to

no more than 3 vias per signal trace. Micro-vias (14 mil through hole) can be used for signals, with larger (20 mil minimum through

hole) used for power and grounds.

8. Trace widths for signals should be 5-6 mils. Power and ground signals should have minimum 10 mil traces from pins to vias (that drop

down to power/ground planes)

8a. DDR_VREF signal should be 20mil trace.

9. DDR section of board should keep all signals that are NOT part of the DDR interface outside of defined area on ALL layers.

10. Decoupling capacitors should be used in accordance with the DDR manufacturer's recommendations. Bulk bypass capacitors should be

located nearby DDR memory.

11. Power and ground pins should have dedicated traces to VIA, with adjacent power and ground pins using common trace only when

distance to via is less than .2 inch from any one pin/ball. In this case a more robust trace should be used to connect more than one

pin to the via. (15 mil trace minimum)

Place this cap

close to the

U202

LAYOUT NOTES:

467639-001 6.3V X5R 1206 See table page 1

Place this cap

close to the U200

(QUAKE)

10% 50V X7R

10% 50V X7R

A

DDR_SDRAM.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

9 14

Friday, September 26, 2003

C _864684-049

Title

Document Number Rev

Date: Sheet of File Name Size DDR_ADDR_3 DDR_DATA_6 DDR_UDM DDR_ADDR_6 DDR_DATA_14 DDR_DATA_11 DDR_DATA_4 DDR_DATA_2 DDR_DATA_1 DDR_LDM DDR_ADDR_9 DDR_DATA_0 DDR_ADDR_7 DDR_DATA_7 DDR_DATA_3 DDR_ADDR_4 DDR_DATA_10 DDR_ADDR_1 DDR_DATA_15 DDR_DATA_13 DDR_RASB DDR_WEB DDR_ADDR_11 DDR_ADDR_0 DDR_DATA_9 DDR_DATA_5 DDR_BA_1 DDR_ADDR_5 DDR_CASB DDR_CSB_0 DDR_ADDR_8 DDR_DATA_8 DDR_ADDR_2 DDR_ADDR_12 DDR_ADDR_10 DDR_BA_0 DDR_DATA_12 SD_VREF DDR_LDQS_0 DDR_UDQS_1 DDR_CK DDR_CLKE DDR_CKB DDR_BA_1 SD_DATA_8 DDR_DATA_10 DDR_ADDR_2 SD_LDQS_0 DDR_WEB SD_CLK SD_ADDR_10 SD_DATA_6 SD_DATA_0 SD_UDQS_1 DDR_DATA_3 SD_CSB_0 SD_ADDR_12 DDR_DATA_11 DDR_DATA_14 DDR_DATA_13 DDR_ADDR_9 DDR_ADDR_6 DDR_LDQS_0 SD_DATA_3 DDR_UDQS_1 DDR_CK DDR_ADDR_12 DDR_DATA_4 DDR_CKB SD_CASB DDR_ADDR_4 SD_ADDR_11 DDR_ADDR_0 SD_LDM SD_DATA_7 DDR_DATA_5 DDR_DATA_0 DDR_RASB SD_BA_0 SD_ADDR_6 SD_UDM DDR_ADDR_10 SD_DATA_10 SD_DATA_9 DDR_DATA_12 DDR_ADDR_11 DDR_ADDR_5 SD_CLKB DDR_ADDR_1 SD_BA_1 DDR_CASB SD_DATA_4 SD_DATA_1 DDR_DATA_6 DDR_DATA_1 DDR_DATA_7 SD_WEB DDR_UDM SD_ADDR_9 SD_RASB DDR_LDM SD_DATA_11 SD_DATA_14 SD_DATA_13 DDR_BA_0 DDR_DATA_9 DDR_CSB_0 DDR_ADDR_3 SD_DATA_5 SD_DATA_2 DDR_DATA_2 SD_CLKE DDR_ADDR_7 SD_ADDR_7 SD_DATA_12 SD_ADDR_8 SD_ADDR_2 SD_ADDR_3 SD_ADDR_5 DDR_ADDR_8 SD_ADDR_1 SD_ADDR_4 SD_ADDR_0 DDR_DATA_8 DDR_CLKE DDR_DATA_15 SD_DATA_15 D D D +2.5V +2.5V D D +2.5V D D D R419 33_s R424 33_s RP402 33_8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R410 33_s R416 33_s R402 10K_s R420 33_s C408 10P_s R407 121_s R404 121_s R409 33_s C411 1U_s RP401 33_8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C401 10U_c 1 2 R412 33_s R423 33_s R417 33_s C400 0.01U_s 1 2 R401 1K_s R405 121_s R411 33_s R413 33_s C403 1000P_s 1 2 R406 121_s R428 20_s R400 1K_s R414 20_s C406 0.01U_s C410 1000P_s 1 2 C405 0.1U_s 1 2 R421 33_s R418 33_s R403 10K_s C404 0.01U_s 1 2 R408 33_s RP400 33_8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C409 0.01U_s 1 2 C407 10P_s R422 33_s R415 33_s

8M x16

U400 1 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 29 30 31 32 35 36 37 38 39 40 28 41 42 17 3 6 14 15 16 18 19 21 22 23 24 25 26 27 33 34 43 44 45 46 47 48 49 50 51 52 53 55 58 64 61 66 9 12 20 VD D DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 NC (A13) V DDQ VSSQ NC V DDQ LDQS VD D DNU WE CAS RAS CS NC BA0 BA1 VD D VSS NC CKE CK CK UDM VSS VREF DNU UDQS VSSQ NC V DDQ VSSQ VSSQ V DDQ VSS V DDQ VSSQ LDM SD_DATA_[7..0] SD_WEB SD_ADDR_11 SD_ADDR_9 SD_LDQS_0 SD_LDM SD_BA_1 SD_CLK SD_UDQS_1 SD_ADDR_12 SD_CASB SD_BA_0 SD_ADDR_7 SD_CLKB SD_UDM SD_DATA_[15..8] SD_RASB SD_ADDR_10 SD_CSB_0 SD_ADDR_8 SD_ADDR_[6..0] SD_CLKE

5 5 4 4 3 3 2 2 1 1 D D C C B B A A

Low Leakage Cap

TDO

Bypass

DNI

A

SECURITY.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

10 14

Friday, September 26, 2003

C _864684-049

Title

Document Number Rev

Date: Sheet of File Name Size SYS_RESETB POR_RESETB PKT_DATA PKT_SYNC PKT_CLK VBATT MC_CLK27 MC_IRQB MC_RESETB SPI_MISO INFO_DATA SRAM_VBATT INFO_CLK MC_PKTDATA MC_PKTSTART SPI_CLK MC_CLK40 MC_PKTCLK SPI_MOSI INFO_SYNC MC_SPI_CSB JET JET JET BTV BTV JET BTV BTV BTV JET D +3.3V +3.3V +3.3V D D D D D D D D D +3.3V D D +3.3V D +3.3V C900 4700P_s 1 2 R903 470K_s R906 620_s VB903 TESTPIN BT903 3_0V_BR2335T3L_B 123002-020-99 2 1 3 C902 0.1U_s 1 2 VB901 TESTPIN D911 1n4148w 2 1 CLK27M TEST_PAD D901 1n5711 1 3 C908 4700P_s 1 2 C905 4700P_s 1 2 BT905 3_0V_BR2032T3L_B 2 1 3 C904 0.1U_s 1 2 +C910 100uf_07 1 2 C903 4700P_s 1 2 C909 0.1U_s 1 2 +C914 10u_50v 1 2 R904 470K_s VB902 TESTPIN BT906 3_0V_BR2330A_GA 2 1 3 RP900 33_4_s 1 2 3 4 5 6 7 8 TD900 R926 51_s RP901 470_4 1 2 3 4 5 6 7 8 C911 0.1U_s 1 2 C9130.1U_s 1 2 R922 10K_s D902 1n4148w 2 1 VB900 TESTPIN

MC1.7

U900 MC1_7C 1 2 3 4 5 8 9 10 11 12 13 16 17 18 19 22 23 24 25 26 28 32 33 34 35 100 99 97 94 92 89 88 87 86 85 84 83 82 81 78 77 76 7 15 20 27 29 42 48 53 59 6 14 21 30 46 47 54 71 31 41 60 70 72 80 91 93 95 90 36 37 38 39 40 43 44 45 75 74 68 67 66 65 64 63 62 61 58 49 50 57 56 55 52 51 69 73 79 96 98 SCLK SPL_CSB MOSI MISO UP_INTB TVPC_CLOCK TVPC_DETECTB TVPC_SIO TVPC_RESETB TVPC_3V_SENSE TVPC_5V_SENSE VBATT GNDBATT PDUNDERB VSUPPLY TMROEB TMS TCK TDI TDO PKTCLKOUT PKTSTARTOUT/MOSTRT PKTDATAOUT/MDO0 MDO1 MDO2 CLK_27 CTRL_CLK_27 RESETB SYNC_CLK PKTCLKIN/BITCLK PKTSTARTIN/MISTAT PKTDATAIN/MDI0 MDI1 MDI2 MDI3 MDI4 MDI5 MDI6 MDI7 MIVAL MCLKI MIERROR GN D GN D GN D GN D GN D GN D GN D GN D GN D V DD3 _VDD3 _VDD3 _VDD3 _VDD3 DD3_{V V}DD3 _VDD3 _VDD3 _VDD3 _VDD3 GN D GN D GN D GN D GN D GN D V DD3 MDO3 MDO4 MDO5 MDO6 MDO7 MOVAL MCLKO MOERROR TESTSEL TESTWRB TAD0 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TESTOUT0 FUSE1 FUSE1RTN TESTOUT1 TESTOUT2 TESTOUT3 FUSE0RTN FUSE0 V DD3 TESTCLK V DD3 _VDD3 VBATT_EN C906 0.1U_s 1 2 C901 0.1U_s 1 2 C915 47P_s 1 2 BT907 106007-002 1 2 C907 47P_s 1 2 D912 bat54alt1 3 2 1 BT904 3_0V_BR2450A_GB 414816-003-99 2 1 3 R914 4.7K_s INFO_CLK POR_RESETB SRAM_VBATT WRPROT_1 INFO_SYNC PKT_DATA PKT_SYNC MC_SPI_CSB POR_RAM_ENB SYS_RESETB MC_CLK40 MC_CLK27 INFO_DATA SPI_CLK WRPROT_3 SPI_MOSI PKT_CLK MC_IRQB SPI_MISO

A A B B C C D D E E 4 4 3 3 2 2 1 1

Place no traces or parts between

AUDIO_LEFT_POS/AUDIO_LEFT_NEG and

AUDIO_RIGHT_POS/AUDIO_RIGHT_NEG.

Keep traces close in length and

route traces next to one another.

Surround each pair with DGND.

Surround video trace

DIG_COMPOSITE with DGND.

Place bypass capacitors of +3.3v, +2.5v, and +1.2V near IC's pin on bottom side. QUAKE pin numbers for each cap are indicated. AB5 AB6 AB12 AB13 A17 (DAC B) AB14 AB15 AB17 AB18 AB21 AB22 W22 E8 E9 E10 E15 E18 G22 J22 L22 N22 R22 K5 L5 V5 Y5

VIDEO DAC CALCULATIONS

Ioutfs = 17.4 mA with Rbias = 628 ohms

Choose Rbias = 562 ohms

Rload = 75 ohms (see video page)

Dwhite = 364 (9 bit value) NTSC

Dsync = 14 (9 bit value) NTSC

Vout p-p = Ioutfs * (628 ohms / Rbias) *

Rload * ((Dwhite - Dsync)/511) = 1 Vp-p

E21 E22 U22 V22 AB16 E6 E7 M5 N5 E11 AB19 AB20 AA5

Place these parts near QUAKE.

DAC A, C & D not used.

DAC A, C & D not used.

Signal Opitimize

467639-001 6.3V X5R 1206 See table page 1 467639-001 6.3V X5R 1206 See table page 1 A

QUAKE_ANALOG.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

11 14

Friday, September 26, 2003

Custom 864684-049

Title

Document Number Rev

Date: Sheet of File Name Size +3.3VA0 +3.3VA5 +3.3VA2 SDC_AVDD +1.2VA2 +3.3VA7 +3.3VA6 +3.3VA3 +1.2VA5 +3.3VA4 +1.2VA1 ANA_1.2V +1.2VA3 +1.2VA4 +3.3VA8 +3.3VA9 +3.3VA1 ANA_3.3V D D +1.2V +3.3V +2.5V A D A +3.3V D +1.2V D A A D +3.3V +3.3V D +3.3V +3.3V D D A A D +3.3V D C422 0.1U_s L401 10uH_c_1008 L423 ferrite_0603 1 2 C436 0.1U_s R473 30.1K_s 1% C471 1U_s C426 0.1U_s L424 ferrite_0603 1 2 C437 0.1U_s C448 0.01U_s L413 ferrite_0603 1 2 L425 ferrite_0603 1 2 C455 0.1U_s C427 0.1U_s C472 1U_s

QUAKE Analog

(UO_IREFD) U200A Quake K25 K26 A23 A25 R25 R26 C23 T25 T24 F26 E23 U26 U25 U24 D18 C14 D14 A14 B14 AD22 AE22 AF22 B16 E16 B17 E17 C18 M23 M25 N26 N25 J24 J23 M24 D26 C24 A24 B26 B23 J26 H22 P24 P23 H24 A18 H25 P25 H23 F23 C17 C16 DI_ADC1_VIN DI_ADC1_VIP DI_RFAGC_SDV DI_AGC_SDV DO_ADC3_VIP DO_ADC3_VIN DO_AAGC_SD DO_LO_BP DO_LO_BN UO_IOUTP UO_IOUTN TNR_RFTCK TNR_RFTD TNR_RFTE0 AUD_DIGAUD AUD_LEFT_POS AUD_LEFT_NEG AUD_RIGHT_POS AUD_RIGHT_NEG AUD_I2SI_DATA AUD_I2SI_LRCLK AUD_I2SI_CLK QVD_DV_D_P QVD_DV_C_P QVD_DV_B_P QVD_DV_A_P QVD_RBIAS BTSC_ADC2_VREFP BTSC_ADC2_VCM BTSC_ADC2_VIN BTSC_ADC2_VIP AVD_ADC1_VIP AVD_ADC1_VIN BTSC_ADC2_VREFN UO_PWR0_GATEB UO_PWR1_CLK UO_PWR2_DATA UO_PWR3 UO_RF_SD_OUT DI_ADC1_VREFN DI_ADC1_VREFP DO_ADC3_VREFN DO_ADC3_VREFP QFE_ADC_VBGOUT QVD_VREF QFE_EXT_IREF DO_ADC3_VCM DI_ADC1_VCM UO_DAC_BG_PSUPA QVD_AVSS_BIAS QVD_AVSS_BIAS2 C465 1U_s C487 0.1U_s C466 1U_s C450 10U_c L412 ferrite_0603 1 2 RP411 1000_4 1 2 3 4 5 6 7 8 C484 0.1U_s C475 0.1U_s 1 2 RP410 1000_4 1 2 3 4 5 6 7 8 C440 0.1U_s L421 ferrite_0603 1 2 C463 1U_s L410 ferrite_0603 1 2 C453 0.1U_s L422 ferrite_0603 1 2 C434 10U_c C441 0.01U_s L418 ferrite_0603 1 2 C456 0.1U_s 1 2 C419 0.1U_s C445 0.1U_s C435 0.1U_s L420 ferrite_0603 1 2 C438 0.1U_s C474 0.1U_s L411 ferrite_0603 1 2 C421 0.1U_s C482 0.1U_s C443 0.1U_s C442 0.1U_s C425 0.01U_s C485 0.1U_s C467 1U_s

QUAKE Power

U200C Quake AB12 AB13 J2 2 K5 L5 L22 N22 AB6 AB5 AB19 AB20 E11 E21 E22 E6 G23 J25 L25 L24 G25 N23 P22 E24 G26 E26 E25 M22 L23 H26 K24 K23 P26 R24 G24 D25 D16 A17 D17 B18 A16 M26 N24 L11 L12 L13 L14 L15 L16 M11 M12 M13 M14 M15 M16 N11 N12 N13 N14 N15 N16 P11 P12 P13 P14 P15 P16 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15 T16 T26 T23 R23 E14 E13 D24 F22 E18 G2 2 E8 E9 E15 AA5 Y5 AB16 V5 R22 W22 AB22 E10 AB21 AB18 AB15 AB17 AB14 F24 T22 F25 C22 D22 C20 E19 E7 M5 N5 U22 V22 VDD25 VDD25 VDD12 VDD12 VDD12 VDD12 VDD12 VDD25 VDD25 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 DI_ADC1_NSUPA DI_ADC1_NSUPA_SHA QFE_XTAL_NSUPA QFE_ADC_ASUB VSS_PLL DO_ADC3_NSUPA DO_ADC3_NSUPA_SHA UO_DAC_NSUPA UO_DAC_NSUPD UO_DAC_BG_NSUPA UO_DAC_ASUB BTSC_ADC2_NSUPA_SHA BTSC_ADC2_NSUPA DI_ADC1_PSUPA DI_ADC1_PSUPA_SHA QFE_XTAL_PSUPA DO_ADC3_PSUPA DO_ADC3_PSUPA_SHA VDD_PLL UO_DAC_PSUPD QVD_AVDD_C QVD_AVDD_B QVD_AVDD_A QVD_AVDD_BIAS QVD_AVDD_D BTSC_ADC2_PSUPA BTSC_ADC2_PSUPA_SHA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DO_LO_VBB DO_LO_VSSB DO_LO_BGND SDC_AGND SDC_AVDD UO_QUIET_NSUPD UO_QUIET_PSUPD VDD12 VDD12 VDD12 VDD12 VDD12 VDD33 VDD12 VDD33 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 VDD12 UO_DAC_PSUPA DO_LO_VDDB UO_VBIAS QFE_PGND QFE_VPP XTAL_CLK27_PSUPA XTAL_CLK27_NSUPA VDD33 VDD33 VDD33 VDD33 VDD33 R475 470_s C446 0.01U_s L415 ferrite_0603 1 2 C473 0.1U_s C493 1U_s C428 0.1U_s R472 8.06K_s 1% C439 0.1U_s C454 0.1U_s L402 10uH_c_1008 L414 ferrite_0603 1 2 C447 0.1U_s C492 1U_s C444 0.01U_s C481 1U_s R474 562_s 1% L419 ferrite_0603 1 2 C457 0.1U_s 1 2 C486 0.1U_s C424 0.01U_s C432 0.1U_s C420 0.01U_s RP412 470_4 1 2 3 4 5 6 7 8 C423 0.01U_s C464 1U_s TX_DAC-OOB_IF_NEG AUDIO_RIGHT_POS OOB_IF_POS IB_IF_NEG AUDIO_RIGHT_NEG AUDIO_LEFT_POS TX_DAC+ OOB_VCO_POS TX_OEN IB_IF_POS OOB_VCO_NEG DIG_COMPOSITE AUDIO_LEFT_NEG US_CTL_CSB US_CTL_CLK US_CTL_DATA TUNER_SDA TUNER_SCLK OOB_AGC QAM_AGCI QAM_AGCT

5 5 4 4 3 3 2 2 1 1 D D C C B B A A

2 Vrms at 0 dBFS.

1.132 Vrms at 0 dBFS

2 Vrms at 0 dBFS.

MC44BC375U data sheet: 85% FM modulation at 1 kHz with 205 mVrms input at pin 7, with pre-emphasis.

Pre-emphasis gain at 1 kHz = 0.87 dB. 100% modulation = +/- 25 kHz.

To achieve +/- 50 kHz FM modulation (200%) without pre-emphasis, the nominal input level at pin 7 is:

2*(205 mVrms)*(0.87 dB)/(85%) = 534 mVrms.

The digital audio level at the top end of R853 must be greater than 534 mVrms in order to achieve alignment.

Target value = 566 mVrms for analog channel and 1132 mVrms for digital channel.

Loop Filter must

be as close as

possible to pins

14&15

Lowpass filter, F3dB = 159 kHz

10%

Place no traces or parts between

AUDIO_RIGHT_POS and AUDIO_RIGHT_NEG.

Keep traces close in length and route

traces next to one another. Surround

the pair of traces with digital ground

plane.

2 Vrms at 0 dBFS.

Place no traces or parts between

AUDIO_LEFT_POS and AUDIO_LEFT_NEG.

Keep traces close in length and route

traces next to one another. Surround

the pair of traces with digital

ground plane.

2 Vrms at 0 dBFS.

Audio DAC Filter and Output Amp

Video DAC Filter and Output Amp

Video/Audio RF Modulator (Remod)

Change to

surface mount.

TDK part

NLFV25T-100K.

Must be X7R

X7R

A

AUDIO_VIDEO.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

12 14

Friday, September 26, 2003

C _864684-049

Title

Document Number Rev

Date: Sheet of File Name Size DAC_AUD_LEFT REMOD_AUDIO DAC_AUD_RIGHT REMOD_VIDEO DAC_AUD_RIGHT DAC_AUD_LEFT REMOD_VIDEO D A A A A A A A A A A A A A +5V D -5V D D -5V D +5V D D D +5V D D -5V D D +5V A A R704 1K_s 1% C820 0.1U_s C723 22P_s 1 2 C807 0.01U_s C822 0.1U_s C704 10P_s 1 2 R734 8.25K_s 1% C720 270P_s 1 2 C702 0.1U_s 1 2 R735 100K_s 1% C817 750P_s 5%, NPO C739 100P_s C721 22P_s 1 2 C719 0.1U_s 1 2 R727 8.25K_s 1% R707 1K_s R737 47.5K_s 1% R743 1.3K_s 1% R806 150_s RES\1%\0603 R702 20_s C707 100P_s C725 270P_s 1 2 C816 27P_s R807 10K_s R808 7.5K_s C718 0.1U_s 1 2 C803 7P_s L1119 10uH_c_1008 R705 510_s R809 50K_POT 1 3 2 R803 2.2K_s C745 100P_s C815 0.1U_s C813 0.01U_s R732 100K_s 1% C810 0.01U_s C802 43P_s C812 0.1U_s L804 3.3uH_c_1210 R714 3.3K_s Q702 2sc2712 1 3 2 R741 2K_s 1% C726 22P_s 1 2 R810 1K_s D800 smbj13 2 1 R700 102_s 1% C808 0.047U_s Y800 4MHz C819 0.022U_s R713 3.3K_s L700 6.8uH_c_0805 C821 1000P_s R728 8.25K_s 1% Q701 2sc2712 1 3 2 + -U700B NJM4580 128006-129-26 5 6 7 8 4 U800 mc44bc375u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CHS PSS LOP XTAL GND PREEM AUDIO SPLFLT PS/LO VIDEO VCCA GND TVOUT TVOVCC PLLFLT SFS R805 560_s L801 120nH_c_0603 1 2 C701 150P_s 1 2 R703 1.2K_s R801 27_s R733 8.25K_s 1% R800 470_s C804 36P_s C724 22P_s 1 2 R738 100K_s 1% R736 47.5K_s 1% C805 9P_s C800 0.01U_s R804 2K_POT 118874-513-14 1 3 2 R730 47.5K_s 1% R708 75_s 1% R802 470_s C809 0.022U_s R729 47.5K_s 1% Q700 2sc2712 1 3 2 C703 0.1U_s 1 2 C818 1U C700 270P_s 1 2 R706 887_s 1% L800 150nH_c_0603 1 2 R701 280_s 1% F800 tps4_5mb2 1 3 2 + C1142 10uf_01 1 2 + -U700A NJM4580 128006-129-26 3 2 1 8 4 R742 2K_s 1% L803 4.7uH_c_0805 1 2 C814 1000P_s R731 100K_s 1% CH3/4_SEL AUDIO_LEFT_POS LINE_OUT_LEFT LINE_OUT_RIGHT AUDIO_RIGHT_NEG AUDIO_LEFT_NEG AUDIO_RIGHT_POS DIG_COMPOSITE COMP_OUT REMOD_OUT

A A B B C C D D E E 4 4 3 3 2 2 1 1

3. Keep these 2 traces very close to each other. Don't route

under bypass caps. Don't place any trace between them.

70 to 130 mhz LPF. Helps to

reduce LO leakage and also reject signals above 130 MHz.

Note 3

1. Use 0603 chip caps and resistors.

2. LA7784 Batwings must be connected to ground.

Notes :

Keep the bypass capacitors very close to the pins of the LA7784

See note 3

See note 3

149188-018

180 MHz Lowpass Filter

Inductors are TDK MLG1608 series

OOB Tuner

60 MHz Lowpass Filter

10%

Inductors are TDK MLF1608 series

10%

QAM IF SAW Filter and AGC Amp

10%

10%

10%

10% 501442-002

See table page 1. 10V Y5V 0805 L1110 should be changed by new part number L1112 should be changed by new part number C1100 C1101 Do not install Table 1 C1102 C1103 Do not install L1100 L1101 0 ohm resistor L1102 L1103 0 ohm resistor R1100 1000 ohms 1% R1101 R1102 499 ohms 1% L1104 L1105 0 ohm resistor A

AFE.SCH

San Diego, California, USA. Taipei, Taiwan, R.O.C.

13 14

Friday, September 26, 2003

C 864684-049

Title

Document Number Rev

Date: Sheet of File Name Size +5VA_OOB SAW_IF_NEG +5VA_IB SAW_IF_POS A A A A A A A A A A +5V A A A A +5VA_OOB +5VA_OOB L1104 1.5uH_c_0603 C1124 1000P_s 1 2 TP1104 TUNER_IF L1118 27nH_c_0603 R1107 49.9_s 1% R1110 23.7_s 1% TP1106 OOB_IF_NEG L1108 100nH_c_0603 TP1105 OOB_IF_POS C1130 6P_s 1 2 L1102 1.5uH_c_0603 C1125 0.1U_s 1 2 C1120 0.01U_s 1 2 L1113 27nH_c_0603 R1109 23.7_s 1% F1100 x6964m 1 2 4 5 3 IN ING POUT1 POUT2 CHIP C1140 27P_s TP1103 QAM_AGCI L1100 1.5uH_c_0603 L1111 100nH_c_0603 R1102 499_s1% R1103 51_s L1106 10uH_c_1008 C1136 0.01U_s 1 2 L1112 220nH_c_0603 1 2 L1117 27nH_c_0603 TP1107 AGND C1105 0.01U_s 1 2 C1121 0.01U_s 1 2 C1135 0.01U_s 1 2 C1132 12P_s 1 2 C1131 5P_s 1 2 TP1108 OOB_AGC C1122 0.1U_s 1 2 F1101 saf49_10mc220z 1 2 4 5 3 _IN CHIP POUT1 POUT2 SOUT C1141 0.1U_s 1 2 + C1109 10uf_01 1 2

U1101

LA7784

471105-001-32 1 2 3 23 24 26 27 4 5 12 13 6 7 11 15 25 28 14 19 20 9 10 16 17 18 21 22 8 NC_ G N D NC_ G N D GN D RF_IN1 RF_IN2 MIX_OUT1 MIX_OUT2 IF_ IN1 IF_ IN2 OUT1 OUT2 NC_ G N D GN D GN D GN D GN D GN D VC C _ POST _AM P V CC_ MIX _ L O V CC_ DRIV E R AGC_IN NC_ G N D LO_IN1 LO_IN2 NC_ G N D VC C _LN A VC C _LN A V CC_ IF C1134 11P_s C1128 0.01U_s 1 2 C1133 9P_s 1 2 U1100

LA7783

469774-001-28 1 16 2 7 15 3 4 5 9 8 10 14 12 6 13 11 IF_IN+ IF_IN-GN D GN D GN D AGC_SW DELAY_ADJ VC C IF_OUT-IF_OUT+ DRV _ A MP _ V CC VC C AGC _ VC C AGC_OUT2 AGC_OUT1 AGC_IN C1127 0.01U_s 1 2 C1107 0.1U_s 1 2 TP1101 IB_IF_NEG C1103 5P_s 1 2 L1103 1.5uH_c_0603 R1101 499_s1% C1138 47P_s C1123 0.1U_s 1 2 L1114 27nH_c_0603 C1139 47P_s C1101 9P_s 1 2 R1100 1K_s 1% C1126 0.1U_s 1 2 C1137 27P_s C1110 0.1U_s 1 2 C1102 9P_s 1 2 L1101 1.5uH_c_0603 C1108 0.01U_s 1 2 C1104 0.01U_s 1 2 C1129 0.01U_s 1 2 C1100 5P_s 1 2 L1115 27nH_c_0603 L1109 100nH_c_0603 R1104 51_s L1110 120nH_c_0603 TP1102 AGND L1105 1.5uH_c_0603 TP1100 IB_IF_POS R1105 75_s L1116 27nH_c_0603 OOB_IF_POS OOB_AGC OOB_IF_NEG OOB_VCO_POS OOB_VCO_NEG OOB_TAP IB_IF_NEG QAM_AGCI IB_IF_POS QAM_IF+

QAM_IF-A A B B C C D D E E 4 4 3 3 2 2 1 1

Place these parts near tuner IC.

Place these parts near QUAKE.

70 MHz Highpass Filter

42 MHz Lowpass Filter

Place close to the ALPS TUNER

Inductors are TDK MLG1608 series

SEE OPTION TABLE 1

R603

R604

Option Table 1

L609

L608

L607

L606

L605

L604

C614

Microtune

MT1530

13.0,

1%

SEE OPTION TABLE 1 463131-001

SEE OPTION TABLE 1

Upstream Amp

56nH

15.8, 1%

C613

C612

C611

R600

56nH

100nH

82nH

0.1uF

SEE OPTION TABLE 1

467639-001 6.3V X5R 1206 DNI

C603

C604

Anadigics

ARA2018

Sanyo

LA7791T

35.7,

1%

35.7,

1%

15.8,

1%

180nH

56nH

82nH

220nH

180nH

56pF

120pF

120pF

100pF

330pF

220pF

100pF

330pF

220pF

56pF

120pF

120pF

93.1,

1%

26.1,

1%

31.6,

1%

15pF

DNI

6800

pF

270pF

0.1uF

A

TUNER_UPSTREAM.SCH

San Diego, California, U.S.A. Taipei, Taiwan R.O.C.

14 14

Friday, September 26, 2003 864684-049

Title

Document Number Rev

Date: Sheet of File Name SCLK SDA SCLK UPSTREAM SDA UPSTREAM JET D A +5V A +5V_TUNER A D A A A A +5V_TUNER A +5V_TUNER A A A A A +5V_US +5V_US A A +5V A A A A A A A A +5V_US A A A A +5V_US A +5V_US A A A R505 470_s RP600 33_4_S 1 2 3 4 5 6 7 8 C616 0.01U_s R523 1M_2010 C538 27P_s C604 0.1U_s C608 0.01U_s C612 330P_s C613 330P_s Q501 2sc5227_5 1 3 2 C524 120P_s C540 18P_s L523 10uH_c_1008 C559 100P_s C537 100P_s L607 56nH_c_0603 R501 1K_s C601 0.1U_s C607 0.01U_s 1 2 L606 56nH_c_0603 C526 470P_s L521 270nH_c_1008 1 2 D500 smbj13 2 1 R601 0_s C542 39P_s R602 0_s C525 1000P_s C539 100P_s L511 150nH_c_0603 1 2 U600 la7791t 12 18 5 6 2 4 11 3 1 20 19 17 16 15 14 13 7 10 9 8 /SHDN TXEN VIN+ VIN-VCC1 GND1 NC GND GND GND2 VCC2 NC VOUT+ VOUT-VCM NC DGND SCLK SDA /CS C614 120P_s +C557 470u_10v 1 2 R503 470_s L608 56nH_c_0603 R604 13_s 1% L513 120nH_c_0603 1 2 C605 0.01U_s 1 2 L610 10uH_c_1008 R522 4.7_s L604 56nH_c_0603 R502 470_s S501 Diplexer shield 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 GND GND GND GN D GN D GN D GN D GND GND GND GND GN D GN D GN D GN D GND C555 1000P_s C501 0.1U_s R526 0_s T600 458pt_1087 1 6 2 3 4 C563 100P_s C500 0.1U_s 1 2 C600 1000P_s C611 120P_s C603 6800P_s C536 33P_s C553 1000P_s C533 150P_s C602 0.1U_s L609 56nH_c_0603 R603 13_s 1% R600 26.1_s R504 470_s TUNER1 TDEZ1X002A 7 2 1 5 11 8 6 12 4 9 3 10 13 14 15 16 AS GND RF_IN SCL IF-GN D SDA IF+ +5V OPEN AGC GND GND GND GND GND L519 390nH_c_1008 1 2 L512 390nH_c_1008 1 2 C532 22P_s C554 1000P_s C535 390P_s L520 270nH_c_1008 1 2 R521 470_s C527 2P_s C534 22P_s C609 0.01U_s C558 10U_c C610 0.1U_s L605 56nH_c_0603 C564 100P_s +C617 470u_10v 1 2 C541 82P_s C560 100P_s L500 1uH_c_1008 1 2 L522 27uH_r 1 2 R500 150_s L517 100nH_c_1008 1 2 L516 120nH_c_1008 1 2 C556 0.1U_s 1 2 C606 0.01U_s 1 2 C615 0.01U_s R519 120_s R520 1.2K_s E500

RF_conn

L518 390nH_c_1008 1 2 TUNER_SDA TUNER_SCLK QAM_IF+ QAM_IF-QAM_AGCT OOB_TAP TX_DAC+ TX_DAC-TX_OEN US_CTL_CLK US_CTL_CSB US_CTL_DATA