Agenda. Boolean Algebra: Circuit & Algebraic SimplificaXon. Laws of Boolean Algebra. Boolean Algebraic SimplificaXon Example.

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CS  61C:  Great  Ideas  in  Computer  

Architecture  (Machine  Structures)  

State  and  State  Machines  

Instructors:   Randy  H.  Katz   David  A.  PaGerson  

hGp://inst.eecs.Berkeley.edu/~cs61c/fa10   10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   1  

Agenda  

• 

State  Elements  

• 

Administrivia  

• 

Technology  Break  

• 

Finite  State  Machines  

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Boolean  Algebra:  Circuit  &  

Algebraic  SimplificaXon  

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Laws  of  Boolean  Algebra  

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Boolean  Algebraic  SimplificaXon  

Example  

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Agenda  

• 

State  Elements  

• 

Administrivia  

• 

Technology  Break  

• 

Finite  State  Machines  

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Remember  This?  

Conceptual  MIPS  Datapath  

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   7  

Uses  for  State  Elements  

• 

Place  to  store  values  for  some  amount  of  Xme:  

– Register  files  (like  $1-­‐$31  on  the  MIPS)  

– Memory  (caches,  and  main  memory)  

• 

Help  control  flow  of  informa6on  between  

combina6onal  logic  blocks  

– State  elements  are  used  to  hold  up  the  movement  

of  informaXon  at  the  inputs  to  combinaXonal  logic  

blocks  and  allow  for  orderly  passage  

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   8  

Accumulator  Example  

Want: S=0;

for (i=0;i<n;i++)

S = S + X

i

Why  do  we  need  to  control  the  flow  of  informaXon?  

Assume:  

• 

 Each  X  value  is  applied  in  succession,  one  per  cycle  

• 

 Afer  n  cycles  the  sum  is  present  on  S  

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SUM  

Xi   S  

First  Try:  Does  this  work?  

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No!

   

Reason  #1:  How  to  control  the  next  iteraXon  of  

the  ‘for’  loop?  

Reason  #2:  How  do  we  say:  ‘S=0’?  

Feedback  

Second  Try:  How  About  This?  

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   11  

Rough  

Xming  …  

Register  is  used  to     hold  up  the  transfer     of  data  to  adder  

Time  

Register  Internals  

• 

n  instances  of  a  

“Flip-­‐Flop”  

• 

Flip-­‐flop  

name  because  the  output  flips  and  flops  

between  0  and  1    

• 

D  is  “data”,  Q  is  “output”  

• 

Also  called  “d-­‐type  Flip-­‐Flop”  

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Flip-­‐Flop  Timing  Behavior  (1/2)  

•  Edge-­‐triggered  d-­‐type  flip-­‐flop  

– This  one  is  “posiXve  edge-­‐triggered”  

•  “On  the  rising  edge  of  the  clock,  input  d  is  sampled  and   transferred  to  the  output.  At  other  Xmes,  the  input  d  is  ignored   and  the  previously  sampled  value  is  retained.”  

•  Example  waveforms:  

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Flip-­‐Flop  Timing  Behavior  (2/2)  

•  Edge-­‐triggered  d-­‐type  flip-­‐flop  

– This  one  is  “posiXve  edge-­‐triggered”  

•  “On  the  rising  edge  of  the  clock,  input  d  is  sampled  and   transferred  to  the  output.  At  other  Xmes,  the  input  d  is  ignored     and  the  previously  sampled  value  is  retained.”  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   14  

Accumulator  Revisited    

Proper  Timing  (1/2)  

•  Reset  input  to  register  is  used  to  force  

it  to  all  zeros  (takes  priority  over  D   input)  

•  Si-­‐1  holds  the  result  of  the  ith-­‐1  iteraXon  

•  Analyze  circuit  Xming  starXng  at  the  

output  of  the  register  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   15  

Accumulator  Revisited  

Proper  Timing  (2/2)  

•  reset  signal  shown  

•  Also,  in  pracXce  X  might  not  arrive  to  

the  adder  at  the  same  Xme  as  Si-­‐1  

•  Si  temporarily  is  wrong,  but  register  

always  captures  correct  value  

•  In  good  circuits,  instability  never  

happens  around  rising  edge  of  clk  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   16  

Agenda  

• 

State  Elements  

• 

Administrivia  

• 

Technology  Break  

• 

Finite  State  Machines  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   17  

Agenda  

• 

State  Elements  

• 

Administrivia  

• 

Technology  Break  

• 

Finite  State  Machines  

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Agenda  

• 

State  Elements  

• 

Administrivia  

• 

Technology  Break  

• 

Finite  State  Machines  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   19  

Maximum  Clock  Frequency  

• 

What  is  the  maximum  frequency  of  this  circuit?  

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Max  Delay  =    

Setup  Time  

+  

CLK-­‐to-­‐Q  Delay  

+  

CL  Delay  

Hint:  

Frequency  =  1/Period  

Recap  of  Timing  Terms  

•  Clock  (CLK):  steady  square  wave  that  synchronizes  the  system   •  Setup  Time:  when  the  input  must  be  stable  before  the  rising  

edge  of  the  CLK  

•  Hold  Time:  when  the  input  must  be  stable  a:er  the  rising   edge  of  the  CLK  

•  “CLK-­‐to-­‐Q”  Delay:  how  long  it  takes  the  output  to  change,   measured  from  the  rising  edge  of  the  CLK  

•  Flip-­‐flop:  one  bit  of  state  that  samples  every  rising  edge  of  the   CLK  (posiXve  edge-­‐triggered)  

•  Register:  several  bits  of  state  that  samples  on  rising  edge  of   CLK  or  on  LOAD  (posiXve  edge-­‐triggered)  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   23  

Another  Great  Idea:  

Finite  State  Machines  (FSM)  

• You  may  have  seen  FSMs  

in  other  classes  

• Same  basic  idea  

• FuncXon  can  be  

represented  with  a  “state  

transiXon  diagram”  

• With  combinaXonal  logic  

and  registers,  any  FSM  can  

be  implemented  in  

hardware  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   24  

Example:  3  Ones  FSM  

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Draw  the  FSM  …  

FSM  to  detect  the  occurrence  of  3  consecuXve  1’s  in  the  Input  

Assume  state  transiXons  are  controlled  by    

the  clock:  On  each  clock  cycle  the  machine  checks  the  inputs  and   moves  to  a  new  state  and  produces  a  new  output  …  

=!

Hardware  ImplementaXon  of  FSM  

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+!

Register  needed  to  hold  a  representaXon  of  the  machine’s  state.   Unique  bit  paGern  for  each  state.  

CombinaXonal  logic  circuit  is   used  to  implement  a  funcXon   maps  from  present  state  and  

input  to  next  state  and  output.   The  register  is  used  to  break  the  feedback   path  between  NS  and  PS,  controlled  by  the  clock  

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Hardware  for  FSM:    

CombinaXonal  Logic  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   27   1" 00" 1" 10" 0" 00" 0" 10" 0" 10" 1" 01" 0" 00" 0" 01" 0" 01" 1" 00" 0" 00" 0" 00" Output" NS" Input" PS"

Truth  table  …  

Next  lecture  we  will  discuss  the  detailed  implementaXon,  but   for  now  can  look  at  its  funcXonal  specificaXon,  truth  table  form  

General  Model  for  Synchronous  

Systems  

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   28  

• CollecXon  of  CL  blocks  separated  by  registers  

• Registers  may  be  back-­‐to-­‐back  and  CL  blocks  may  be  back-­‐to-­‐back   • Feedback  is  opXonal  

• Clock  signal(s)  connects  only  to  clock  input  of  registers  

Fall  2010  -­‐-­‐  Lecture  #22  

system

datapath control

state

registers combinational logic multiplexer comparator code registers register logic switching networks

Design  Hierarchy  

10/21/10   29  

Summary  

• 

State  elements  are  used  to:  

– Build  memories  

– Control  the  flow  of  informaXon  between  other  

state  elements  and  combinaXonal  logic  

• 

D-­‐flip-­‐flops  used  to  build  registers  

• 

Clocks  tell  us  when  D-­‐flip-­‐flops  change  

– Setup  and  Hold  Xmes  important  

• 

We  pipeline  long-­‐delay  CL  for  faster  clock  

• 

Finite  State  Machines  extremely  useful  

– You’ll  see  them  again  150,  152,  164,  172…  

Figure

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