# Agenda. Boolean Algebra: Circuit & Algebraic SimplificaXon. Laws of Boolean Algebra. Boolean Algebraic SimplificaXon Example.

## Full text

(1)

### State  and  State  Machines

Instructors:   Randy  H.  Katz   David  A.  PaGerson

hGp://inst.eecs.Berkeley.edu/~cs61c/fa10   10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   1

### Finite  State  Machines

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   2

### Algebraic  SimpliﬁcaXon

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   3

### Laws  of  Boolean  Algebra

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   4

### Example

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   5

(2)

### Conceptual  MIPS  Datapath

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   7

### blocks  and  allow  for  orderly  passage

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   8

i

### Afer  n  cycles  the  sum  is  present  on  S

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   9

Xi   S

### First  Try:  Does  this  work?

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   10

Feedback

### Second  Try:  How  About  This?

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   11

### Xming  …

Register  is  used  to     hold  up  the  transfer     of  data  to  adder

Time

(3)

### Flip-­‐Flop  Timing  Behavior  (1/2)

•  Edge-­‐triggered  d-­‐type  ﬂip-­‐ﬂop

– This  one  is  “posiXve  edge-­‐triggered”

•  “On  the  rising  edge  of  the  clock,  input  d  is  sampled  and   transferred  to  the  output.  At  other  Xmes,  the  input  d  is  ignored   and  the  previously  sampled  value  is  retained.”

•  Example  waveforms:

10/22/10   Fall  2010  -­‐-­‐  Lecture  #23   13

### Flip-­‐Flop  Timing  Behavior  (2/2)

•  Edge-­‐triggered  d-­‐type  ﬂip-­‐ﬂop

– This  one  is  “posiXve  edge-­‐triggered”

•  “On  the  rising  edge  of  the  clock,  input  d  is  sampled  and   transferred  to  the  output.  At  other  Xmes,  the  input  d  is  ignored     and  the  previously  sampled  value  is  retained.”

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   14

### Proper  Timing  (1/2)

•  Reset  input  to  register  is  used  to  force

it  to  all  zeros  (takes  priority  over  D   input)

•  Si-­‐1  holds  the  result  of  the  ith-­‐1  iteraXon

•  Analyze  circuit  Xming  starXng  at  the

output  of  the  register

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   15

### Proper  Timing  (2/2)

•  reset  signal  shown

•  Also,  in  pracXce  X  might  not  arrive  to

the  adder  at  the  same  Xme  as  Si-­‐1

•  Si  temporarily  is  wrong,  but  register

always  captures  correct  value

•  In  good  circuits,  instability  never

happens  around  rising  edge  of  clk

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   16

### Finite  State  Machines

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   17

(4)

### Finite  State  Machines

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   19

### What  is  the  maximum  frequency  of  this  circuit?

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   20

### CL  Delay

Hint:

Frequency  =  1/Period

### Recap  of  Timing  Terms

•  Clock  (CLK):  steady  square  wave  that  synchronizes  the  system   •  Setup  Time:  when  the  input  must  be  stable  before  the  rising

edge  of  the  CLK

•  Hold  Time:  when  the  input  must  be  stable  a:er  the  rising   edge  of  the  CLK

•  “CLK-­‐to-­‐Q”  Delay:  how  long  it  takes  the  output  to  change,   measured  from  the  rising  edge  of  the  CLK

•  Flip-­‐ﬂop:  one  bit  of  state  that  samples  every  rising  edge  of  the   CLK  (posiXve  edge-­‐triggered)

•  Register:  several  bits  of  state  that  samples  on  rising  edge  of   CLK  or  on  LOAD  (posiXve  edge-­‐triggered)

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   23

### hardware

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   24

### Example:  3  Ones  FSM

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   25

### Draw  the  FSM  …

FSM  to  detect  the  occurrence  of  3  consecuXve  1’s  in  the  Input

Assume  state  transiXons  are  controlled  by

the  clock:  On  each  clock  cycle  the  machine  checks  the  inputs  and   moves  to  a  new  state  and  produces  a  new  output  …

## =!

### Hardware  ImplementaXon  of  FSM

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   26

## +!

Register  needed  to  hold  a  representaXon  of  the  machine’s  state.   Unique  bit  paGern  for  each  state.

CombinaXonal  logic  circuit  is   used  to  implement  a  funcXon   maps  from  present  state  and

input  to  next  state  and  output.   The  register  is  used  to  break  the  feedback   path  between  NS  and  PS,  controlled  by  the  clock

(5)

### CombinaXonal  Logic

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   27   1" 00" 1" 10" 0" 00" 0" 10" 0" 10" 1" 01" 0" 00" 0" 01" 0" 01" 1" 00" 0" 00" 0" 00" Output" NS" Input" PS"

### Truth  table  …

Next  lecture  we  will  discuss  the  detailed  implementaXon,  but   for  now  can  look  at  its  funcXonal  speciﬁcaXon,  truth  table  form

### Systems

10/21/10   Fall  2010  -­‐-­‐  Lecture  #23   28

• CollecXon  of  CL  blocks  separated  by  registers

• Registers  may  be  back-­‐to-­‐back  and  CL  blocks  may  be  back-­‐to-­‐back   • Feedback  is  opXonal

• Clock  signal(s)  connects  only  to  clock  input  of  registers

Fall  2010  -­‐-­‐  Lecture  #22

system

datapath control

state

registers combinational logic multiplexer comparator code registers register logic switching networks

10/21/10   29

Updating...

## References

Updating...

Related subjects :