Arquitectura Virtex
Compuesta de dos elementos
principales configurables : CLBs y IOBs. Los CLBs se interconectan a través de una matriz general de routeado (GRM).
● Posse una intefaz VersaRing que
proporciona recursos adicionales de interconexión a la periferia del dispositivo.
● Existen otoros circuitos que se
conectan a la GRM:
1) Bloques dedicados a memoriaas de 4K. 2) Relojes DLL para la
distribución y compensación de
IOB y
señales
soportadas
CLBs y LCs
● Each Virtex CLB contains four Lcs, organized in two similar slices, as shown in
Figure.
● The basic building block of the Virtex CLB is the logic cell (LC). An LC includes a
4-input function generator, carry logic, and a storage element.
● The output from the function generator in each LC drives both the CLB output and
Virtex-4 Overview Module 7
SONET
•
Virtex-4 RocketIO™
transceivers
–
Full-duplex serial
transceiver blocks with
integrated SERDES and
Clock and Data Recovery
(CDR)
•
622 Mbps to >10 Gbps
operation
–
Widest Range of
Operation
•
Compatible with Virtex-II
Pro
•
Supports chip-to-chip,
backplane, chip-to-optics
The Most
Advanced
Serial I/O
Virtex-4 Overview Module 8
Support
Support
Networking
Networking
Telecom
Telecom
Computing
Computing
Storage
Storage
Video
Video
0.622 1.0 2.0 3.0 5.0 10.0 11.0 OC-12 OC-12 OC-48 OC-48 GbEGbE XAUIXAUI
10GbE 10GbE CEI (OIF) CEI (OIF) SATA3 SATA3 SATA2 SATA2 SATA SATA 1GFC 1GFC 2GFC2GFC PCIE PCIE HD-SDI HD-SDI SATA SATA GbE GbE 1.45 1.25 2.5 1.5 3.0 0.622 2.488 3.125 1.25 6.25 1.5 3.0 6.0 1.06 2.12 10GFC 10GFC 6.0 10.519 SATA2 SATA2 Rate (Gb/s) CEI (OIF) CEI (OIF) 4GFC 4GFC 4.25 8GFC 8GFC 8.5
Serial I/O Challenges
10.313 11G OBSAI OBSAI 0.768-1.5CPRICPRI 0.622 - 2.5 PCIE Gen2 PCIE Gen2 5-6
Virtex-4 Overview Module 9
World-Class Clocking
●High-performance
●Up to 500 MHz system
clock
●Up to 700 MHz source
synchronous clock
●Powerful DCM clocking
●Zero-delay buffer
●Phase-shift control
●Frequency synthesis
●More resources
●Up to 20 DCMs
●32 global clocks
Virtex-4 Overview Module 10
Fast and Flexible BRAM
•
Enhanced architecture for higher
performance
–
500 MHz performance
•
Optional programmable FIFO logic
–
Saves logic resources
–
500 MHz FIFO performance
•
Tunable Block Structure
–
Scalable and efficient
memory utilization
–
Design compatible with
Virtex-II Pro
Virtex-4 Overview Module 11
Virtex-4 Secure Chip AES Provides
Maximum Design Security
•
Bitstreams encrypted with
256-bit AES algorithm
•
Cryptographic keys
automatically erased upon
malicious tampering
•
Part of standard design
flow
Among FPGA vendors, only Xilinx meets U.S.
Among FPGA vendors, only Xilinx meets U.S.
Government standards for secure module
Government standards for secure module
design
design
Virtex-4 Overview Module 12
Virtex-4 Clock Management:
Powerful
Solutions
●Simplified system design
●
Abundant resources
●
Application-targeted features
●
Comprehensive software support
●
Increased system performance
●
Lower jitter and duty cycle distortion
●500 MHz clock generation and control
Clocking features, performance, and flexibility
Clocking features, performance, and flexibility
unmatched by any other FPGA
Virtex-4 Overview Module 13
Next Generation
48 48 48 Subtract P RSTA 18 PCIN 0 PCOUT C BCOUT BCIN B CarryIn 0 0 72 RSTM A:B 36 Y Z OpMode 7 18 48 48 17-bit shift 17-bit shift 48 1 0 0 1 36 36 18 X CEM CE MREG D Q RSTP CEP CE PREG D Q CEB CE BREG D Q CEA CE AREG D Q RSTB A 2-Deep 2-DeepVirtex-4 Overview Module 14
Integrated PowerPC 405
World’s Most Popular Embedded Processor Architecture
•
High-performance
– 680 DMIPS@ 450MHz
•
Low power
– 0.29mW/MHz
•
2
ndgeneration FPGA with PowerPC
405
– Preserves HW and SW IP
– CoreConnect™ bus architecture
– Full array of system-level IP
•
New APU interface
– Provides direct access from FPGA fabric to PowerPC core
– Easy microcontroller and coprocessor support
Virtex-4 Overview Module 15
New Tri-Mode Ethernet MAC
●
Fully integrated Ethernet Media
Access Controller (EMAC)
● 10/100/1000 Mbps
● 2 or 4 cores per Virtex-4 FX device
●
UNH-Compliant
●
Use with PowerPC or
stand-alone
●
Key benefits
● Saves up to 4000 logic cells
per Ethernet MAC
● Implement single-chip
1000 Base-X Ethernet
● Great for network management
or remote FPGA monitoring
Processor Processor Block Block Phy Phy Interface Interface Phy Phy Interface Interface Client Client Interface Interface Client Client Interface Interface Statistics Statistics Interface Interface Statistics Statistics Interface Interface
Virtex-4 Overview Module 16
Three Virtex-4 Platforms
Resource Resource 14-200K LCs 14-200K LCs Logic Memory DCMs DSP Slices SelectIO RocketIO PowerPC Ethernet MAC
