Voltage Divider Bias

(1)

Voltage Divider Bias

ENGI 242

ELEC 222

BJT Biasing 3

For the Voltage Divider Bias Configurations

• Draw Equivalent Input circuit

• Draw Equivalent Output circuit

• Write necessary KVL and KCL Equations

• Determine the Quiescent Operating Point

– Graphical Solution using Load lines

– Computational Analysis

(2)

23 February 2005 ENGI 242/ELEC 222 3

Voltage-divider bias configuration

Voltage Divider Input Circuit Approximate Analysis

This method is valid only if R2

≤

.1

β

RE

Under these conditions R

E

does not significantly load R

2

and it may be ignored:

I

_B

<< I

₁

and I

₂

and I

₁

≅

I

₂

Therefore:

We may apply KVL to the input, which gives us:

-VB

+ VBE

+ IE

RE

= 0

Solving for I

E

we get:

2 B CC

1 2

R

V = V

R +R

⎛

⎞

⎜

⎟

⎝

⎠

B BE E

E

V - V

I =

(3)

This method is always valid must be used when R

2

> .1

β

RE

Perform Thevenin’s Theorem

Open the base lead of the transistor, and the Voltage Divider bias circuit is:

Calculate R

TH

2 TH CC

1 2

R

V = V

R +R

⎛

⎞

⎜

⎟

⎝

⎠

We may apply KVL to the input, which gives us:

-VTH

+ IB

RTH

+ VBE

+ IE

RE

= 0

Since I

E

= (

β

+ 1) I

B TH

TH E BE E E

TH BE E

E

TH E

Solving for I we obtain

R

-V + I

+ V + I R = 0

+

1 V - V

I =

R

_{+ R}

+ 1

:

β

(4)

Determining V

TH

⎛

⎞

⎜

⎟

⎝

⎠

2 TH CC

1 2

R

V = V

R + R

Determining R

TH

1 2

TH

1 2

R R

R =

(5)

The Thévenin Equivalent Circuit

Note that V

E

= V

B

– V

BE

and I

E

= (

β

+ 1)I

B

Input Circuit Exact Analysis

We may apply KVL to the input, which gives us:

-V

TH

+ I

B

R

TH

+ V

BE

+ I

E

R

E

= 0

Since I

E

= (

β

+ 1) I

B TH

TH E BE E E

TH BE E

E

TH E

Solving for I we obtain

R

-V + I

+ V + I R = 0

+

1 V - V

I =

R

+ R

+

1 :

β

(6)

Collector-Emitter Loop

Collector-Emitter (Output) Loop

Applying Kirchoff’s voltage law:

- V

CC

+ I

C

R

C

+ V

CE

+ I

E

R

E

= 0

Assuming that

I

E

≅

I

C

and solving for V

CE

:

Solve for V

E

:

V

E

= I

E

R

E

Solve for V

C

:

V

C

= V

CC

- I

C

R

C

or

V

C

= V

CE

+ I

E

R

E

Solve for V

B

:

V

B

= V

CC

- I

B

R

B

or

V

B

= V

BE

+ I

E

R

E CC CE C

C E

V - V

I =

(7)

Voltage Divider Bias Example 1

V

CC

= 22V

R

1

= 39k

Ω

R

2

= 3.9k

Ω

R

C

= 10k

Ω

R

E

= 1.5k

Ω

β

= 140

Voltage Divider Bias Example 2

V

CC

= 18V

R

1

= 39k

Ω

R

2

= 8.2k

Ω

R

C

= 3.3k

Ω

R

E

= 1k

Ω

(8)

Voltage Divider Bias Example 3

V

CC

= 16V

R

1

= 62k

Ω

R

2

= 9.1k

Ω

R

C

= 3.9k

Ω

R

E

= .68k

Ω

β

= 80

Design of CE Amplifier with Voltage Divider Bias

1. Select a value for V

CC

2. Determine the value of

β

from spec sheet or family of curves

3. Select a value for I

CQ

4. Let V

CE

= ½ V

CC

(typical operation

,

0.4 V

CC

≤

V

C

≤

0.6 V

CC

)

5. Let V

E

= 0.1 V

CC

(for good operation

,

0.1 V

CC

≤

V

E

≤

0.2 V

CC

)

6. Calculate R

E

and R

C

7. Let R

2

≤

0.1 β

R

E

(for this calculation, use low value for

β

)

8. Calculate R

1

⎛

⎞

⎜

⎟

⎝

⎠

CC B 1 2

B

V - V

R = R

(9)

CE Amplifier Design

• Design a Common Emitter Amplifier with Voltage Divider

Bias for the following parameters:

V

CC

= 24V

I

C

= 5mA

V

E

= .1V

CC

V

C

= .55V

CC

β

= 135

(10)

CE Amplifier Design

(11)

Collector Feedback Bias

ENGI 242

ELEC 222

BJT Biasing 4

For the Collector Feedback Bias Configuration:

• Draw Equivalent Input circuit

• Draw Equivalent Output circuit

• Write necessary KVL and KCL Equations

• Determine the Quiescent Operating Point

– Graphical Solution using Loadlines

– Computational Analysis

(12)

DC Bias with Collector (Voltage) Feedback

Another way to improve the stability of a bias circuit is to add a feedback path

from collector to base

In this bias circuit the Q-point is only slightly dependent on the transistor

β

Base – Emitter Loop Solve for I

B

Applying Kirchoff’s voltage law: -VCC

+ IC

′

RC

+ IBRB

+ VBE

+ IERE

= 0

Note: IC

′

= IE

= IC + IB

Since I

E

= (

β

+ 1) I

B

then: -VCC

+ (

β

+ 1)IB

RC

+ IBRB

+ VBE

(

β

+ 1)IBRE

= 0

Simplifying and solving for I

_B

:

CC BE

B

V - V

(13)

Applying Kirchoff’s voltage law: -VCC

+ IERC

+ IBRB

+ VBE

+ IERE

= 0

Since I

E

= (

β

+ 1) I

B

then:

Simplifying and solving for I

_E

:

β

B

CC E C E BE E E

CC BE E

B

C E

R

-V + I R + I

+ V + I R = 0

( + 1)

V - V

I =

R

+ (R + R )

(

β

+ 1)

Base – Emitter Loop Solve for I

E

(14)

Network Example

(15)

Design of CE Amplifier with Collector Feedback Bias

1. Select a value for V

CC

2. Determine the value of

β

from spec sheet or family of curves

3. Select a value for I

EQ

4. Let V

CE

= ½ V

CC

(typical operation

,

0.4 V

CC≤

V

C

≤

0.6 V

CC

)

5. Let V

E

= 0.1 V

CC

(for good operation

,

0.1 V

CC≤

V

E

≤

0.2 V

CC

)

6. Calculate R

E

, R

C

and R

B

E CC

CC CQ CC CC

C

E E

CC E C BE E E

B

V = .1V

V - V

V - .6V

R =

=

;

I

V - I R - V - I R

R =

;

I

CC E E CC C E

CC E C E B

.1V

R =

I

.4V

R =

I

V - I (R + R ) - 0.7

R =

V

(16)

Common Emitter Bias

with Dual Supplies

(17)

Voltage Divider Bias with Dual Power Supply

Input Circuit Find V

TH

and R

TH

⎛

⎞

⎛

⎞

⎜

⎟

⎜

⎟

⎝

⎛

⎞

⎜

⎟

⎝

⎠

⎛

⎞

⎜

⎟

_⎠

⎝

⎠

⎝

⎠

2 1

TH CC EE

1 2 2 TH1 CC 1 1 2 2 EE 1 TH2 EE 1 2 TH 1 2 TH 1 H1 TH 2 T 2

R

V = V

R + R

(Note V is negative)

R

V = - V

R + R

V =

R

V = V

- V

R + R

R R

R =

R +

V + V

R

Voltage Divider Bias with Dual Power Supply

Output Circuit

≅

CC C C CE E E EE

E C

C

CC EE CE C

C E

CC EE CE C

E C

E

V + V - V

I =

R +

-V + I R + V + I R - V = 0

If we assume I I (when

β

> 100)

If we use the exact solution I =

α

R

V + V - V

I =

R

I

β

+

α

(18)

Voltage Divider Bias with Dual Power Supply

(19)

PSpice Bias Point Simulation

(20)

PSpice Simulation for DC Sweep

The response of V

CE

demonstrates that it

reaches a peak value near the Q point and

then decreases

The response of V

C

demonstrates rises rapidly towards

the Q Point and then increases gradually towards a

maximum value

(21)

PSpice Simulation for AC Sweep