Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis

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August 17, 2006

Micron

MT29F2G08AAB 2 Gbit

NAND Flash Memory Structural Analysis

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Structural Analysis

Table of Contents 1 Overview

1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary

2 Device Overview 2.1 Package and Die 2.2 Die Features

3 Process Analysis

3.1 General Device Structure 3.2 Bond Pads

3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts

3.6 Peripheral Low-Voltage Transistors 3.7 Peripheral High-Voltage Transistors 3.8 Flash Array Transistors and Poly 3.9 Isolation

3.10 Wells and Substrate

4 Memory Cell Analysis 4.1 Plan-View Analysis

4.2 Cross-Sectional Analysis – Parallel to Bit Line 4.3 Cross-Sectional Analysis – Parallel to Word Line

5 Materials Analysis

5.1 TEM-EDS Analysis of Dielectrics

5.2 TEM-EDS Analysis of Metals

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Structural Analysis

6 Critical Dimensions

6.1 Horizontal Dimensions

6.2 Vertical Dimensions

Report Evaluation

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Overview 1-1

1 Overview

1.1 List of Figures

2 Package and Die Analysis 2.1.1 Package Top Photograph 2.1.2 Package Bottom Photograph 2.1.3 Plan-View Package X-Ray 2.1.4 Die Photograph

2.1.5 Die Markings 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Bond Pads

3 Process Analysis

3.1.1 General Device Structure 3.1.2 Die Edge Overview 3.1.3 Die Seal Structure

3.1.4 Detail of Poly Stack at Die Seal 3.2.1 Bond Pad Overview

3.2.2 Bond Pad – Edge 3.2.3 Bond Pad – Center 3.3.1 Passivation Overview 3.3.2 Passivation 2 – TEM 3.3.3 IMD 1

3.3.4 IMD 1-1 – TEM 3.3.5 PMD

3.4.1 Minimum Pitch Metal 2 3.4.2 Metal 2 Profile – TEM 3.4.3 Minimum Pitch Metal 1

3.4.4 Minimum Pitch Metal 1 – TEM 3.4.5 Detail of Metal 1 Barrier – TEM 3.5.1 Minimum Pitch Vias

3.5.2 Poly 4 Contact – Bit Line Contact

3.5.3 Detail of Metal 1 to Poly 4 Contact

3.5.4 Poly 3 Contact – Source Line Contact

3.5.5 Detail of Metal 1 to Poly 3 Contact

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Overview 1-2

3.5.6 Minimum Pitch Contacts to Poly 2 3.5.7 Contact to Poly 1

3.5.8 Minimum Pitch Contacts to N

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Diffusion 3.5.9 Contacts to P

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Diffusion

3.6.1 Minimum Gate Length Peripheral NMOS Transistors

3.6.2 Detail of Minimum Gate Length Peripheral NMOS Transistors 3.6.3 Plan-View of Peripheral Transistor Layout

3.6.4 Peripheral Transistor Gate – Gate Width Direction 3.7.1 Peripheral HVNMOS Transistor

3.7.2 Detail of Peripheral HVNMOS Transistor – S/D Contact 3.7.3 Peripheral HVPMOS Transistor

3.7.4 Detail of Peripheral HVPMOS Transistor – S/D Contact 3.7.5 HVMOS Transistor – TEM

3.7.6 Detail of HVMOS Transistor – TEM 3.7.7 TEM Lattice Image

3.8.1 Minimum Pitch Floating Gate Array Transistors 3.8.2 Minimum Pitch Floating Transistors on STI

3.8.3 Source Line Select Transistor and Storage Transistors – TEM 3.8.4 Detail of Floating Gate Stroage Transistor – TEM

3.8.5 ONO Interpoly Dielectric – TEM 3.8.6 ONO at Gate Stack Edge – TEM

3.8.7 Storage Transistor Gate Dielectric – TEM

3.8.8 Storage Transistor (Gate Width Direction) – TEM 3.9.1 Stacked Poly Over STI

3.9.2 Minimum Width STI

3.9.3 STI/Gate Oxide Interface – TEM 3.10.1 Array N-Well

3.10.2 SCM of Array Wells

3.10.3 SRP Profile of Array Well Structure 3.10.4 SRP Profile of Periphery P-Well

4 Memory Cell Analysis

4.1.1 Die Photograph – Die Deprocessed to Poly 4.1.2 Plan-View Word Line Drivers

4.1.3 Plan-View Detail of Word Line Drivers and Edge of Array 4.1.4 Plan-View Page Buffer/Write Drivers

4.1.5 Plan-View Detail of Write Drivers and Edge of Array

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4.1.6 Plan-View Detail Edge of Array 4.1.7 Plan-View Detail of Word Lines 4.2.1 Flash Array Parallel to Bit Line

4.2.2 Bit Line Contact to Flash Array – TEM

4.2.3 Detail of Floating Gate Storage Transistors – TEM 4.3.1 Floating Gates

4.3.2 Detail of Floating Gates 4.3.3 Bit Line Select Line

4.3.4 Source Line – Between Blocks

5 Materials Analysis

5.1.1 TEM-EDS Spectrum of Passivation 3 5.1.2 TEM-EDS Spectrum of Passivation 2

5.1.3 TEM-EDS Spectrum of Passivation 1 (Metal 2 ARC) 5.1.4 TEM-EDS Spectrum of ILD 1-3

5.1.5 TEM-EDS Spectrum of ILD 1-2

5.1.6 TEM-EDS Spectrum of ILD 1-1 (Metal 1 ARC) 5.1.7 TEM-EDS Spectrum of PMD 2

5.1.8 TEM-EDS Spectrum of PMD 1

5.1.9 TEM-EDS Spectrum of Sidewall Spacer

5.2.1 TEM-EDS Spectrum of Metal 2 Adhesion Layer 5.2.2 TEM-EDS Spectrum of Metal 1 Adhesion Layer 5.2.3 TEM-EDS Spectrum of Gate Silicide

6 Critical Dimensions

1.2 List of Tables

1.5.1 Device Summary 1.6.1 Process Summary 3.3.1 Dielectric Thicknesses

3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions

3.6.1 Transistor and Polycide Dimensions

Overview 1-3

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