Customer Use Model for 90 nm and 65 nm Equivalence Checking
Application Note 5047
Introduction
Avago Technologies performs equivalence checking throughout the entire design methodology flow. Avago performs checks at the block level, up and down the hierarchy, and at the full-chip level.
Avago Technologies Flow
Avago Technologies performs equivalence checking at both the block and full-chip levels. Block-to-block check- ing occurs at many steps in the design flow as every change to the netlist is checked. The lower level hierar- chical blocks are black-boxed to allow for independent verification of each block. This process also allows the designer to proceed with verification even though other blocks in the hierarchy are not ready. It also helps with debug isolation and enables quick design feedback. The block-to-block verification is performed with Synopsys Formality or Cadence Conformal.
Once all blocks on the chip are complete, Avago Tech- nologies performs a full-chip equivalence check using Cadence Conformal’s hierarchical approach. This process does not exclude any child modules except behavioral models such as RAMs and PLLs. This process applies constraints (such as turning off test mode) at the chip level to ensure propagation of TAP reset and consistency of constraints applied to hierarchical interfaces. Depend- ing on the engagement model with the customer and whether or not Avago Technologies receives RTL or a synthesized netlist, Avago Technologies will run full-chip equivalence checking in one of two ways. When RTL is provided by the customer, Avago Technologies will use a two- step approach: 1) RTL to synthesized gates 2) syn- thesized gates to Final netlist. Avago Technologies has determined that when using Cadence Conformal, this two-step approach is preferable to a direct RTL to final netlist comparison. In cases in which Avago receives a synthesized netlist, Avago will only perform a synthe- sized netlist to final netlist comparison.
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The following are Avago Technolgies-specific information:
• List of constraints such as placing TAP in reset mode.
Constraints are used to place chip in a particular state. For example, the test access port (TAP) needs to be placed in the reset state in order for equivalence checking to pass. Typically, the TAP circuitry is instan- tiated in the final gate netlist by Avago Technologies and the RTL does not include the TAP. To avoid mis- matches due to differences, the TAP must be placed in reset mode. There are other constraints that need to be applied, such as clock bypass circuitry, etc. The runscript (dofile) will have the exact name (sometimes chip specific) for all these constraints.
• List of black boxes
Conformal cannot handle behavioral models such as memories and analog models. Avago advises black- boxing these models to increase Conformal perfor- mance.
Typically, these models include RAMs, Register Arrays, FIFOs, PLL/DLL and SerDes. Since the modules names are design specific, Avago Technologies will provide the list of modules that need to be black- boxed.
• List of renaming rules
Renaming rules help Conformal map the key points quickly. Typically, renaming rules are dictated by
“change names” and optimization during synthesis as well as post-synthesis hierarchy manipulation.
Customer Use Model
Avago Technologies recommends that its customers run equivalence checking using the full chip model to enable complete, independent and efficient verifica- tion. The customer use model is very similar to Avago Technologies full chip equivalence check model. Avago Technologies’ will deliver the run script (dofiles) and the log files created during Avago Technologies full-chip equivalence checking run. The customer can then choose to inspect the setup and log files and determine whether an independent customer- performed equivalence check is necessary.
The following sections in this document outline Avago Technologies deliverables and Avago Technologies-spe- cific information to enable quick and efficient Cadence Conformal runs.
Avago Technologies Deliverables
The following are deliverables from Avago Technologies to enable customer complete equivalence checking:
• Synthesized gates netlist (chipname_synth.v) If the design handoff includes RTL- handoff, Avago Tech- nologies delivers the synthesized netlist.
• Final Netlist (chipname_final.v) This netlist is the art- work- extracted verilog gates netlist.
• Logfile and report files (rtl2synth.log, rtl2synth.*.rpt, synth2final.log...) Avago Technologies delivers the output (log file) of Avago Technologies Full Chip Verplex hierarchical equivalence check run. Avago Technologies also delivers the report files generated during the run, such as “design data” and rule checks.
• Dofile (rtl2synth.dofile, synth2final.dofile) Avago delivers the dofile used to run Full chip Conformal hierarchical equivalence check. This file includes all commands necessary to run Conformal for Avago Technologies’ design methodology.
Running Cadence Conformal
The following steps are required for efficient Cadence Conformal run using Avago Technologies’ libraries and meth- odology.
1. Set the default options for Conformal.
set flatten model -latch_fold // converts two latches in LSSD to a dff set flatten model -seq_fold_inv // folds master/slave w/o inversion set flatten model -seq_constant // converts dff o/p to 0/1 if i/p is 0/1 set flatten model -gated_clock // remodels gate clock logic for dff
set mapping method -nophase // no inverse mapping (simplest) set mapping method -sensitive // names are case sensitive
set mapping method -nobbox_name_match // allows easier BlackBox mapping
2. Define analog models such as PLL, behavioral models and RAMs as black-boxes to increase Conformal performance performance.
add notranslate module <module name> -both
3. Add the naming and renaming rules for Conformal. The following naming rules are common to all chips. Avago Technologies will provide additional renaming rules that are specific to each chip.
set naming rule “_” “A” -array -golden set naming rule “_” “_” -parameter -golden
4. Read in the libraries. Define DFF_MODEL for Avago Technologies libraries.
read library -define DFF_MODEL -define functional <file location> -both
5. Read the design files for golden and revised. Avago Technologies recommends running RTL to synthesized gates and synthesized gates to final netlist.
read design <list of files> -root <root module> -golden read design <list of files> -root <root module> -revised
6. Add the constraints. Avago Technologies recommends placing TAP in reset mode, bypassing clock circuitry and turning off test mode.
add pin constraint 0 TEST__TRST_L -both // for TAP
add pin constraint 1 atpg_mode_L pad_tri_L -both // for TAP, pads add instance constraint 0 <clock path > -both // for Clock Bypass mode
7. Avago Technologies will also provide the list of modules that need to be uniquified for hierarchical comparison.
uniquify <module name>
8. Run Conformal in hierarchical mode.
write hier_compare dofile chip_hier.do -constraint -replace dofile chip_hier.do
report hier_compare result -all -usage
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Example DOFILE
The following is a snippet of the dofile typically used in Avago Technologies flow.
set log file rtl2gates.log -replace // Hierarchy naming characters set naming rule “_” -hier -golden //array delimiter property:
set naming rule “_” “A” -array -golden // “[]” delim chars: rtl // *****************************************************
// Read in models
// *****************************************************
// Read in Golden model
read library MODEL_FILES/FCLIB13_10_verilog.formal.lib \ MODEL_FILES/FCLIB13_10_verilog.simulation.lib \
-define DFF_MODEL -golden -replace read design rtl.v -root bib -golden -replace // Read in Revised model
read library gates_lib.in \ MODEL_FILESFCLIB13_10_verilog.formal.lib \ MODEL_FILES/FCLIB13_10_verilog.simulation.lib
-define DFF_MODEL -revised -replace -extract read design gates.v -root bib -revised -replace
//******************************************************
// Constrain models
//******************************************************
del black box -all -both // for interactive reuse del pin constraint -all -golden // for interactive reuse ...
...add pin constraint 0 TEST__TRST_L -both // Using properties to control model flattening:
add inst constraint 0 run_bist_dly_reg -golden ...
...add notranslate module cram_bp2_w256_x88_m4_d8_x1y1 add notranslate module ra_8x200_1rw
...
//**************************************************************
// Compile model
//**************************************************************
set screen display off
report design data -verbose -both > rtl2gates.design.rpt set screen display on
set flatten model -latch_fold // compile options set flatten model -seq_fold_inv // folds master/slave // w/o inversion
set flatten model -seq_constant set flatten model -gated_clock
//********************************************************
// Mapping
//********************************************************
// mapping method defaults
set mapping method -nophase // no inverse mapping
set mapping method -name only // try direct name mapping first set mapping method -sensitive // names are case sensitive // allows easier BlackBox mapping
set mapping method -nobbox_name_match // Renaming rules
add renam rule dff_prim_rule1 /ZT1SNOD.*$ “” -revised add renam rule dff_prim_rule2 /ZT1SINOD.*$ “” -revised ...
For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved.
AV02-1703EN - July 20, 2010 ...
write hier_compare dofile rtl2gates.hier.do -constraint -replace dofile rtl2gates.hier.do
report hier_compare result -all -usage > rtl2gates.results.rpt // Report files
report pin constraints -all -both > rtl2gates.constraints.rpt report pin equivalences -all -both > rtl2gates.pinequiv.rpt ...report tied signals -net -class full -both > rtl2gates.tied.rpt
report floating signals -undriven -full -both > rtl2gates.undriven.rpt report clock -both > rtl2gates.clocks.rpt
// report modelling messages
report messages -model > rtl2gates.model.msg.rpt set screen display on
...
...report environment > rtl2gates.env.rpt
report rule check -all -verb -full -both > rtl2gates.rulecheck.rpt // report rule checks report messages -compare > rtl2gates.cmp.msg.rpt // report compare messages set screen display on
report stat > rtl2gates.stat.rpt // report compare summary report stat // report compare summary
usage // show time/memory use exit
