Power Efficient Control Unit Design Using 40nm Field Programmable Gate Array

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Power Efficient Control Unit Design Using 40nm Field Programmable Gate Array

Srishti Priya Chaturvedi¹, Aryan Kaushik², Vidhu Baggan³

1,2,3

Chitkara University Institute of Engineering and Technology Chitkara University, Punjab, India

Abstract

In today’s modern generation, people are living in a digital world where each and every thing is interconnected and communicating. This generation is living in a technology dependent world. With the enlargement of population, the resources of energy are reducing. Therefore, there is a demand of developing efficient systems. Energy efficiency is a major concern and an active research area now a day. Therefore, this paper introduces an energy efficient Control Unit Circuit implemented with Field Programmable Gate Array (FPGA) Virtex-6 and Input/output Standard This research work has not only considered the transmitted power at every transmission node but also examined the consumed processing power on every reception node to analyze the overall performance of the circuit. This CU circuit is capable enough to perform its fundamental task with low power consumption. This research work has utilized FPGA, along with the I/O Standard and found that the power consumption level for the CU of a computer's Central Processing Unit (CPU) has reduced significantly and furthermore, Stub Series Terminated Logic (SSTL) I/O Standard has been used for input and output power matching. FPGA is known for itshigh cost but based on the previous research work, it is also observed to be an efficient circuit. This work used a complete family of I/O Standard and each member’sperformance has been observed very carefully. For the coding purpose Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used which is also an easy language and widely used. Simulation is performed on Xilinx ISE Design Suite and performance of the complete circuit is analyzed on X-power analyzer tool. After implementation, it is observed that the CU circuit using SSTL15 I/O Standard has consumed the least input power while on the contrary the circuit using SSTL2_II_DCI I/O Standard has utilized the highest power consumption.

Keywords—FPGA, CU, SSTL I/O Standard, VHDL, Xilinx- Suite, X-power Analyzer.

I.INTRODUCTION

Looking at the present context globally the need of the hour is to develop energy-efficient systems to protect our environment, tame climate change, and facilitate sustainable development which would be backboned on information and technology. The solutions developed in this regard are referred to as Green Communications [1-2] which is the part of our eco-technology. Eco technology in a broad sense can be defined as utilizing technology in order to benefit the environment, and hence in this technology advanced era, researchers aim to design and implement such tools which not only ensures a comfortable life to the humans but also is eco-friendly and helps our nature to maintain its integrity. Keeping in mind this requirement enormous researches have been made so far in queue and also many areongoingfor developing energy efficient devices which can be used for the betterment of the society. These efficient devices are characterized as technologically advanced and are capable to perform their specified task with the utilization of fewer resources. Since today’s world is left with the limited resources and rapidly growing population, meeting everyone’s requirements has become a great challenge for the researchers but this became possible with their hard work and unstoppablegrowing advancement in technology.Hence is this regard, researches now-a-

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days are solely power centred. Power is the lifeline of any power efficient circuit which needs to be optimized for supreme output. Large quantities of researches have been undertaken in seriesaiming to minimize the power consumption level of the circuit.Therefore to achieve the objective of Green Communication in this research work, FPGA implemented low power consuming CU circuit is introduced and to avoid power level mismatching, I/O standard is incorporated. The power consumption by the circuit is analysed on X-power analyser tool. A CU is an integral part of any computer's CPU which is responsible to administer its processor [3]. A CU is the heart of any computer without which a computer is meaningless. It governs the computer's logical unit, memory, input-output devices and makes them respond to any instruction. There are two methods to design a CU, they are Hardwired CU and Micro programmed CU. Hardwired CU is composed of combinational and sequential circuits on a single chip like logic gates, flip flops, registers, decoders and many more. Designing process requires a lot of planning, hard work and an error free infrastructure. If in case any modification or change is required in the circuit, the designer has to modify all the components as well, it can be a challenging and complicated task.On the other hand, a programming approach is used in the designing of micro programmed CU.In this type of design, a sequence of micro instructions generates the signals for controlling the execution of any instruction. In case any change or modification is needed, then it can be done by updating the micro programby the programmer.On the basis of these two prime differences between the designs of a CU during the manufacturing process, number of other differences can be stated in the form of Table 1. depicted below.

In this research work hard wired CU circuit is taken and its power consumption level is observed. By introducing an electronic microcontroller called FPGA changes in the power consumption level is observed. FPGA family is a big family consisting of large number of members like Virtex, Kintex, and Spartan etc. and further these members are sub divided depending on their internal circuitry. Since FPGA are known for their high cost, therefore researchers also tried to reduce the size of the FPGA chip so to make it cost effective.

Different technologies have been used so far for this purpose like nanometre scale, micrometre scale, picometre scale etc. In this research work for implementation of CU circuit, 40 nanometre Virtex- 6 FPGA is targeted. Besides for the purpose of optimizing the power of any circuit, selecting the correct I/O standard plays a significant role in the overall performance [4].These standards are programmable and broadly are used are used to communicate with other devices and simplifies any complex design. If they are used in the circuit, then the designer need not to worry about the variations in voltage level, power level etc. of the circuit, the existing circuit adapts itself as per the requirement of the circuit, making it risk free circuit.There are various types of I/O Standards which are being used for various purposes like SSTL, HSTL, and LVCMOS etc. Hence the I/O standard is used to match the impedance of I/O port of register and transmission line of register [5-6] such as in this research work for matching the input and output load power, Stub Series Terminated Logic (SSTL) I/O standard is used [7]. SSTL is an electrical interface generally used with Double Data Rate (DDR), Dynamic Random-Access Memory (DRAM) memory modules and Integrated Circuits (ICs). Several standards are there that define SSTL levels for ICs and or memory modules [8-9]. Fig.1shows different types of SSTL and SSTL Digitally Controlled Impedance (DCI) I/O Standard family for which the power consumption rate had been analysed. Likewise, other I/O standards also have a complete set of family members having specific properties.

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Fig.1.Types of SSTL I/O standard

Hence this paper presents the idea of implementing FPGA along with various I/O standards on a CU Circuit There is a lot of work has been done on FPGA with different energy efficient techniques for different digital circuits that minimize power consumption which ensures green communication, but no work has been done yet on control unit circuit. So in this work, the authors are designing an energy efficient CU circuit with the help of Virtex-6 FPGA using SSTL I/O standard. This work is a step towards contribution to green communication and power efficient devices.

II. Motivation and Contribution

Today’s technology is a digital technology with Computers as the heart of the infrastructure and CU is further the heart of any computer. Researches are ongoing in the direction of enhancing the performance of any system and therefore on the various micro circuits which plays a key role in any system. In case of Computer world, a CU circuit plays an important role, but there are very less work done in optimizing the performance of a CU circuit. This research work tried to focus solely in this direction and tried to enhance the overall performance of Computer Systems. Previous research works done in this area showed that power consumed by this small CU circuit is at critical level, which is noticeably responsible for the increased power consumption level by the whole system.

Optimizing the power level of a CU circuit will also optimize the overall performance of the complete system. This motivated us to work in this direction and therefore in this paper, we introduced CU circuit composed of FPGA along with I/O Standard to develop a power efficient system. After a careful analysis, it has been investigated that the power consumption level by the CU circuit is reduced to a noticeable value. The proposed method used various members of SSTL I/O standards and observed the changes in the final result. Hence this work contributes in developing an energy efficient system using CU circuit and hence worked in the direction of improving the CU circuit performance.

III.RELATED WORK

With the advent of the ever-advancing technologies especially in the field of information and technology, the modern era, is seeing a desperate urge of coherent electronic devices. They are expected to be capable of performing all the tasks assigned to them but at the same time be able to regulate the consumption of energy employed for processing the tasks. Hence with regard to this, numerous researches have been conducted making it prominent and active research area.

In connection to this background we observed that in paper [13], authors have designed power efficient Universal Asynchronous Receiver- Transmitter(UART) circuit on software tool XILINX Integrated Synthesis Environment (ISE) and analyzed its performance on various members of FPGA family like Spartan 6 (45nm) FPGA, (ambient temperature of 25.0degree C), Spartan 3 (90nm) FPGA, (ambient temperature of 25.0degree C) and Virtex 4 (65nm) FPGA, (ambient temperature of 50.0degree C).The default airflow for Spartan-6 and Spartan-3 is 0 while Virtex-4 has default

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airflow of 250 Linear Feet per Minute (LFM). Hence this paper came with the outcome that Spartan-6 requires least power to operate among all the three FPGA.

In paper [14], authors proposed that power consumption is directly proportional to number of elements used in realization of Hardware Description Language(HDL) code on FPGA. Hence reducing the number of components resulted into the reduced power.

They have designed 4-bit unsigned Up Counter on XILINX ISE 14.2 and implemented on Virtex -6 FPGA. They have used two codes in order to check the reduced power required. By changing mapping style, they calculated 6% power reduction and also reduced the number of Look-Up Table (LUT) and D flip-flop which further leads to area efficient design.

In paper [15] and [16] authors analyzed different I/O standards of High-Speed Transceiver Logic (HSTL) in order to find the most energy-efficient I/O standard from the I/O power perspective. The selection of the I/O standard plays an important role in energy-efficient design.

Similarly, in paper [17] authors have designed an energy efficient Watermark Generator (WMG) and hence extended the life of the battery. WMG is a device embedded into the camera. Low Voltage Transistor-Transistor Logic(LVTTL) I/O standard is used to optimize the power and it is implemented on Kintex-7 FPGA. Various operating frequency and current values had been used to analyze the performance of the circuit.

Also, in paper [18], authors have designed an Address Register sensitive towards rise in voltage and analyzed its performance on XILINX ISE 14.1, its result is checked on Virtex6 and Spartan 6 of FPGA family, lowering the voltage results in lowering down the power consumption. Out of the two circuits Spartan 6 consumed the least voltage.

In paper [19], authors analyzed that power changes with frequency hence it is directly proportional to frequency. On increasing frequency, power consumption level increases irrespective of the I/O standard. They checked the performance of Arithmetic-Logic Unit (ALU) using various I/O Standard, like Low Voltage Complementary Metal Oxide Semi-Conductor(LVCMOS) 12, LVCMOS15, LVCMOS25, and HSTL. They found that HSTL and LVCMOS 12 are the most power efficient I/O Standard. They used Spartan 3 and Virtex6 of FPGA family and concluded that Virtex 6 FPGA with LVCMOS 12 I/O Standard is the most efficient circuit for designing power efficient ALU circuit.

Similarly, in paper [20] authors designed a power efficient UART on XILINX ISE and tested its performance on Virtex-4,90 nm FPGA Virtex-5, 65nm FPGA andVirtex- 6, 40 nm of FPGA family using nanometer technology. They have also considered the ambient temperature and airflow which is 50 deg. C and 250 LFM respectively.

Post this it is concluded that not only FPGA kit but also the thermal properties played a vital role in reducing the energy consumption. Furthermore, the comparative analysis also shows that among the three members of FPGA family, Virtex-6, 90 nm technology has contributed the least power consumption by the UART and hence the most efficient technology. All these researches have been performed on various members of FPGA family using different technologies, similarly for I/O standards as well multiple researches have been performed.

Like in paper[21], authors have designed an energy efficient portable ALU using LVCMOS family I/O standard and analyzed the results. Further they made it portable by replacing the LVCMOS I/O standard with MOBILE Double Data Rate(DDR) I/O standard.

In paper [22], authors analyzed the power consumption by the I/O Standard for mobile applications by using a hardware solution which is capable enough to measure the power consumption at each transition level in the form of a signal without disturbing the integrity of the system.

In paper [23] another category of I/O standard had taken by the authors that is, LVCMOS and reduction in dynamic power and dynamic current of ALU has analyzed

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on applying low input specifications. For this purpose, Virtex-6 FPGA had targeted and coding is performed by using Verilog HDL, the experiment showed that LVCMOS can be one of the most efficient I/O standards while designing any VLSI circuit.

In paper [24], Low voltage digitally controlled impedance I/O standard is targeted and power utilization level is observed, by using Virtex-6 and for generation of waveform ISE Simulator(ISIM) is used. Out of the two LVDCI_25 and LVDCI_12, former I/O Standard proved to be highest power consumer while the later utilized the lowest power.

It is observed that all the specifications remain the same except the leakage power specification that came with the minor changes.

In paper [25],an apparatus and a method is introduced for controlling the power utilization by monitor of the PC by automatic switching between ON and OFF state corresponding to the state of power of PC.

In [26] research paper, Pentium processor is implemented named as processor 90/100 which showed the increased performance over the previous processor and also consumed low power and lesser area as compared to the later. Hence proved to be more efficient and technologically advanced.

This research work [27] showed that power optimization is of utmost importance for FPGA using nanometer technologies and hence designed FPGA circuits using configurable dual Vdd and correspondingly Computer Aided Design(CAD) is developed.

In paper [28] two steps that is simulation and measurement had been taken care of while determining the power utilization during the fabrication of FPGA. Recent member of FPGA Virtex™-II family is targeted.

In paper [29], comparative analysis had been made for FPGA, Graphics Processing Unit(GPU) and Multicores for designing sliding window applications. Out of the three circuits, FPGA proved to be the most efficient andenhanced the performance of the device.

Likewise, in paper [30], authors experimented floating point multiplier and adder/subtractor units on FPGA and analyzed its performance.

Paper [31], shows that SSTL I/O standard along with the combination of Virtex-6 of FPGA family develops a complete energy efficient ROM. Comparison had been made among the SSTL family I/O Standard so to get the most energy efficient I/O standard.

In research work [32], an energy efficient 32-bit ALU is designed by using various LVCMOS I/O standard and the research isperformed on XILINX-ISE. For coding purpose Verilog HDL is used and the power analyzer tool is X-power analyzer. They also came with the outcome that this design is completely compatible with the 4^th generation i7 microprocessor.

Similarly, in research work [33-34], as a contribution to green communication researchers designed energy efficient register design on ultra-scale FPGA and also targeted Fibonacci Generator along with LVCMOS I/O standard, operated this circuit at variouslocations, at different temperatures and observed variations in its performance.

Also in paper [35], authors analyzed FPGA and Application Specific Integrated Circuit(ASIC) technologies implemented circuits so to observe the power consumption ratio and observed that FPGA devices are rarely used where low power is an issue as compare to ASIC devices.

Lastly in paper [36], authors analyzed the power consumption of ALU circuit on FPGA.

Thus, from all these research work, it can be stated that FPGA is proved to be one of the efficient microcontroller which have brought a renaissance in today’s digital world.

Some related work can be expressed in tabular form shown in Table 2. Below Sr No. Related

Work

Technology Used Circuit Designed

1. 13 Spartan-6,Spartan- UART Circuit

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3,Virtex-4 FPGA

2. 14 Virtex-6 Four-bit Unsigned Up-

Counter

3. 17 Kintex-7 and LVTTL I/O

standard

WMG

4. 18 Virtex-6, Spartan-6 Address Register

5. 19 Spartan-3, Virtex-6 and

LVCMOS

ALU Circuit

6. 20 Virtex-4, Virtex-5, Virtex-

6

UART Circuit

7. 23 Virtex-6 and LVCMOS ALU Circuit

8. 31 Virtex-6 and SSTL ROM Circuit

9. 33-34 FPGA and LVCMOS Register Circuit

Table 2. Related work analysis IV.EXPERIMENTAL SETUP

A CU receives the input information and then converts it into control signals, and finally forwards it to the central processor. The computer’s processor then notifies the integrated hardware what operations to perform. The functions of a CU are CPU dependent i.e. it depends on the type of CPU.

The CU circuit with 40nm Virtex-6 FPGA is implemented on Xilinx ISE Design Suite.

Coding is performed by using the Very High-Speed Integrated Circuit Hardware Description Language (VHDL) language on the CU circuit. The power associated with different I/O standard is calculated on the X-Power Analyzer tool.

X power analyzer tool is an interactive graphical tool and is capable to perform following tasks with 100% accuracy,

 Power consumption for Xilinx® FPGA and CPLD devices.

 Can analyze thermal performance.

 Also analyzes static and dynamic power for different voltage levels.

 Also provides the complete data set for optimizing power level area wise.

The schematic representation of the CU Circuit is depicted in Fig.2.

[ Fig.2.Schematic representation of CU.

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V. I/O STANDARD POWER DISSIPATION ANALYSIS

Power dissipation in CPU is the epicenter of the total power requirement of a computer which needs to be managed in order to develop a power efficient circuit. Therefore, there is a requirement to minimize the power consumption of each device integrated on the board [10].

Power calculations of any device include the required power-supply, current requirements, cooling/heat-sink requirements, and device selection criteria. There are basically two components namely Static and Dynamic power which are associated with the total power consumption level in any VLSI design and hence in a CU Circuit [11-12].

Product of leakage current and the supply voltage is termed as the Static Power. Static power is considered to be the power when the circuit is OFF or when the circuit is nonfunctional. Furthermore, static power is associated with Direct Current (DC) current.

Also, the static power of FPGA circuit is proportional to the static current, which is the current that is independent of the gate switching. Therefore, total static power consumption can be stated as shown in the equation.

PS = α*β

Where PS=Static Power α = Supply Voltage β = Leakage Current

The dynamic power is the power related to change. The power dissipation occurs when the circuit is ON, is usually considered as the dynamic power. It is associated with the alternating current (AC) current. Therefore, the dynamic power of FPGA circuit is proportional to the active current, that is, the current that flows when the transition or switching occurs. Hence, it can be observed that the total dynamic power consumption for any FPGA circuit is the sum of the power utilized by the internal circuitry and the power consumed by the input and output ports of the device. Therefore, for calculating the total power dissipation, following equation can be used,

µ= PS + DP Where

µ= Total Power Dissipation PS= Static Power

DP=Dynamic Power

Therefore, considering the static power dissipation (leakage power) and the dynamic power dissipation (IOs, logic, clock and signal power) total power can be calculated which is further analyzed on X- power analyzer tool.

After experimental analysis, it is observed that dissipated power for some parameters of the circuit remains unchanged, they are clocks, logic, and signals for all the SSTL I/O Standard, while change in power dissipation occur in IOs, leakage and therefore the total power(W) of the device.

Based on this observation, it can be concluded that the SSTL I/O standard that consumes the least power can be implemented in future technology and hence supports Green Communication. These I/O standard members along with the Virtex-6 FPGA enable to get the efficient circuit.

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A. Power Dissipation Analysis for SSTL18_I_DCI I/O Standard

This research work observed the performance of power consumed by the CU circuit when incorporated with microcontroller FPGA (Virtex-6) along with I/O standard. . The CU circuit with 40nm Virtex-6 FPGA is implemented on Xilinx ISE Design Suite.

Programming required is done by using the Very High-Speed Integrated Circuit Hardware Description Language (VHDL) language on the CU circuit. For input-output power matching, SSTL is used. The power associated with different I/O standard is calculated on the X-Power Analyzer toolWhen SSTL18_I_DCI I/O Standard is used it is found that IOs is consuming 0.295W of the total power and leakage power of the device is 1.299W. The total power consumed by the CU circuit with SSTL18_I, I/O Standard is 1.628, shown in Fig.3. Values of the various parameters are shown in Table 3.

Parameter Clocks Logic Signals IOs Leakage Total Power

(W)

0.032 0 0.002 0.295 1.299 1.628

Table 3. Power Dissipation Analysis for SSTL18_I_DCI I/O Standard

Fig.3. Power Analysis for SSTL18_1_DCI I/O Standard B. Power Dissipation Analysis for SSTL2_II I/O Standard

In case of CU circuit comprised of FPGA (Virtex-6)and SSTL2_II I/O Standard,we observed that total power consumed by various parameters of the circuit are IOs, Leakage, and Total power are 0.290W, 1.300W and 1.624W respectively which are shown below.

Table 4. shows the values.

(W)

0.032 0 0.002 0.290 1.300 1.624

Table 4. Power Dissipation Analysis for SSTL2_II I/O Standard

0.032 0 0.002

0.295

1.299

1.628

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Power(W)

On Chip

Clocks Logic Signals IOs Leakage Total

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Fig.4. Power Analysis for SSTL2_II I/O Standard C. Power Dissipation Analysis for SSTL18_II I/O Standard

Similarly when SSTL18_II I/O Standard in the CU circuit was employed along with the Virtex-6, we observed the power consumption by the CU circuit in terms of some parametersand therefore IOs power obtained is 0.219W, Leakage power is 1.298W and Total power is 1.550W, and it’s shown in Fig.5. Table 5. Depicts the observed values.

(W)

0.032 0 0.002 0.219 1.298 1.550

Fig.5. Power AnalysisSSTL18_II I/O Standard D. Power Dissipation Analysis for SSTL15 I/O Standard

On experimenting the CU circuit using SSTL15 I/O Standard, changes have observed in IOs power, Leakage power and Total power which are 0.170W, 1.296W, and 1.500W respectively. Table 6. Shows the output values.

(W)

0.032 0 0.002 0.17 1.296 1.500

Table 6. Power Dissipation Analysis for SSTL15 I/O Standard

0.032 0 0.002

0.29

1.3

1.624

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Power (W)

On Chip

Clocks Logic Signals IO s Leakage Total

0.032 0 0.002

0.219

1.298

1.55

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Power (W)

On Chip

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Fig.6. Power Analysis for SSTL15 I/O Standard E. Power Dissipation Analysis for SSTL2_II_DCII/O Standard

Similarly, changes are noticeable in the CU circuit’s power consumption level when SSTL2_II_DCI I/O Standard is used along with the FPGAwhich is shown below in Fig.

7. Table 7. Is given below

(W)

0.032 0 0.002 0.28 1.323 2.636

Fig.7. Power Analysis forSSTL2_II_DCI I/O Standard F.Power Dissipation Analysis for SSTL18_II_DCI I/O Standard

In case of SSTL18_II_DCI I/O Standard, IOs power was 0.659W, Leakage power was 1.308W and Total power was 2.000W, which is represented in Fig.8. Table shown below states the observed values.

(W)

0.032 0 0.002 0.659 1.308 2.000

Table 8. Power Dissipation Analysis for SSTL18_II_DCII/O Standard

0.032 0 0.002

0.17

1.296

1.5

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Power (W)

On Chip

0.032 0 0.002

0.28

1.323

2.636

0 0.5 1 1.5 2 2.5 3

Power (W)

On Chip

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Fig.8. Power Analysis for SSTL18_II_DCI I/O Standard G.Power Dissipation Analysis for SSTL15_DCI I/O Standard

Results fromSSTL15_DCI I/O Standard, are depicted clearly in Fig.9 which shows the variation in power consumption level of IO power, leakage power and total power. Table shown here provides the observed values.

(W)

0.032 0 0.002 0.248 1.298 1.580

Table 9. Power Dissipation Analysis for SSTL15_DCI I/O Standard

Fig.9. Power Analysis forSSTL15_DCI I/O Standard H. Power Dissipation Analysis for SSTL2_I_DCI I/O Standard

Power analysis table of SSTL2_I_DCI I/O Standard shows that IOs power is 0.444W, Leakage power is 1.303W, and Total power is 1.781W. Table 10. Shown below clearly shows the value.

(W)

0.032 0 0.002 0.444 1.303 1.781

Table 10. Power Dissipation Analysis for SSTL2_I_DCI I/O Standard

0.032 0 0.002

0.659

1.308

2

0 0.5 1 1.5 2 2.5

Power (W)

On Chip

Clock Logic Signals IO s Leakage Total

0.032 0 0.002

0.248

1.298

1.58

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Power (W)

On Chip

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Fig10. Power Analysis for SSTL2_I_DCI I/O Standard I. Power Dissipation Analysis for SSTL18_I I/O Standard

Figure and table shown below shows the changing parameters of CU circuit which are leakage, IOs and Total power when their power consumption performance is observed on power analyzer tool.

(W)

0.032 0 0.002 0.186 1.297 1.517

Table 11. Power Dissipation Analysis for SSTL18_II/O Standard

Fig11. Power Analysis for SSTL18_I I/O Standard

VI.RESULTS

We can analyze the performance of all the SSTL I/O Standard from Fig. 12 by taking SSTL15 I/O Standard which is the least power consuming SSTL as the Reference Model.

0.032 0 0.002

0.444

1.303

1.781

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Power (W)

On Chip

0.032 0 0.002

0.186

1.297

1.517

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Power (W)

On Chip

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Fig12. Power Comparison chart of SSTL I/O Standard

From Fig. 12 clearly depicts that SSTL2_II_DCI I/O Standard when used along with the Virtex-6 FPGA consumes the maximum power and SSTL18_II_DCI I/O Standard attains the second position, and their values are 2.6W and 2W respectively. On the other hand, the other family members consume the power ranging from 1.5W to 1.7W. Therefore, it can be stated that in future technologies, CU Circuit can be designed by taking any of these SSTL I/O standard for efficient functioning. Using this type of circuit can be utilized for the betterment of eco-technology and therefore for the society.

VII.CONCLUSION

Through this paper it’s attempted to highlight the objective of Green Communications and to explore innovative ways of minimizing the total power required to operate the future mobile communications systems. Green communication assures that emerging wireless/wired network systems will deliver services at the minimum energy cost aiding in the global effort to curb climate change. Many researchers are tirelessly contributing a lot in this field in order to enhance the performance of any system.

Here this research work tried to gain the attention of the reader on designing a CU circuit that is power-efficient and has a significant contribution in reducing the power consumption level of the whole computer system.

This research focused on utilizing any device which is proved to be one of the most efficient microcontroller of today’s generation which is Virtex-6 of FPGA family and also for power level matching SSTL I/O Standard is considered. Hence a CU circuit is developed which is composed of Virtex-6 FPGA and SSTL I/O standard and analyzed on power analyzer tool. Final analysis states that power consumption level for various parameters of the circuit is the least in case of Virtex-6 FPGA used alongwith SSTL15 I/O Standard while it is highest in case of Virtex-6 SSTL2_II_DCI I/O Standard.

So, the future technologies can work on implementing a circuit composed of FPGA Virtex-6 with SSTL15 I/O Standard in order to develop an energy efficient circuits as their contribution to Green Communication and hence to eco-technology.

VIII. FUTURE SCOPE

This research work observed the performance of CU circuit on Virtex-6 from FPGA family, researchers can analyze the circuits on other family members of FPGA family like Spartan, Kintex etc. This research used 40nm technology, nowadays 28nm, 14nm technologies are also in vogue, which can be further used for research purposes. In this paper, analysis is performed on SSTL I/O Standards for input and output power matching, researchers can analyze the same parameters using various other I/O standards like LVTL, HSTL, and LVCMOSetc. Experiments shows variation in the power consumption level of

0 0.5 1 1.5 2 2.5 3

TOTAL POWER(W)

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the circuit, other parameters like noise,energy etc. can also be analyzed and thus can contribute to eco-technology.

REFERENCES

1. W.Vereecken, W.V. Heddeghem, D.Colle, M. Pickavet, and P. Demeester.

"Overall ICT footprint and green communication technologies." In 2010 4th International Symposium on Communications, Control and Signal Processing (ISCCSP), pp. 1-6. IEEE, 2010.

2. S. M T. Siddiquee, K. Kumar, B. Pandey, A. Kumar,” Energy Efficient Instruction Register for Green Communication”, International Journal of Engineering and Advanced Technology (IJEAT), Volume-8, Issue-2S2, January 2019.

3. K. Kumar, S. Ahmad, B. Pandey, A. K Pandit, D. Singh, D.M A.Hussain "Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8, Issue-9S2, July 2019.

4. P. R. Singh, B. Pandey, T. Kumar, and T. Das. "I/O standard- based-power optimized processor register design on ultra-scale FPGA." In 2014 International Conference on Computing for Sustainable Global Development (INDIACom), pp. 172-177. IEEE, 2014.

5. K. Goswami, B. Pandey, T. Kumar, and D.M AHussain. "Different I/O Standard and Technology-Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green WirelessCommunication on FPGA." Wireless Personal Communications 96, no. 2 (2017): 3139-3158.

6. S.Madhok, A. Kaur, and B.Pandey. "Different IO standard-based energy-efficient decoder design for 64-bit processor architecture." In 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 1813-1817. IEEE, 2015.

7. T. Das, B. Pandey, M. A. Rahman, and T. Kumar. "SSTL based green image ALU design on different FPGA." In 2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE), pp. 146-150.

IEEE, 2013

8. M.Bansal, N. Bansal, R.Saini, B. Pandey, L. Kalra, and D. M.A.Hussain. "SSTL I/O Standard-based environment-friendly energy-efficient ROM design on FPGA." In 3rd International Symposium on Environmental Friendly Energies and Applications (EFEA), pp. 1-6. IEEE, 2014

9. K.Kalia, K. Nanda, S. Malhotra, and B. Pandey. "HSTL based low power thermal aware adder design on 65nm FPGA." In 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 1490-1495.

IEEE, 2015.

10. E.Fetzer, R.J. Reidlinger, D.Soltis, W.J. Bowhill, S. Shrimali, K.Sistla, E.Rotem et al. "Managing power consumption in a multi-core processor." U.S. Patent 9,069,555, issued June 30, 2015.

11. B.Goel and S.A. McKee. "A methodology for modeling dynamic and static power consumption for multicore processors." In 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pp. 273-282. IEEE, 2016.

12. H. Yoon, M.McLaren, D.S. Milojicic, R.Schreiber, and N.P.Jouppi. "Computer power management." U.S. Patent 9,575,542, issued February 21, 2017.

13. K.Kumar, A.Kaur, B.Pandey, and S. N. Panda. "Low Power UART Design Using Different Nanometer Technology-Based FPGA." In 2018 8th International Conference on Communication Systems and Network Technologies (CSNT), pp.

1-3. IEEE, 2018.

(15)

14. B.Pandey, and M. Pattanaik. "Low power VLSI circuit design with efficient HDL coding." In 2013 International Conference on Communication Systems and Network Technologies, pp. 698-700. IEEE, 2013.

15. K.Goswami, and B. Pandey. "Voltage scaling based low power high- performance Vedic multiplier design on FPGA." In 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 1529-1533. IEEE, 2015.

16. K.Goswami, and B.Pandey. "Reduction of I/O power using energy-efficient HSTL I/O standard in Vedic multiplier on FPGA." In 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 1514-1518. IEEE, 2015.

17. B.Pandey, A.Kaur, T.Kumar, T.Das, M.A.Rahman, and D.M.A.Hussain. "LVTTL based energy efficient watermark generator design and implementation on FPGA." In 2014 International Conference on Information and Communication Technology Convergence (ICTC), pp. 642-646. IEEE, 2014.

18. B. Pandey, K. Kumar, S. Ahmad, A. K Pandit, D. Singh, D.M A.Hussain"

Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA”, International Journal of Innovative Technology and Exploring Engineering (IJITEE) Volume-8 Issue- 9S2, July 2019

19. B.Pandey,J.Yadav,Y.K.Singh, R.Kumar, and S. Patel. "Energy efficient design and implementation of ALU on 40nm FPGA." In 2013 International Conference on Energy Efficient Technologies for Sustainability, pp. 45-50. IEEE, 2013.

20. K.Kumar, A. Kaur, S. N. Panda, and B. Pandey. "Effect of Different Nano Meter Technology-Based FPGA on Energy Efficient UART Design." In 2018 8th International Conference on Communication Systems and Network Technologies (CSNT), pp. 1-4. IEEE, 2018.

21. T. Kumar, B. Pandey, T. Das, and B. S. Chowdhury. "Mobile DDR IO standard based high performance energy efficient portable ALU design on FPGA." Wireless Personal Communications 76, no. 3 (2014): 569-578

22. L. Marraa, F. Iannuzzoa, M. D. Zenzob, V. Micalib, G. Valerib, D. Biancob, and G.

Busattoa. "Experimental analysis of energy consumption by MobileDDR memory for mobile applications." In 2008 IEEE International Symposium on Industrial Electronics, pp. 1686-1691.IEEE, 2008.

23. B. Pandey, and R. Kumar. "Low voltage DCI based low power VLSI circuit implementation on FPGA." In 2013 IEEE Conference on Information & Communication Technologies, pp. 128-131. IEEE, 2013.

24.

24. B. H. Oh, and H. C. Lee. "Apparatus and method for controlling power of monitor." U.S. Patent 7,664,975, issued February 16, 2010.

25. Debnath, K. Debnath, and R. Fernando. "The Pentium processor-90/100, microarchitecture and low power circuit design." In Proceedings of the 8th International Conference on VLSI Design, pp. 185-190. IEEE, 1995.

26. F. Li, Y. Lin, and L. He. "FPGA power reduction using configurable dual- Vdd." In Proceedings of the 41st annual design automation conference, pp.

735-740. ACM, 2004.

27. L. Shang, A. S. Kaviani, and K. Bathala. "Dynamic power consumption in Virtex™-II FPGA family." In Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, pp. 157-164.

ACM, 2002.

28. J. Fowers, G. Brown, P. Cooke, and G. Stitt. "A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications."

In Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, pp. 47-56. ACM, 2012.

(16)

29. Govindu, L. Zhuo, S. Choi, and V. Prasanna. "Analysis of high-performance floating-point arithmetic on FPGAs." In 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings, p. 149. IEEE, 2004.

30. M. Bansal, N. Bansal, R. Saini, B. Pandey, L. Kalra, and D. M. A. Hussain.

"SSTL I/O Standard based environment friendly energy efficient ROM design on FPGA." In 3rd International Symposium on Environmental Friendly Energies and Applications (EFEA), pp. 1-6. IEEE, 2014.

31. N. Bansal, M. Bansal, R. Saini, B. Pandey, L. Kalra, and D. M. A. Hussain.

"LVCMOS I/O Standard Based Environment Friendly Energy Efficient ALU Design on FPGA."

32. P. R. Singh, B. Pandey, T. Kumar, and T. Das. "I/O standard based power optimized processor register design on ultra-scale FPGA." In 2014 International Conference on Computing for Sustainable Global Development (INDIACom), pp. 172-177. IEEE, 2014.

33. T. Kumar, B. Pandey, T. Das, and D. M. A. Hussain. "I/O standard based thermal/energy efficient green communication for Wi-Fi protected access on FPGA." In 2014 6th International Congress on Ultra-Modern Telecommunications and Control Systems and Workshops (ICUMT), pp. 95- 98. IEEE, 2014.

34. Amara, F. Amiel, and T. Ea. "FPGA vs. ASIC for low power applications." Microelectronics journal 37, no. 8 (2006): 669-677.

35. Pandey and M. Pattanaik. "Clock gating aware low power ALU design and implementation on FPGA." International Journal of Future Computer and Communication 2, no. 5 (2013): 461.

36. V. Mohindru and Y. Singh. "Node authentication algorithm for securing static wireless sensor networks from node clone attack." International Journal of Information and Computer Security 10, no. 2-3 (2018): 129-148.

37. V. Mohindru, and Y. Singh. "Performance analysis of message authentication algorithms in wireless sensor networks." In 2017 4th International Conference on Signal Processing, Computing and Control (ISPCC), pp. 468-472. IEEE, 2017.

38. V. Mohindru, Y. Singh, and R. Bhatt. "A Review on Lightweight Node Authentication Algorithms in Wireless Sensor Networks." In 2018 Fifth International Conference on Parallel, Distributed and Grid Computing (PDGC), pp. 517-521. IEEE, 2018.

39. V. Mohindru, R. Bhatt, and Y. Sin8h. "Reauthentication scheme for mobile wireless sensor networks." Sustainable Computing: Informatics and Systems 23 (2019): 158-166.