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A Static Phase Offset Reduction Technique for Multiplying Delay Locked Loop

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Figure

Figure 1. (a) Edge combiner based MDLL; (b) Cyclic reference injection based MDLL.
Figure 4. Concept of block diagram of the proposed SPO reduction technique; (a) S-domain model of MDLL; (b) S-domain model of MDLL with SPO Δθ; (c) S-do- main model of MDLL with SPO Δθ; and a gain stage insertion; (d) Equivalent SPO becoming Δθ/G after a g
Figure 6. Simplified timing diagram of PD.
Figure 9. Spectral plots of VCDL output under different conditions (a) SPO = 0, G1 = 1; (b) SPO = 2e−12, G1 = 1; (c) SPO = 2e−12, G1 = 10; (d) SPO = 2e−12, G1 = 50

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