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TSMC 4 0 Design Flow Diagram

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(1)

TSMC Hierarchical

Design Flow

(2)

RC Correlation (StarRCXT->Apollo->FE)

flattened prototyping (FE)

IR drop analysis (MarsRail)

hierarchical prototyping (FE) Netlist, Timing Constraint, Size

top level trial route (APO) floorplanning (FE)

RC Correlation(FE->PC) block frame view and pdb

generation(APO)

block preCTS implementation (PC): placement, timing optimization block timing model generation top preCTS implementation (PC):

placement, timing optimization top/block implementation (APO):

CTS, track assign, SDF RC Correlation

(APO->PC) block/top post CTS implementation (PC) block/top detail route (APO):

double via, xtalk, antenna

fullchip STA (PT, StarRCXT, NDC)

characterizing timing-violated

blocks(PT) budgeting (PT)

full chip verification: IR analysis (Voltage Storm)

DRC LVS (Calibre)

Formal Verification (Formality, Verplex) xtalk (CeltIc)

APO: Apollo

FE: First Encounter

NDC: Nautilus DC

PC: Physical Compiler

(3)

RC Correlation (StarRCXT->Apollo->FE)

flattened prototyping

(FE)

floorplanning (FE)

hierarchical prototyping (FE) Netlist, Timing Constraint, Size

original netlist timing constraint (sdc) timing library(.lib) standard cell library(.cdump) technology file initial floorplan (I/O, critical macro

placement) Amoeba Place congestion OK? design import CTS trial route Extract RC Timing Analysis IPO Is Timing Met? no yes yes no ti ming r epa ir loop conges tio n r epa ir loop trial route save route save place saved initial placement saved initial routing create fences (shaping, resizing) specify partition macro placement refinement Amoeba place power planning trial route

feed-through buffer insertion, refine placement, trial route

save floorplan save placement save netlist

commit partition

top level route

Congestion OK? floorplan file(.fp)

placement file(.place) netlist(.v)

load placement, load routing

saved initial placement and routing co n g es ti on r ep ai r loop CTS trial route Extract RC Timing Analysis IPO Is Timing Met? yes no timing r ep a ir lo o p no yes Save Partition Partitioned netlist, constraint, floorplan original netlist timing constraint (sdc) timing library(.lib) standard cell library(.cdump) technology file design import

IR drop analysis

(MarsRail)

(4)

1. partitioned netlist 2. partitioned timing

constraint

3. standard cell library 4. macro library 5. timing library Design Import Load Floorplan AmoebaPlace Partitioned Floorplan (.fp) CTS TrialRoute congestion OK? Extract RC Timing Analysis IPO Is timing met?

modify top level floorplan Macro Placement PT:Budgeting RC Correlation Extract RC SPEF Setload Delay Calculation SDF Save netlist Save Placement Netlist PDEF no yes no yes

Create Stamp Model Model Definition Model Data

RC Correlation (StarRCXT->Apollo->FE)

flattened prototyping (FE)

floorplanning (FE)

hierarchical prototyping

(FE) (Block Level)

Netlist, Timing Constraint, Size

IR drop analysis (MarsRail)

top level trial route (APO)

(5)

Stamp Models of Each Partition

1.Macro Libraries of Each Partition (.cdump) 2.Top Level Netlist 3.Top Level Timing

Constraints 1. Standard Cell Library 2. Timing Library 3. Technology file Top Level Floorplan Design Import Load Floorplan AmoebaPlace CTS Trial Route congestion OK? Extract RC Timing Analysis IPO Is timing met? PT:Budgeting RC Correlation Extract RC SPEF Setload Delay Calculation SDF Save netlist

Save Partition Netlist no yes no yes Save IO File (pin locations) .tdf RC Correlation (StarRCXT->Apollo->FE)

flattened prototyping (FE)

floorplanning (FE)

hierarchical prototyping

(FE) (Top Level)

Netlist, Timing Constraint, Size

IR drop analysis (MarsRail)

top level trial route (APO)

(6)

RC Correlation(FE->PC) block frame view and

pdb generation(APO) block level preCTS implementation (PC): placement, timing optimization

block timing model extraction

top level preCTS

implementation (PC): placement, timing optimization

top/block level implementation (APO): CTS, track assign, SDF RC Correlation(APO->PC) block/top post CTS implementation (PC) block/top detail route (APO):

double via, xtalk, antenna fullchip STA characterizing timing-violated blocks (PT) budgeting (PT)

PC

• netlist

• timing constraint

design import

write boundary

parasitics

PC

.SPEF

remove SDF

on boundary

1.boundary net

transition time

2.boundary

capacitance

load boundary

parasitics

extract timing model

PC

.SDF

(7)

RC Correlation(FE->PC)

block frame view and

pdb generation(APO)

block level preCTS implementation (PC): placement, timing optimization

block timing model extraction

top level preCTS implementation (PC): placement, timing optimization

top/block level implementation (APO): CTS, track assign, SDF RC Correlation(APO->PC) block/top post CTS implementation (PC) block/top detail route (APO):

double via, xtalk, antenna fullchip STA

characterizing timing-violated blocks (PT)

budgeting (PT)

Create Lib (Ref = Std)

NetlistIn

load floorplan script

Make Macro

Create Timing Model

Load Timing

Constraint

Load Timing CLF

Dump LEF

(dumpLibLEF.scm)

.CLF

.CLF with clock

port capacitance,

clock port subtype,

port direction

lef2plib

.LEF

PLIB

Read PLIB

write PDB

PDB

FE

• netlist(simplified)

• floorplan script

• tdf files

• Timing constraints

(Clock information

only)

APO CTS

PC

metal_case.pl

(8)

RC Correlation(FE->PC)

block frame view and pdb generation(APO) block level preCTS implementation (PC): placement, timing optimization

block timing model extraction

top level preCTS implementation (PC): placement, timing optimization

top/block level

implementation (APO):

CTS, track assign, SDF

RC Correlation(APO->PC)

block/top post CTS

implementation (PC)

block/top detail route (APO): double via, xtalk, antenna

characterizing timing-violated blocks (PT) budgeting (PT) NetlistIn *_cts_fixed.pdef PC netlist .pdef

Load floorplan script

Load power plan script

Load timing constraints

Read PDEF (readPDEF3.scm)

Purge clock net/ default TranDelay

CTS

Report skew Dump PDEF (dumpPDEF3.scm)

Hierarchical Netlist Out

Write SDF/Setload

1.floorplan script 2.power plan script 3.tdf

FE

FE

timing constraint (clock information only)

*.hvout *_cts_fixed.sdf *_cts_fixed.dc Define Synchronous Pin pdef_pc2apo.pl pdef_apo2pc.pl sdf_apo2pc.pl Create Lib (RefLib = Std) Create Lib (RefLib = Std cell, generated pdb library) CTS related files metal_case.pl

PC

(9)

RC Correlation(FE->PC)

block frame view and pdb generation(APO) block level preCTS implementation (PC): placement, timing optimization

block timing model extraction

top level preCTS implementation (PC): placement, timing optimization

top/block level implementation (APO): CTS, track assign, SDF RC Correlation(APO->PC) block/top post CTS implementation (PC)

block/top detail route (APO):

double via, xtalk, antenna

fullchip STA characterizing timing-violated blocks (PT) budgeting (PT) Create Lib (RefLib = Std) Create Lib (RefLib = Std cell, generated pdb library) NetlistIn Read PDEF preRoute CTS APO CTS related files generated after CTS Route Xtalk reduction route Antenna-fixing route

PC

netlist .pdef

Block level

Top level

Define Synchronous Pin (Top level only)

*_cts_fixed.pdef Dump PDEF (dumpPDEF3.scm) Write SDF/Setload *_cts_fixed.sdf *_cts_fixed.dc pdef_apo2pc.pl sdf_apo2pc.pl dc_apo2pc.pl

Write SPEF *_route.SPEF

Load floorplan script

Load power plan script

1.floorplan script 2.power plan script 3.tdf

FE

metal_case.pl

PC

References

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