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SPADIC: CBM TRD Readout ASIC

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Schaltungstechnik Simulation und Schaltungstechnik Simulation und

SPADIC: CBM TRD Readout ASIC

Tim Armbruster

tim.armbruster@ziti.uni-heidelberg.de HIC for FAIR, Darmstadt

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Introduction to SPADIC

Abstract Data Flow Concept

Charge Pulse Amplification and Shaping →

Continuous Digitization →

Continuous Filtering →

Digital Hit Detection →

Package building

(pulse snap-shots plus meta-data) →

Fast serial output interface

Channel 1 Output logic Channel 2 ... ... Channel n Channel n-1 U n co rr el at ed c h ar g e p u ls es Output Packages

SPADIC

SPADIC applications

- TRD

- Maybe RICH

- MUCH ???

- ...

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Planned SPADIC Architecture and Building Blocks

• 32 channels ASIC in UMC 180 nm • Basic channel structure

– Input protection

– Preamplifier / Shaper (~ 90 ns shaping time, positive pulses)

– ADC (~ 8 Bit)

– IIR Filter (ion-tail cancellation, baseline correction, ...)

– Digital trigger logic (self-triggered scheme)

– Package builder (payload, time-stamp, channel #, …)

• Global parts after the channels – Inter-channel network (token

ring)

– DAQ compatible protocol

encoder (computer architecture group, HD)

– Serializer, driver (two 500 Mbit/s links per chip)

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More Features ...

(Possible) Additional Features

• Preamplifier/Shaper

– Switchable tradeoff between preamplifier noise and power consumption – Input mode for large negative input pulses (up to 10^6 electrons, RICH) – Switchable gain (2-4 steps)

– Switchable shaping time (2-4 steps) • Digital

– Different hit detection modes (e.g. single-/dual-threshold)

Neighbor readout (channels will be able to trigger the readout of

neigbor channels)

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Planned SPADIC 1.0 Floorplan

● 3 x 4(?) mm² estimated die size ● 32 channels, 80µm pitch

● Digital parts will probably dominate

Bias Slow Control Post-Processing / Triggering / Package Building < 5 mm 3 m m

Detector Pads Bias + Power Pads Digital I/O

Preamp/Shaper FIR Inj. ADC

Serial I/O

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Block Diagram of Latest SPADIC v0.3

preamp 25 shaper 25 SR 0 preamp 0 shaper 0 ADC 0 Analog Bias

12 x 7 Bit current DAC

Shift Register Control 8 8 8 8 8 8 8 8 Output MUX and Decoder 16 9 Test and Calibration Circuits ADC 7 SR 7 ESD Pad ESD Pad ESD Pad ESD Pad ESD Pad ESD Pad ESD Pad ESD Pad

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Front-End Amplifier: Preamplifier/Shaper Circuit

H s ≈ ADC 1s RSCS2

R

S

R

S

C

S

C

S

11x

1x

(also channels with less instances for test purpose on chip) • O'Connor FB • 2nd order shaper • Shaping time: 82 ns • Unified amplifier cell • N-MOS input

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Algorithmic ADC Design

U to I compa-rator current in/out write write & read Vref digital out current mode voltage node digital domain storage node

8 (scaled) pipeline stages, therefore 9 Bit design, 7.5 Bits effective so far • Algorithmic working principle (“1.5 redundant Bits” / conversion step)

25 MSamples/s, layout only 130x120 µm², power consumption 4.5 mW

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Latest SPADIC: Layout

Bias circuitry (12 current DACs)

26 preamp/shaper channels

Detector capacitors (5pF per block)

8 pipelined ADCs

ADC control + bias

5.2 kBit shift register matrix

Control + readout/decoder logic blocks

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Test-Setup: SPADIC plugged on Susibo

SPADIC To TRD

Power

Power daisy-chain Ext trigger input (sync-t)

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Setup in Lab

2 Hitclients with live-data

2 SPADIC Setups

Test pulses injected trough test pulse generator on PCB

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Hitclient Screenshot

Software package available: Configuration Tool

+ Online Monitoring + DABC Plug-in

Screenshot of latest version (12/2010)

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CERN Testbeam 2010: Münster's TRD-SPADIC Setup

2 Münster's ALICE-Style chambers with drift

4 SPADIC Setups

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CERN Testbeam 2010

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CERN Testbeam 2010: Go4 Spadic online event

CERN Testbeam Nov. 2010 Go4 TRD (Münster) online event (screenshot) 2 TRD chambers, each with 2 Spadic setups (2 x 8 channels) Data is being Analyzed

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New Setup: Improved PCB Layout, under construction

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Summary

Status of Latest Prototype (SPADIC v0.3)

● 8 complete channels (plus 18 test channels)

● Positive input charges, about 0..40fC input range ● 2nd order shaping, 90 ns shaping time

● Noise: 800e @ 30 pF capacitive input load

● ADC with 7.5 Bit effective (INL) @ 25 Msamples/s ● Power per Channel/ADC: 3.8/4.5 mW

● Size: 1.5 x 3.2 mm²

Status of Latest Setup

● 8 complete setups have been available @ CERN Testbeam

Nov. 2010

● New PCB with low noise layout and reduced ground loops has

just been designed and is now being fabricated

● Ongoing software development (config. + monitoring tools)

First full-blown SPADIC (v1.0)

● Design phase has just been started

● Planned Submission: summer/fall 2011

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References

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