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Ultra low inductance design for a GaN HEMT based 3L ANPC inverter

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Figure

Fig. 2. Switching sequences for leg-A of the 3L-ANPC inverter [18].
Fig. 4. PCB design for GaN HEMT gate driver.
Fig. 6. Power cell design in a 4-layer PCB.
Fig. 8. Common-mode currents through parasitic capacitances with respectto output voltage rise.
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