I. Course Information
Electronic Devices and Circuits ENGE 311
Fall Semester 2013 September 2nd through December 13th
Lecture: Edwards-Holman 325 (MoWeFr: 11:40 AM – 12:30 PM)
Lab: Wood-Mar 106 (TH: 2:40 PM – 5:30 PM)
II. Professor Information
Dr. Robert Melendy Assistant Professor
Office Location: Wood-Mar Hall 217
Office Phone: (503) 554-2730
E-mail: [email protected]
III. Course Description
This course is an introduction to the terminal characteristics of the fundamental semiconductor devices. The operation and small-signal models of the following devices will be examined: Operational amplifiers, diodes, the field-effect transistor (FET), and the bipolar-junction transistor (BJT). Basic single-stage amplifiers containing these devices will be examined, including gain, biasing, and frequency response. Switching characteristics of transistors in saturation and cutoff will also be investigated. There are three lectures and one laboratory each week.
IV. Course Web Page
https://sites.google.com/a/georgefox.edu/prof-melendy-s-engineering-student-s-link/
V. Course Objectives
Upon completion of this course you will be expected to know how to:
1. Analyze various configurations of Operational Amplifier circuits.
2. Evaluate the effectiveness of Operational Amplifier models.
3. Design and test practical circuits that utilize Operational Amplifiers.
4. Analyze the terminal characteristics of various Diode circuit configurations.
5. Design and test practical circuits that utilize using Diodes.
AND
C
IRCUITS
ENGE 311
Course Syllabus
6. Analyze circuits involving MOSFET and BJT transistors.
7. Explain when to use large-signal and small-signal models of MOSFET and BJT transistors.
8. Design biasing networks for effective use of MOSFET and BJT amplifiers.
9. Design various configurations of MOSFET transistors including source, common-gate, and common-drain configurations.
10. Design various configurations of BJT transistors including common-emitter, common-base, and common-collector configurations.
11. Evaluate appropriate amplifier configuration models for differing requirements.
12. Describe the semiconductor device physics for Diodes, MOSFET, and BJT transistors.
13. Use a standard PSPICE modeling program for the analysis of microelectronic circuits.
VI. Course Prerequisite
ENGE 220 (Digital Logic Design) and ENGE 250 (Electric Circuit Analysis).
VII. Required Textbooks
Microelectronic Circuits (6th edition), Sedra and Smith (2009) – Oxford University Press.
VIII. Grade Breakdown
Labs (450 pts.)
Exams (four at 100 pts. each) (400 pts.)
Final Examination (150 pts.)
Total = 1,000 pts.
IX. Grade Distribution
Grade Percentage Points Grade Percentage Points
A 92-100% 920-1,000 C 72-77% 720-779
A- 90-91% 900-919 C- 70-71% 700-719
B+ 88-89% 880-899 D+ 68-69% 680-699
B 82-87% 820-879 D 60-67% 600-679
B- 80-81% 800-819 F 0-59% 0-599
X. Course Policies A. Assignments
Labs: The labs will consist of approximately 11 microelectronic experiments. Most lab experiments will require a pre-lab to be completed before you come to lab. Failure to complete the pre-lab before the designated lab experiment time will result in a 25% grade penalty for that lab. All labs will be due at the beginning of the following lab period. Failure to complete even a single lab experiment and/or a lab report will result in a full letter-grade reduction in your overall course letter-grade.
Exams: Exams will be given during regularly scheduled lecture times (SEE XIV – SCHEDULE OF TOPICS). Exams will be closed book and closed note. You will be provided with an equation/formula sheet for each exam so that you don’t have to memorize lengthy and complicated equations.
Exam Policy
I have a firm policy in place for missed exams. There are six “typical” conditions under
which I will accept a missed exam:
(i) A medical-related issue – requires documentation from a clinic or a medical provider; (ii) a funeral service which you attend; (iii) jury duty (requires a letter from the court in which you serve as a juror); (iv) military duty (requires a letter from a commanding officer); (v) a Bruin
sports event in which you are the athletic participant (requires a release from you coach or
athletic coordinator); or (vi) a community service event that you are scheduled to participate in.
Whenever possible, please clear events in advance with me.
B. Personal Communication Devices Policy
The use of cell phones and/or any other such devices that are used to send or receive personal messages is prohibited. Be sure that your cell phone ring tone is completely shut off
before you enter the classroom. It is a simple rule associated with professionalism and respect for others.
C. Attendance Policy and Punctuality
I expect you to attend each weekly set of classes and to actively participate. Tardiness is frowned upon, especially when it is habitual. Diligence with these expectations will greatly increase the value, understanding and enjoyment from the course for everyone involved.
XI. Class File
You are REQUIRED to maintain a file of all your labs and exams. You may be asked to submit your engineering class files at the end of each semester. These files are used by the engineering program during the ABET accreditation process. Student confidentiality and privacy will be maintained during this process. You may always collect your class file from your professor after the accreditation process is complete.
The third mission objective of the George Fox University Engineering Program states:
“GFU Engineers will understand responsible service from a Christian worldview that emphasizes integrity in every aspect of this service, motivates individuals to a life of
responsible service to humankind, and recognizes the need for a life of continued learning.”
Each semester, we will collectively identify an influential Christian writing to be read and reflected upon by the engineering faculty and students throughout the semester. Readings may be integrated and assessed at the discretion of each engineering course instructor.
XIII. Americans with Disabilities Act
If you have specific physical, psychiatric, or learning disabilities and require accommodations, please contact the Disability Services Office as early as possible so that your learning needs may be appropriately met. You will need to provide current documentation of your disability to the Disability Services Office. For more information, go to ds.georgefox.edu or contact Rick Muthiah, Dean of the Center for Teaching and Learning (503-554-2314 or [email protected]).
XIV. Schedule of Topics
This schedule of topics, dates and order of presentation has been very carefully planned. However, your professor reserves the right to make adjustments as may be deemed necessary.
Week Date Scheduled Topic Read BEFORE Class
1
M Sept. 2 Introduction to Course Objectives and Syllabus
W 4 Decibels and Amplifier Models 1.1 – 1.4
F 6 Amplifiers 1.4 – 1.6
2 WM 119 Operational Amplifiers (Inverting)Serve Day – NO CLASSES 2.1 – 2.2
F 13 Operational Amplifiers (Non-Inverting), Summers 2.3
3
M 16 Difference Amplifiers 2.4
W 18 Integrators, Differentiators, DC Imperfections 2.5 – 2.6 F 20 Finite Open-Loop Gain, Large Signal Operation 2.7 – 2.8
4
M 23 Ideal Diodes 4.1
W 25 Terminal Characteristics 4.2
F 27 Diode Models 4.3
5
M 30 **EXAM I**
W Oct. 2 Zener Diodes, Rectifiers 4.4 – 4.5
F 4 Rectifiers
6
M 7 Physical Operation of the pn-Junction 3.1 – 3.3 W 9 Physical Operation (Cont’d)
F 11 Mid-Semester Holiday – NO CLASSES
7
M 14 Physical Operation of MOSFETS 5.1
W 16 MOSFET I/V Characteristics 5.2
F 18 **EXAM II**
8
M 21 MOSFET’s at DC 5.3
W 23 MOSFET’s as an Amplifier 5.4
F 25 MOSFET Small Signal Operation 5.5
9 M 28 MOSFET Amplifier Configurations 5.6
F Nov. 1 Biasing 5.7
10
M 4 Discrete-Circuit MOSFET Amps, Body Effects 5.9
W 6 BJT Physical Operation 6.1
F 8 Documentary: “TRANSISTORIZED”
11
M 11 BJT I/V Characteristics 6.2
W 13 BJT’s at DC 6.3
F 15 **EXAM III**
12
M 18 BJT’s in Amplifier Design 6.4
W 20 BJT Small Signal Operation 6.5
F 22 BJT Amplifier Configurations 6.6
13
M 25 BJT Amplifier Configurations (Cont’d)
W 27 Biasing 6.7
F 29 Thanksgiving Holiday – NO CLASSES
14
M Dec. 2 Discrete-Circuit BJT Amplifiers 6.8
W 4 CMOS Inverters, CMOS Logic Gates 13.2 – 13.4
F 6 CMOS Inverters, CMOS Logic Gates (Cont’d)
15
M 9 **EXAM IV**
W 11 CMOS Latches, Flip-Flops 15.1
F 13 CMOS Memories 15.2
