An approach to predicting dynamic power dissipation of
coupled interconnect network in dynamic CMOS logic
circuits
HUANG Gang (
), YANG Huazhong (
), LUO Rong (
)
& WANG Hui (
)
Department of Electronic Engineering, Tsinghua University, Beijing 100084, China Correspondence should be addressed to Huang Gang (email: [email protected]) Received January 8, 2002
Abstract In deep submicron (DSM) integrated circuits (IC), coupling capacitors between
inter-connects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also in-vestigates the correlation coefficient method (CCM). Given the signal probabilities and the correla-tion coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capaci-tors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dy-namic CMOS logic circuits.
Keyword: interconnect, power estimation, coupling capacitors, correlation coefficient, dynamic CMOS logic circuits, signal probability.
With the incessant development of fabrication technologies and increasing chip density in DSM era, the parameters of interconnect have been dominant over those of gate in many aspects such as timing, noise and power dissipation. Therefore, to meet the demand of fast circuit simula-tion task and fast static analysis of circuit behaviors, it is of extreme importance to gain a reduced but accurate model of interconnect. This has caused the development of reduced-order modeling techniques[1,2], static timing analysis aiming at the existence of interconnect[3ü7]and static noise analysis with the consideration of crosstalk between interconnects[8,9], but there were few jobs done in the power dissipation of interconnect.
op-erating frequency, due to the need of SOC (system-on-a-chip) design, has made the total chip power increase. As a critical part of total power consumption, the power dissipation for intercon-nect more and more concerns VLSI designers and EDA researchers. From the 1980s to present, for each designing stage, from system-level to circuit-level, many jobs and mature tools[10ü12]are developed to predict the power consumption of CMOS digital systems. These tools have acted important roles in the verification of VLSI designs in decades, but they are not so effective in the power estimation of coupled nets for their neglecting of coupling capacitors. In the starting stage of system design, it is difficult to gain accurate power estimation since due to the lack of detailed layout data in high-level abstraction; in circuit-level, accurate results can be obtained by tedious simulation, but the long simulation time must be suffered. In order to achieve a tradeoff between speed and accuracy, a gate-level power estimation approach, which can deal with the power esti-mation problem of coupling capacitors in dynamic CMOS ICs, is presented in this paper.
The sources of power consumption in digital CMOS ICs are categorized into several types for their different internal mechanisms, and the dynamic power, namely capacitive switching power, accounts for a majority of the total power. In this paper, the type of power discussed is just dynamic power, and hereafter the term “power” is referred to as dynamic power if there is no spe-cific indication.
Static and dynamic CMOS ICs are two most widely used digital design styles adopting CMOS technology. Compared to static CMOS ICs, the dynamic one has excellent properties in many aspects: high switching speed, much fewer devices and much less chip area, and DOMINO logic circuit is a representative type of the dynamic. However, dynamic CMOS ICs consume more power than the static in the condition of the same loads and functions, since the dynamic uses a sequence of precharge and conditional evaluation phases to realize complex functions, and the value of power dissipation is determined by signal probabilities of nodes in the logic circuit, while the static uses sampling and holding phases to carry out logic functions and the power dissipation is related to the switching activities of nodes in the logic circuit. Therefore, it is of consequence to intensively study the power dissipation of dynamic CMOS ICs.
On condition that the logic block of certain dynamic CMOS gate is a pull-up block, the power dissipation of the node driven by the dynamic CMOS gate is
2 average L dd 1 ,
P =C V P f (1)
where Paveragerepresents the average dynamic power dissipation of the node, Vddthe voltage of
power supply, f the clock frequency of that node, P1the probability when the node is at 1 (the high logic level) and CLthe load capacitance which denotes the cumulative effect of the capacitors as-sociated with the node including the overlap and junction capacitors of the drain, the equivalent capacitor of the driven interconnects and input capacitors of the driven gates. For dynamic gate with pull-down block, P1 should be replaced by P0, and P0 is the probability when the node at-taches 0 (the low logic level).
Total average power consumption in a combinational logic circuit is the sum of the average power consumption of all the nodes, whereas as the size of devices is scaling down, coupling capacitance, resulting from the coupling effect between multi-layer nets and neighbor nets on the same layer, becomes increasingly notable as a critical part of total capacitance. First, it cannot be neglected that the coupling capacitors also act as a role in energy storage; second, the energy stored in coupling capacitors is never only associated with the signal in a single node, but the sig-nals in multiple coupled nodes.
This paper presents and proves: the coupling capacitor in dynamic CMOS ICs can be de-coupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor. And the power of the mapped circuit could be gained by generally-used nodal probability method (NPM) such as DWAA[10]. This paper also addresses the power estimation problem by using Cor-relation Coefficient Method[10](CCM). Given the signal probabilities and the correlation coeffi-cients between signals, the result of power dissipation in dynamic CMOS can be calculated by using CCM. It can be proved that the two methods draw equal results, that is to say, the decoup-ling method implicitly keeps correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, the coupling capacitors in static CMOS ICs could be de-coupled and mapped into more complicated logic blocks, the powers of original circuits being equal to those of the mapped ones that can be easily obtained by NPM.
1 Power model of interconnect network
Fig. 1 illustrates a dynamic CMOS gate with a pull-up block. Cdrainis the parasitic drain ca-pacitance of the transistor driving node N. Cwireis the equivalent interconnect capacitance driven by N. Cinputis the input capacitance of transistors driven by N. CL=Cdrain+Cwire+Cinputdenotes the cumulative effect of the three kinds of capacitance mentioned above. Vddis the supply voltage of
the gate.
In fig. 1, in certain clock cycle, if only taking the dynamic power into account and assuming no other sources, it can be drawn that each time when N attaches 1, power supply loses energy. During that period, CL gets charged through the pull-up block and certain amount of energy has been conveyed from the power supply to CL. iVdd defined as supply current, is equal to the
charging current ofCL, andvout(t) is defined as the transient voltage at N. Then, 2 out L L out L 0 ( ) 0 0 , dd dd dd V V V dd dd dd dd dv e i t V dt V C dt C V dv C V dt ∞ ∞ =
∫
=∫
=∫
= (2) L 2 out LL out L out out
0 ( ) 0 0 2 . dd dd V dd C V out dv C V e i t v dt C v dt C v dv dt ∞ ∞ =
∫
=∫
=∫
= (3) In eqs. (2) and (3), dd Ve is defined as the value of energy drawn from the power supply, and L
C
e represents the energy stored in CLat steady state. Also, if Q is defined as the amount of the charge in CLat steady state, from eqs. (2) and (3) it can be deduced that
L 1 1 . 2 dd 2 C V dd e = e = V Q (4)
Eq. (4) means that energy stored in CLequals half of the total power dissipation. Power dissipa-tion of interconnect BYwire
dd
V
e is define as the power consumed due to charging Cwire, and ewireis the amount of energy stored in Cwireat steady state. Then eVddBYwire can be separated from the total power dissipation as described in the following equation.
2 BYwire 2 wire wire .
dd
V dd
e = e =C V (5)
A coupled interconnect network is shown in fig. 2(a). Because of the existence of coupling capacitors, to predict total power by summing up the power of all the nodes (calculated from eq. (1)) is not feasible any more. Enlightened by eq. (5), we could separate the interconnect network from the entire circuit, and figure out the power dissipation of the interconnect network as a whole. Let eVddBYcoupledWires be the power dissipation caused by the energy storage in the interconnect network, and let ecoupledWires be the amount of energy stored in the interconnect network at steady state. Then we have
BYcoupledWires 2 copuledWires.
dd
V
e = e (6)
Fig. 2. (a) Separating the interconnect network from the whole circuit; (b) mapping the network into a pure capacitor network; (c) taking the capacitor network as a single capacitor.
At steady state, the static charge is all accumulated in capacitors. In view of power, the power dissipation of interconnect is a C-problem (only related to capacitors), while delay and noise are related to RC or even RLC. Therefore, resistors have nothing to do with interconnect power cal-culation and can be removed. Fig. 2(b) clearly displays the pure capacitor network transformed from the original interconnect network, and the simplified capacitor network could be regarded as a single “big” capacitor charged by power supply as shown in fig. 2(c). Thus the following equa-tion holds:
coupledWires 1
, 2 dd
e = V qΣ (7)
where, qΣ, the charge of the “big” capacitor at steady state, is the key parameter to computing BYcoupledWires
dd
V
e . qΣ is the total charge stored in all the capacitors at steady state and can be fig-ured out by modified nodal analysis (MNA) method[13].
We suppose the network hasm nodes and n capacitors and letAm n× , Cn n× , Vm×1 and Qn×1 represent the directional adjacent matrix, the admittance matrix, the node-voltage vector and the vector of charge stored in capacitors at steady state, respectively. By MNA method we have,
T
1 ( ),
n× = fabs
Q CA V (8)
where fabs M( ) means turning each element of matrix M into its absolute value. Therefore, qΣ can be simply calculated by summing up all the elements in Qn×1.
As an example, we calculate, by MNA methods, the amount of charge stored in a three-node network shown in fig. 3. The network includes three grounded capacitors (C1, C2, C3) and three coupling capacitors (C12, C23, C13). The voltages of the three nodes are defined as v1, v2 and v3 respectively. v1, v2 and v3 equal 0 or Vdd, i.e. V =
[
v v v1, 2, 3]
%
. The adjacent matrix A and admittance matrix C are
1 1 0 1 0 0 0 1 1 0 1 0 , 0 0 0 1 1 1 = − − − A 1 12 2 13 23 3 diag(C C, ,C C, ,C ,C ). = C (9)
Then the vector of charge stored in the 6 capacitors can be easily derived as
[
]
T 1 1 | 12( 1 2) | 2 2 | 13( 1 3) | | 23( 2 3) | 3 3 . C v C v v C v C v v C v v C v = − − − Q (10)2 Decoupling coupling capacitors by XOR gates
Perceptibly, the three elements with absolute operators in eq. (10) just represent the amount of charge stored in the three coupling capacitors, and the charge value in each coupling capacitor is determined by the signals of its nodes. If the grounded capacitors in node i, j are written as Ci
and Cj, and the coupling capacitor between the two nodes as Cij, similar to eq. (10), the amount of
charge stored in Cijcan be expressed as C vij( i −vj) at steady state of certain clock cycle, where
the values of viand vjare 0 or Vdd. Table 1 lists the voltage difference vij=vi−vj, the charge stored in Fig. 3. A three-node network with coupling
Cijin case of all possible viand vj.
Table 1 The charge stored in Cijvs. its terminal voltage viand vj
vi(logic value) vj(logic value) vij Absolute value of the charge stored in Cij
0(0) 0(0) 0 0
Vdd(1) 0(0) Vdd CijVdd
0(0) Vdd(1) Vdd CijVdd
Vdd(1) Vdd(1) 0 0
Examining table 1, it could be distinctly recognized that, after mapping |vij| into logic value
(0 to logic 0, Vddto logic 1), the logic value is the
result of an XOR operation whose inputs are the logic values at node i and j, as illustrated in fig. 4. That is to say, an XOR could decouple a coupling capacitor into a grounded capacitor.
Average power dissipation, the most concerned parameter to evaluate the power consumption of circuits, is the average power effect in a long
opera-tion with input vectors which embody the statistical properties of digital systems. Logic simula-tion with certain number of input vectors, which keep the statistical properties of primary input signals, is the foremost measure to solve the power estimation problem of digital systems. Signal probabilities are computed by analyzing the node signals captured in logic simulation. However, with the development of SOC, a chip has more and more devices and input ports. Too few input vectors would result in inaccuracy, while simulation with plethoric input vectors is a time-consuming job. Thus, with the backdrop of today’s CMOS technology and design method-ology, logic simulation is not a suitable way towards the power estimation. In recent years, a number of statistical methods are widely adopted to predict dynamic power. Given some statistical parameters (such as the probabilities and correlation coefficients between primary input signals) of digital systems, signal probabilities of interior and output nodes can be calculated by propagating those statistical parameters throughout the whole circuit. At steady state of certain clock cycle, the two circuit cells in fig. 4 are equivalent in view of power, but traditional tools based on propagat-ing statistical parameters (such as DWAA[10]) cannot effectively deal with circuits with coupling capacitors (the left part of fig. 4 is an example). Utilizing the method proposed in this paper, any coupling capacitor could be substituted by an equivalent cell, and generally-used dynamic CMOS power estimation tools work well for the decoupled network.
An approach based on correlation coefficient method is presented in the next section, and the result drawn from the approach proves that decoupling by adding an XOR gate could hold corre-lation properties of signals in the circuit. The invariance of power dissipation before and after de-coupling is guaranteed if and only if both the input and output capacitance of the XOR gate are set to zero.
3 Correlation coefficient method (CCM)
3.1 Power estimation of dynamic CMOS logic circuits
Let vk and Ckdenote the voltage and the effective grounded capacitance at node k,
respec-tively. P(k) is defined as the probability of vk=Vddat steady states. P(k) can be gained by
probabil-ity propagation method[10]. qk, the amount of charge stored in Ckat steady state, equals Ckvk, and vk
is a two-value (0 or Vdd) random variable. Then we have the mathematical expectation of qk:
( k) ( k k) k ( k) k ( ) dd.
E q E C v =C E v =C P k V (11) Obviously, E(qk) is fully determined by P(k). However, as regards the coupling capacitance Cij, we
have another story. Suppose qijis the amount of charge stored in Cij. Then,
(
)
( ij) ij( i j) .
E q =E C v −v (12)
As E(qij) is the mathematical expectation of two random variables, P(i) and P(j) could not
deter-mine it fully because it also depends upon the correlation between Viand Vj. In this paper, the term
“correlation coefficient”, firstly proposed in ref. [10], is introduced to smooth the way for it. Given two random variables X and Y, P(XY), the probability of XY (i.e. XIY), can be de-rived from P(X/Y)=P(XY)/P(Y), where P(X/Y) is the conditional probability of X given Y. Then, rX,Y, the correlation coefficient between X and Y, is defined as
, ( ) ( ) ( ) X Y.
P XY =P X P Y r (13)
Based on the conception of conditional probability, the correlation coefficient between the signals at node i and j can be expressed as
, , ( ) ( / ) ( / ) . ( ) ( ) ( ) ( ) i j j i P ij P i j P j i r r P i P j P i P j = = = = (14) As a result, , ( / ) ( )i j, P i j =P i r P j i( / )=P j r( )i j, , (15)
(
)
(
)
{
}
{
}
( ) ( ) (( ) ( 0)) (( 0) ( )) [ ( 0/ ) ( ) ( 0/ ) ( )] [1 ( / )] ( ) [1 ( / )] ( ) [1 ij ij i j ij i j ij i dd j dd i j dd dd ij dd j i dd i dd i j dd j dd ij dd ij dd E q E C v v C E v v C P v V v V P v v V V C V P v v V P v V P v v V P v V C V P j i P i P i j P j C V P = − = − = = = × + = = × = = = = + = = = = − + − = − I I{
, ,}
, ( ) ] ( ) [1 ( ) ] ( ) [ ( ) ( ) 2 ( ) ( ) ]. i j i j ij dd i j j r P i P i r P j C V P i P j P i P j r + − = + −Eq. (16) offers an effective solution for calculating the energy stored in coupled interconnect network, if correlation coefficients between signals can be figured out in advance.
Investigating the method illustrated in fig. 4 and the result drawn from eq. (16), we can see that P(i)+P(j)−2P(i)P(j)ri,j exactly represents the output signal probability of the XOR gate. It
strongly proves that the decoupling process shown in fig. 4 preserves correlation properties of signals if and only if the input and output capacitance of the XOR gate are set to zero. Propagating signals’ correlation coefficients is time-consuming, but after decoupling the original network, the problem could be readily solved by traditional power estimation methods such as DWAA proposed in ref. [10].
3.2 Energy stored in generalized interconnects CCM could also be applied to the energy storage issue of broad sense interconnects. As shown in fig. 5, in the circumstance that multiple signals (signal 1 to signal l) drive only one node, CCM can be used to compute the signal probability of the driven node.
It is easy to jump to conclusion that any signal
with a Vddvoltage can make the node attach Vdd, and in a logic sense this is just the function of an
OR gate as illustrated in the left part of fig. 6(a). To get the result of the signal probability of the node, the multiple-input OR gate ought to be mapped into a cascade of two-input OR gates since two-input gate is well applicable to CCM. Then, the output signal probability of each two-input OR gate could be worked out, and also the correlation coefficient between each OR gate’s output signal and the input signals of succeeding OR gates should be updated by adopting the method as presented below on a simple case.
Fig. 6. (a) Mapping a multiple-input OR gate into a cascade of two-input OR gates; (b) two-input OR gate and the signal of next stage.
As shown in fig. 6(b), signals a and b are input signals of certain OR gate, and signal d is the output. Signal e is assumed to be one of input signals in succeeding stages. According to the sta-tistical properties of OR gate, the probability of signal d and the correlation coefficient between signal d and signal e can be obtained by the following equations:
, ( ) ( ) ( ) ( ) ( )a b, P d =P a +P b −P a P b r (17) , , , , , , , ( ) ( ) ( ) ( ) . ( ) ( ) ( ) ( ) a e b e a e b e a b d e a b P a r P b r P a P b r r r r P a P b P a P b r + − = + − (18)
3.3 Error and complexity analysis of CCM
Without any assumption, the derivation of eq. (16) is mathematically complete, which also ensures the exactness of the method proposed in section 2. CCM could be used for calculating the power dissipation of coupling capacitors, but the result will be accompanied by errors. Because the computation of the second order correlation coefficients lead up to sharp increase in CPU time for its cubic complexity, second and higher correlation coefficients are neglected in ref. [10]. As a result, each multiple-input gate is mapped into a series of two-input gates, and fig. 7 shows the transformation of a multiple-input AND gate.
Fig. 7. Mapping three-input AND gate into a cascade of two-input AND gates.
In fig. 7, signals a, b and c are the input signals of a three-input AND gate, and signal d is the output. Signal e represents arbitrary signals related to the AND gate. Signal g is the interim signal when mapping the three-input gate into two-input gates. And the correlation coefficients rg,eand rd,eare , , , , g e a e b e r =r r (19) , , , , , , . d e g e e c a e b e e c r =r r =r r r (20)
Eqs. (19) and (20) ignore the high order correlation coefficient of signals by assuming , , , , .
g e ab e a e b e
r =r =r r (21)
Generally,1
2 n n( −1) correlation coefficients should be calculated if considering all the pos-sible correlation of
n
nodes. Therefore, in practice, the procedure of propagating first order correlation coefficients still has a O N( )
gate2 complexity, where Ngateis the number of gates. 4 Extending the decoupling method to static CMOS power estimation problemThe mechanism of the dynamic CMOS ICs is greatly different from that of the static. The charging and discharging of load capacitors in dynamic CMOS ICs are only related to the node voltages of the current clock cycle, but in static CMOS ICs the charging and discharging events occur only when the node voltages are switching from 0 to Vddor from Vddto 0 in two successive
clock cycles. Thus, when investigating the power dissipation of static CMOS ICs, the most im-portant parameter is the switching activities of nodes which are defined as the probability when the voltage of the node in two successive clock cycles are different from each other. As associated with two clock cycles, the power estimation of the static CMOS ICs is more complicated than that
of the dynamic. Here is a basic power estimation formula[13]of static CMOS ICs. 2
average L dd 0 1 ,
P =C V P→ f (22)
where Paveragerepresents the average dynamic power dissipation of a node, and P0→1 is the prob-ability that the node switches from 0 to Vdd. Other symbols are the same as those in eq. (1).
In the static CMOS ICs, the energy exported from the power supply to charge a node from 0 to Vddis twice the energy stored in the equivalent capacitor at the node. So the power consumption
of the whole static CMOS IC could be figured out by calculating the amount of charge stored in the load capacitors before the discharging phase.
Coupling capacitors between interconnects also bring trouble to the power estimation of the static CMOS ICs. Eq. (22) cannot be applied di-rectly to the circuits with multiple coupled nodes, since the energy stored in coupling capacitors is not only associated with the signal in a single node. By an analogous method similar to the one discussed in section 2 for the dynamic CMOS ICs,
the coupling capacitor in static CMOS ICs could be decoupled and mapped into an equivalent complex logic block that could be processed by traditional dynamic CMOS method such as DWAA[10].
The static CMOS block in fig. 8 has n input nodesin 1, in 2, , in nand m output nodes (out 1, out 2, , out m). Cijis the coupling capacitor between node out i and out j. The amount of
charge stored in Cijis determined by the signals of the two conjoint nodes. vsi(t), vsj(t), vij(t) and qij(t) are defined as the voltage of node i, the voltage of node j, voltage difference and the amount
of charge stored in Cijduring the tth clock cycle, respectively. In the (η −1)th andηth clock cycles,
the relation among these charge values and voltage values (also logic values) is described in table 2. qij( )η −qij(η−1) denotes the charge variance of Cijduring the two clock cycles. The positive
charge variance indicates the charge loss of power supply caused by charging Cij, while the
nega-tive means that Cijis discharging to the grounded.
When qij( )η −qij(η−1) is larger than zero, i.e. when vsi(η−1), vsj(η−1), vsi( )η and
( )
sj
v η are with the shadow values as shown in table 2, the power supply exports charge and dis-sipates power. The exported charge and consumed power satisfy the relation expressed in eq. (4). Regarding vsi(η−1), vsj(η−1), vsi( )η and vsj( )η as the input signals of certain dynamic logic circuit, the power dissipation of the dynamic logic circuit as illustrated in fig. 9(a) equals the power consumption caused by Cijin the original static logic circuits.
Table 2 The relation between the charge variance of Cijand its terminal voltage variance vsi(η −1) vsj(η −1) vsi(η) vsi(η) qij(η)−qij(η −1) 0(0) 0(0) 0(0) 0(0) 0 0(0) 0(0) 0(0) Vdd(1) CijVdd 0(0) 0(0) Vdd(1) 0(0) CijVdd 0(0) 0(0) Vdd(1) Vdd(1) 0 0(0) Vdd(1) 0(0) 0(0) −CijVdd 0(0) Vdd(1) 0(0) Vdd(1) 0 0(0) Vdd(1) Vdd(1) 0(0) 2CijVdd 0(0) Vdd(1) Vdd(1) Vdd(1) −CijVdd Vdd(1) 0(0) 0(0) 0(0) −CijVdd Vdd(1) 0(0) 0(0) Vdd(1) 2CijVdd Vdd(1) 0(0) Vdd(1) 0(0) 0 Vdd(1) 0(0) Vdd(1) Vdd(1) −CijVdd Vdd(1) Vdd(1) 0(0) 0(0) 0 Vdd(1) Vdd(1) 0(0) Vdd(1) CijVdd Vdd(1) Vdd(1) Vdd(1) 0(0) CijVdd Vdd(1) Vdd(1) Vdd(1) Vdd(1) 0
Fig. 9. (a) The equivalent circuit with the same power dissipation as Cii; (b) the equivalent circuit of fig. 9(a) when signals are
temporally independent.
It can be proved that when vsi(η−1), vsj(η−1), vsi( )η and vsj( )η are with the shadow
values, the amount of charge stored in the two grounded capacitors in fig. 9(a) equals the amount of charge pumped into the original coupling capacitor Cijfrom the (η −1)th to theηth clock cycle.
Assuming that in the original static logic block the signals on input nodes are both spatially and temporally independent, the logic values of any nodes are independent in any clock cycles. As a result, t1, t2are assumed to be two different clock cycles. Then the circuit in fig. 9(a) and fig. 9(b) are equivalent in a power sense. Connecting fig. 9(b) together with the original static logic block shown in fig. 8, we get a target circuit shown in fig. 10. If regarding the circuit in fig. 10 as a dy-namic circuit, signal probabilities and power dissipation of node w and node v can be calculated by DWAA proposed in ref. [10]. Power dissipation due to Cijin the original static logic circuit is
just the sum of the power dissipation at node w and node v, and generally-used dynamic CMOS power estimation tools can be employed on the circuit to figure out the power dissipation due to Cij.
Fig. 10. The target circuit to compute the power dissipation due to Cij.
It is assumed that in the original static logic block the signals at input nodes are both spatially and temporally independent. As a result, for the target circuit in fig. 10, the signals on its 2n input nodes must be spatially independent, which satisfies the precondition of DWAA[10].
5 Conclusion and future directions
This paper presents and proves a simple and fast approach to predicting dynamic power dis-sipation of coupled nets in dynamic CMOS ICs. Any coupling capacitor in dynamic CMOS ICs can be decoupled and mapped into an equivalent cell containing an XOR gate and a grounded ca-pacitor. And the power of the mapped circuit could be gained by generally-used NPM such as DWAA[10]. This paper also investigates the power estimation problem by CCM[10]. Given the sig-nal probabilities and the correlation coefficients between sigsig-nals, the result of power dissipation in dynamic CMOS ICs can be calculated by CCM. It can be proved that the two methods draw equal results, that is to say, the former method implicitly keeps correlation properties between signals. Moreover, the coupling capacitors in static CMOS ICs could be decoupled and mapped into an equivalent complex logic block, and the power of the circuits can be obtained by employing DWAA on the mapped static CMOS circuit. The method proposed in this paper, for both dynamic CMOS and static CMOS, could be expediently embedded into the existing dynamic power esti-mation tools such as DWAA[10].
Section 4 provides the foundation for several directions of future work. The circuit in fig. 10 is made up of two identical static logic blocks, so the size of the mapped circuit is at least twice that of the original block, which doubles the complexity of propagating the statistical parameters. Moreover, generally-used static power estimation tools (such as ref. [13]) cannot be employed on the mapped circuits in fig. 10, since the target parameter for the circuit in fig. 10 is signal prob-ability, not switching activity. To solve the problem presented above, the mapped circuit should be
constructed according to another parameter üüswitching activity. Signal probability is a static parameter to describe the performance of the circuit, and through using signal probability, the switching properties of the circuit between different clock cycles are examined by sacrificing the size of the target circuit. Switching activity can also implicitly preserve the switching property of a node, so the mapped circuit, constructed relying on switching activity, only contains one original logic block and is with almost the same size as the original circuit. Furthermore, without the as-sumption of spatial and temporal independence, how to rebuild the decoupling method is another direction.
Acknowledgements This work was supported by the National Natural Science Foundation of China (Grant No. 60025101) and in part by the National Fundamental Research Program under contract G1999032903.
References
1. Freund, R. W., Feldmann, P., The SyMPVL algorithm and its applications to interconnect simulation, in Numer. Anal. Manuscript, Murray Hill, NJ: Bell Labs., June 1997.
2. Odabasioglu, A., Celik, M., Pileggi, L. T., PRIMA: Passive reducedorder interconnect macromodeling algorithm, IEEE Trans. Computer- Aided Design, Aug. 1998, 17: 645ü654.
3. Cai Xia, Yang Huazhong, Jia Yaowei et al., RSPICE: a fast and robust timing simulator for digital MOS VLSI, IEICE Trans. Fundamentals, Nov. 1999, E82-A(11): 2492ü2498.
4. Yang Huazhong, Cai Xia, Jia Yaowei, MOS transistor model and fast timing simulator, Electronics Letters, April,1999, 35(7): 561ü563.
5. Kayssi, A. I., Sakallah, K. A., Mudge, T. N., The impact of signal transition time on path delay computation, IEEE Trans-action on Circuit and System-II: Analog and Digital Signal Processing, May 1993, 40(5): 302ü309.
6. Franzini, B., Forzan, C., Pandini, D. et al., Crosstalk aware static timing analysis: A two step approach, Proc. IEEE Int. Sym. Quality Electr. Design, San Jose, CA, March 2000, 499ü503.
7. Gao, D. S., Yang, A. T., Kang, S., Modelling and simulation of interconnection delays and crosstalk in high-speed inter-grated circuits, IEEE Trans. Circuits Syst., Jan.1990, SC-37(1): 1ü9.
8. Chen Bin, Yang Huazhong, Wang Hui, Noise estimation of deep sub-micron integrated circuits, Science in China, Ser. F, 2001, 44(5): 396ü400.
9. Chen, P., Keutzer, K., Towards true crosstalk noise analysis, IEEE/ACM Int. Conf. Comp-Aided Design, San Jose, CA, Nov.1999, 132ü137.
10. Ercolani, S., Favalli, M., Damiani, M. et al., Estimate of signal probability in combinational logic networks, 1989 IEEE European Test Conf., Paris, April, 1989, 132ü138.
11. Najm, F., A survey of power estimation in VLSI circuits, IEEE Tran. On VLSI Systems, Nov. 1994, 2(4): 446ü455. 12. Pedram, M., Power simulation and estimation in VLSI circuits, in The VLSI Handbook (ed. Chen, W.-K.), Boca Raton:
CRC Press and New York: IEEE Press, 1999, 18-1ü18-23.
13. Najm, F., Transition density, a new measure of activity in digital circuit, IEEE Trans. Computer-Aided Design, Feb.1993. 12: 310ü323.