SUN_CPU_Rev_D_Feb82.pdf

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28 Feb 1982 22:29 P.DOC[SUN,AVB] Page 1

SUN 68000 Board Rev 0 Documentation Package

February 28. 1982 VLSI SYSTEMS INC.

TRADE SECRET NOTICE:

This document contains unpublished. proprietary information and describes sUbject matter proprietary to VLSI SYSTEMS INC. This document may not be disclosed to third parties or copied or duplicated in any form without the prior written consent of an officer of VLSI SYSTEMS INC. Use of this information by third parties is governed by applicable license agreements.

COPYRIGHT NOTICE:

If, and only if, this document ;s accidentally disclosed or

TRADEMARK NOTICE:

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SUN 68000 Board Content Proprietary VLSI SYSTEMS INC. This is the engineering documention for the SUN graphics board. It includes:

Section

Table of Content Conventions Parts List

Location Summary Signal Summary Address Decoding

Connectors and Jumpers Logic Schematics, 7 pages Decoding PROM Sources Decoding PROM Object Decoding PROM Hex

Page/File

2 3 4 5

6

7

8

P1 trough P7

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SUN 68000 Board Conventions Proprietary VLSI SYSTEMS INC. How to read the logic diagrams:

Signal Definitions:

Negated logic signals, that ;s signals that are asserted active low, are indicated by a backs1ash "\" following the signal name.

For signals with multiple meanings or synonyms, the synonyms are listed separated by a slash

"I".

If a signal has multiple functions that are exclusive of each other, the names are listed separated by a vertical bar or

"I".

For example, the signal name for a read-write signal that is active low for write is "READ/WRITE\".

The inverted version of this signal would be "READ\/WRITE".

A clock that is asserted either in state 3 or 5 will be marked: C.5315. Often a group of signals share the same property.

Such groups of signals typically share the same prefix, separated from a suffix with ".".

For example, all signals driving the Multibus are prefixed with "B.". Signals that are part of busses usually share the same prefix

followed by a number. For example, the 16 data bus signals are labelled ''~O'', "01", "02", and so on up to "DI5".

Clock signals names typically contain information about

their nature as part of their signal name. There are two kinds of clocks: 1) periodic ClOCKS that are labelled C##.##-##,

where the first number is the clock period. the second number the beginning of the active clock phase. and the third number the end of the active clock phase.

2) clocks that derive from 68000 states. These clocks are labelled C.S# where # is the 68000 state they become active.

3) user-programmable clocks that are named according to their function, for example C.TIMERl is the clock from timer 1.

Part Numbers:

Part Numbers consist of one letter followed by three digits. The letter indicates the type of component and is one of:

C discrete Capacitor

J Jumper of Connector K decoupling capacitor M Memory Chip

R discrete Resistor

5 single-in-line component U dual-in-line component X Decoupling capacitor

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28 Feb 1982 22:29 P.OOC[SUN,AVB] Page 3-2

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SUN 68000 Board Parts List Proprietary VLSI SYSTEMS INC.

---GENERIC QTY BRAND PART NUMBER DESCRIPTION

--- ---~---2148 26LS29 26LS32 2764 3622 4164 7201 7406 74LS04 74LS05 74LS148 74LS163 74LS20 74L5244 74L5257 74L5299 74LS374 74LS534 74lS74 74S00 74S02 74508 74S08 74S139 74S158 74S163 74S240 74S244 74S288 7660 8205 8211 8226 8289 82S62 8303B 8304B AM2966 AM9513 C J.50 K1114A LS2518 MC68000 R7.SIP R9. SIP

7 INTEL 1 AMD 1 AMD 4 INTEL 1 SIG 36 ANY 1 NEC

1 TI

1 T I 1 T I

1 TI

1 T I

1 TI

3 TI

1 T I 1 T I

1 TI

3 AMD

2 TI

1 T I

1 TI

1 T I 1 T I 1 T I

1 TI

1 T I 2 T I

1 TI 2 TI 1 INTSIl 1 INTEL 1 INTSIL 4 INTEL 1 INTEL 2 AMD 3 AMD/NAT 4 AMD/NAT 3 AMD 1 AMD 58 AVX

2 AUGAT 1 MOTOROL 1 AMD 1 MOTOROl 3 BURNS 5 BURNS

D2148H-3 AM26LS29PC AM26LS32PC D2764 N82S131 4164 UPD7201 SN7405N SN74LS04N SN74LS05N SN74lS148N SN74lS163N SN74LS20 SN74LS244N SN74LS257N SN74LS299N SN74LS374N SN74LS534N SN74LS74 SN74S00N SN74S02N SN74508N SN74S08N SN74S139N SN74S158N SN74S163N SN74S240N SN74S244N TBP18S030N ICL7660CPA P8205 ICL8211CPA P8226 D8289 N82S62N DP8303N DP8304BN AM2966PC AM9513PC MD015CI04MAA 110-50001-102 LOCOII-16MHZ AM25LS2518 MC68000l 430BR-101-XXX 4310R-I0I-XXX

lK-BY-4 STATIC RAM 55 NSEC QUAD RS-423 DRIVER

QUAD DIFFERENTIAL LINE RECEIVER 8K-BY-8 EPROM

512-BY-4 BIPOLAR PROM

64K-BY-l DYNAMIC RAM 200 NSEC DUAL UART

HEX BUFFER OPEN COLLECTOR OUTPUT HEX INVERTER

HEX INVERTER OPEN COLLECTOR OUTPUT 8-LINE TO 3-LINE PRIORITY DECODER BINARY SYNCHRONOUS 4-BIT COUNTER DUAL 4-INPUT NAND GATES

OCTAL NONINVERTED BUFFERS QUAD DATA SEL~CTOR

EIGHT-BIT UNIVERSAL SHIFT REGISTER OCTAL REGISTER

OCTAL REGISTER INVERTING DUAL D-TYPE FLIPFLOPS QUAD 2-INPUT NAND GATES QUAD 2-INPUT NOR GATES QUAD 2-INPUT AND GATES QUAD 2-INPUT AND GATES DUAL 2-TO-4 LINE DECODER

QUAD INVERTING 2-TO-I-LI~E MUX BINARY SYNCHRONOUS 4-BIT COUNTER OCTAL INVERTING BUFFER

OCTAL NONINVERTED BUFFERS 32-BY-8 BIPOLAR PROM VOLTAGE INVERTER 3-TO-8 DECODER

PRECISION VOLTAGE COMPARATOR QUAD BUS TRANSCEIVERS

MULTIMASTER BUS CONTROLLER 9-INPUT PARITY CHECKER OCTAL INVERTING TRANSCEIVER OCTAL NON-INVERTING TRANCEIVER OCTAL DYNAMIC RAM DRIVER

LSI TIMER

DIPGUARD CAPACITORS 0.1 UF 50-PIN PCB SOLDERTAIl HEADER CRYSTAL OSCILLATOR

QUAD D-REGISTER CPU 8 MHZ

RESISTOR SIP, 7 RESISTORS RESISTOR SIP, 9 RESISTORS

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28 Feb 1982 22:29 P.oOC[SUN,AVB] Page 5

SUN 68000 Board Location Summary Proprietary VLSI SYSTEMS INC.

---LOC oIPTYPE BODY FILE POS

---CI00 C C P4 68

C101 C C P4 AB

C300 C C P4 6B

C301 C C P4 6B

C304 C C P4 01

C400 C C P4 65

C401 C C P4 B7

Jl J.50 J.50 P6 A2

J2 J.50 J.50 P6 A5

J100 J.B J.B P6 A7

JI0I K.2 K.2 P6 B5

JI02 K.2 K.2 P5 08

J400 K.B K.B P6 C7

JSOO J.4 J.4 P6 67

J900 K.2 K.2 P3 07

J90I J.I0 J.10 P6 67

J902 J.t6 J.t6 P6 A7

J903 J.4 J.4 P6 C7

K100 C C P6 01

KI06 C C P6 02

K200 C C P6 02

K201 C C P6 03

K300 C C P6 03

K400 C C P6 04

K402 C C P6 04

K403 C C P6 05

K500 C C P6 05

K501 C C P6 D1

K502 C C P6 02

K700 C C P6 02

KSOO C C P6 03

KS01 C C P6 03

KS02 C C P6 04

K900 C C P6 04

K901 C C P6 05

K902 C C P6 05

MIDD 4164 4164 P2 A3

M1Dt 4164 4164 P2 A4

M1D2 4164 4164 P2 A5

MI03 4164 4164 P2 A6

MI04 4164 4164 P2 A7

M105 4164 4164 P2 C3

MlO6 4164 4164 P2 C4

M107 4164 4164 P2 C5

M10S 4164 4164 P2 C6

M2DO 4164 4164 P2 A4

M201 4164 4164 P2 A4

M202 4164 4164 P2 A5

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28 Feb 1982 22:29 P.OOC[SUN,AVB] Page 5-2

M204 4164 4164 P2 C7

M205 4164 4164 P2 C4

M206 4164 4164 P2 C4

M201 4164 4164 P2 C5

M208 4164 4164 P2 C6

M300 4164 4164 P2 B3

M301 4164 4164 P2 84

M302 4164 4164 P2 B5

M303 4164 4164 P2 86

M304 4164 4164 P2 87

M305 4164 4164 P2 03

M306 4164 4164 P2 04

M301 4164 4164 P2 05

M308 4164 4164 P2 06

M400 4164 4164 P2 B4

M401 4164 4164 P2 84

M402 4164 4164 P2 85

M403 4164 4164 P2 B6

M404 4164 4164 P2 07

M405 4164 4164 P2 04

M406 4164 4164 P2 04

M407 4164 4164 P2 05

M408 4164 4164 P2 06

R300 R R P4 01

R301 R R P4 01

R302 R R P4 01

R900 R R P3 01

5100 R9.SIP R9.SIP P3 Cl 5101 R9.SIP R9.SIP P3 (1 5102 R9.SIP R9.SIP P4 06 5600 R9.SIP R9.SIP P1 02 S601 R7.SIP R7.SIP Pl 03 S602 R1.SIP R7.SIP P1 04 S603 R1.SIP R7.SIP P1 06 S900 R9.SIP R9.SIP P5 03 U100 26LS32 26LS32 P4 A7

U101 2764 2764 P3 A1

UI02 2764 2764 P3 A3

U103 2164 2764 P3 A2

UI04 2164 2764 P3 A5

U105 7201 7201 P4 A4

UI06 AM2966 AM2966 P2 Al U101 14L5244 74L5244 P3 C2 UI08 74L5244 74L5244 P3 C2

U109 7406 7406 P4 C5

P4 C3

P4 02

P4 04

UI10 74LS74 74LS14 P5 C8

P5 07

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28 Feb 1982 22:29 P.DOC[SUN,AVB] Page 5-3 74S02 P5 C3

P5 C3

U300 74L504 74LS04 P5 A5

P5 A4

P4 B6

P4 A6

P4 B6

U301 AM9513 9513 P4 A2

U302 8211 8211 P4 02

U400 7660 7660 P4 B6

U401 K1114A K1114A P5 Al U402 Me68000 68000 PI B1 U403 lS2518 l52518 PI Al

U404 2148 2148 PI A5

U405 2148 2148 PI A3

U406 2148 2148 PI A4

U407 AM2966 AM2966 P2 C1

U408 8226 8226 P2 A8

U409 8226 8226 P2 B8

U410 8226 8226 P2 C8

U411 8226 8226 P2 08

U500 745158 745158 P5 B6 U501 745240 745240 PI C5 U502 745288 745288 PI C3

U503 3622 3622 PI C7

U504 8304B 83048 PI A7 U505 83048 8304B PI A7 U600 7415163 74lS163 P5 A5 U601 7415299 74LS299 P5 A7 U602 745288 745288 PI C3 U603 74lS05 74L505 P4 03

P4 C3

P4 01

P4 C8

U604 2148 2148 PI 86

U605 2148 2148 PI B5

U606 2148 2148 P1 83

U607 2148 2148 PI B4

U611 AM2966 AM2966 P2 81 U700 741520 74L520\ P5 84 74L520 P5 83 U701 745163 745163 P5 A3 U702 741574 74L574 P3 C5

P4 06

U703 7415257 7415257 PI C5

U800 8205 8205 Pl 07

U801 74500 74500 P5 B3 74500\ P5 B4

PI 07

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28 Feb 1982 22:29 P.OOC[SUN,AV8] Page 5-4

P4 08

74S08\ PI 07 US04 83048 83048 PI C7 US05 83048 83048 PI B7 U900 74L5244 74L5244 P3 C4 U901 745244 74S244 P3 C6

U902 8289 8289 P3 04

U903 745240 74S240 P3 C8 U904 74LS534 74LS534 P3 86 U905 74LS374 74LS374 P5 05 U906 74LS148 74LS148 P5 07 U907 74LS534 74LS534 P3 A6 U908 74L5534 74LS534 P3 A6 U909 83038 83038 P3 A8 U910 83038 83038 P3 B8 U911 83038 83038 P3 A8 U912 74S139 74S139 P2 01

P3 C6

XIOO C C P6 C1

XIOI C C P6 C2

XI02 C C P6 C2

XI03 C C P6 C3

XI04 C C P6 C3

XI05 C C P6 C4

XI06 C C P6 C4

XI07 C C P6 C5

XI08 C C P6 C5

X200 C C P6 01

X201 C C P6 02

X202 C C P6 02

X203 ·C C P6 03

X204 C C P6 03

X205 C C P6 04

X206 C C P6 04

X207 C C P6 05

X208 C C P6 05

X300 C C P6 01

X301 C C P6 02

X302 C C P6 02

X303 C C P6 03

X304 C C P6 03

X305 C C P6 04

X306 C C P6 04

X307 C C P6 05

X308 C C P6 05

X400 C C P6 01

X401 C C P6 02

X402 C C P6 02

X403 C C P6 03

X404 C C P6 03

X405 C C P6 04

X406 C C P6 04

X407 C C P6 05

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SUN 68000 Board Signal Summary Proprietary VlSI SYSTEMS INC.

---Mnemonic Description

---

---'~--~----AO .. A23 ACK\ AEN AS

B. AO\ .. A19\ B.AACK\ B.BCLK\ B.BHEN\ B.BPRN\ B.BPRO\ B.BREQ\ B.BUSY\ B.CBRQ\ B.CCLK\ B.DO\ .. 015\ B.INH1\ .. 2\ B.INIT\

B. INTO\ .. INT7\ B.INTA\

B.IORC\ B.IOWC\ B.MRDC\ B.MWTC\ B.XACK\ BCLK\ INIT\ B/l\ BERR BHEN BOOT BOOT READ C.Pt C.P2 C.REFRESH C.TIMER1 C.TIMER2 CASO\ .. 3\ CE.BYTE\ CE.PMAP\ CE.PROMO\ CE.PROM1\ CE.SIO\ CE.SMAP\ CE.SPARE\ CE.WORO\ CEN\ CLR.BOOT\ CTSA\ CXO .. 3

68000 Address Bus Acknowledge

Address Enable

68000 Address Strobe Multibus address bus (20)

UNUSED. Multibus advanced acknowledge Multibus bus clock

Multibus byte high enable Multibus priority in Multibus priority out Multibus bus request Multibus busy

Multibus common bus request Multibus constant clock Multibus data bus (16) Multibus inhibit lines Multibus init

Multibus interrupt request

UNUSED Multibus interrupt acknowledge Multibus I/O read control

Multibus liD write control Multibus memory read control Multibus memory write control Multibus trasfer acknowledge Onboard Bus Clock

Onboard INIT Bus/Local\ Bus Error

Bus High Enable Boot

Boot and Read

Clock Serial Port 1 Cleek Serial Port 2 Clock Refresh

Clock Timer 1 Clock Timer 2

Column Address Strobe 0 .. 3 Chip Enable Byte Buffer Chip Enable Page Map Chip Enable PROM Set 0 Chip Enable PROM Set 1 Chip Enable Serial I/O Chip Enabel Segment Map UNUSED

Chip Enable Word Buffer Multibus Control Enable Clear Boot State

(11)

28 Feb 1982 DO .. 15 DCDA\ DIRTY DS DTACK DTRA\ EN.PMAX\ FCO .. 2

HALT\ HARDRESET INO .. 16 INIT INT.SIO\ INT.TIMER2\ INTlS\ .. 7S\ IO/M\

IPLO\ LDS

M.AO\ .. A7\ M.CASO\ .. CAS3\ M.DIO .. M.OIl5 M.DIL

M.DIU

M.DOO .. M.D015 M.DOL

M.DOU M.RASL\ M.RASU\ M.REF\ M.WE\ MA 11 .. 22 MRDC\ MWTC\ OE.CX\ OE.PORT\ OE.RAM\ OE.TIMER\ Pl.CTS Pl.DSR Pl.0TR Pl.RTS Pl.RXO P1.TXD P2.RXD P2.TXD PAR. EN PAR. ERR PARERRL PARERRU PMAP.ERR\ PROTO .. 3

PU .. PU3

R/W\

ROO\ RESET

22:29 P.DOC[SUN,AVB] Data Bus (16)

Data Carrier Detect Port

A

Modify Bit in Page Map Data Strobe

Data Transfer Acknowledge Data Terminal Ready Port A Enable Page Map Extension 68000 Function Codes (3)

68000 Halt Power On Reset Input Port (16) Onboard INIT

Interrupt Serial I/O Interrupt Timer 2

Interrupt Synchronized (7) IO/Memory\

68000 Interrupt Priority Level (3)

Lower Data Strobe Memory Address Bus

Memory Column Address Strobes (4)

Memory Data In Bus (16) Memory Data In Parity Lower Memory Data In Parity Upper Memory Data Out Bus (16) Memory Data Out Parity Lower Memory Data Out Parity Upper Memory Row-Address Strobe Lower Memory Row-Address Strobe Upper Memory Refresh

Memory Write Enable Strobe Mapped Address (12)

Memory Read Control Memory Write Control

Output Enable Context Register Output Enable Port

Output Enable RAM Output Enable Timer Portl Clear To Send Portl Data Set Ready Portl Data Terminal Ready Portl Ready To Send

Port1 Receiver Data Port1 Transmitter Data Port2 Receiver Data Port2 Trasmitter Data Parity Enable

Parity Error

Parity Error Lower Parity Error Upper Page Map Error Protection (4)

Pull-up Read/Write\

Read Data from Multibus 68000/7201 Reset

(12)

28 Feb 1982 RTSA\

RXDA RXDB

SET.INIT\ SMAP.ERR\ SYS.ACCESS\ TIMEOUT TXDA TXDB UDS USED VCC VEE WE.CX\ WE.PMAP\ WE.PMAX\ WE.RAM\ WE.SMAP\ WE.TIMER\ XA15 .. 20 XACK

22:29 P.DOC[SUN,AVB] Ready To Send A

Receive Data A

Receive Data

B

Set Init\

Segment

Map

Error System Access Timeout Error

Transmit Data Port A Transmit Data Port 8

Upper Data Strobe

Used (Accessed) Bit in Page Map +5V

-5V

Write Enable Context Register Write Enable Page Map

Write Enable Page Map Extension Write Enable RAM

Write Enable Segment Map Write Enable Timer

Intermediate Address (6)

Transfer Acknowledge

(13)

SUN 68000 Board Address Decoding Proprietary VLSI SYSTEMS INC. On-board Device Addresses

All addresses are in hexadecimal.

The actual amount of physical RAM and PROM depends on the system configuration. Note that unused address bits are not further decoded.

All locations are read and write. except those explicitely marked.

Address Data

000000 .. 1FFFFF 0 .. 15 000000 .. 03FFFF 0 .. 15 200000 .. FFFFFF O .. 15 200000 .. 23FFFF 0 .. 15

400000 .. 43FFFF O .. 15 600000 .. 600006 8 .. 15

Description

Logical address space. (Write-O.ly during boot). PROMO during boot state (Read-Only).

System address space (available to supervisor only). On-Board PROMO (Read-Only).

Exit boot state (Write-Only). On-board PROMl.

UART 600000 600002 600004 600006

Uart A Data Register Uart A Command Register Uart B Data Register Uart B Command Re9ister 800000 .. 800002 0 .. 15 Timer

AOOOOO .. BFF800 0 .. 15

800000 Timer Data Register 800002 Timer Command Register Page Map.

0 .. 11 Physical Address Bits 11 .. 22 12 .. 13 Physical Address Space

a -

On-board RAM 1 - Non-existing page 2 - Multibus memory space 3 - Multibus I/O space 14 Modified Bit

15 Accessed Bit

The page map is addressed through the segment map and via address bits Al1 .. A14 from the processor. The lower order 11 address bits are ignored. When the segment map is initialized to idendity, page n is located at address AOOOOO + n * 2tl1. AOOOOO

A00800

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28 Feb 1982 22:29 P.DOC[SUN.AVB] Page 7-2

BFF800 Page 3FF COOOOO .. DFF8~0 0 .. 15 Segment Map

EOOOOO

O •• 5 6 •. 7 8 .. 11 12 .. 15

Virtual address bits 15 .. 20 Reserved for future use Protection bits

Current Context (Read-Only)

Segment n is located at address COOOOO + n

*

2~15.

The lower order 15 address bits are discarded. COOOOO Segment 0

C08000 Segment 1 DF8000 Segment 3F

0 .. 15 16-bit input port (Read-Only)

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28 Feb 1982 22:29 P.OOC[SUN,AVB] Page 8

SUN 68000 Board Connectors and Jumpers Proprietary VLSI SYSTEMS INC. Connectors, Cablest and Jumpers:

" " indicates a connector pair

tt • • " indicates default (pre-wired) connection

JI-Connector:

Prewired to be a DCE on Port 1 and a OTE on Port 2.

VCC J1-01 Se ria 1 Port 1 Pin 25. +5 Volt P1.TXD J1-03 Se ria 1 _{Port 1 Pin 2, Transmit Data}

P1.RXD J1-05 Se ria 1 Port 1 Pin 3, Receive Data Pl. GND J1-13 Se ria 1 Port 1 Pin 7, Signal Ground SET.INIT\ J1-18 Se ria 1 Port 1 Pin 18, Set.INIT\

P2.TXD J1-28 Se ria 1 Port 2 Pin 2, Transmit Data P2.RXD Jl-30 Se ria 1 Port 2 Pin 3, Receive Data P2.GND J1-38 Se ria 1 Port 2 Pin 7, Signal Ground J1-Cable:

Use a 50-wire flat cable and split it into two 25-wire strands. Connect a female OB-25 flat cable connector pin 1 to wire 1 of cable (terminal side) and connect a male 06-25 flat cable connector pin 1 to wire 25 of cable (computer side).

J2-Connector: INO

IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 SEl.INIl\

M.REF\

vee

P2 Serial Port:

JI-01 JI-03 JI-05 JI-07 JI-09 Jl-l1 J1-13 JI-15 Jl-17 Jl-19 Jl-21 JI-23 JI-25 JI-27 JI-29 Jl-31 JI-45 .. 46 Jl-47 Jl-49

Input Bit 0 Input Bit 1 Input Bit 2

Input Bit 3 Input Bit 4 Input Bit 5 Input Bit 6 Input Bit 7 Input Bit 8 Input Bit 9 Input Bit 10 Input Bit 11 Input Bit 12 Input Bit 13 Input Bit 14 Input Bit 15

Active contact of IN!T toggle Halt indicator output

Halt indicator supply

(16)

28 Feb 1982 P2.RxD P2.TxD P2.RxD P2.TxD

PROM Type: Prewi red 2764/2732 2716

22:29

J100-1: : 2 J100-3: :4 J100-1 .. 3 JI00-2 .. 4

for 2732/2764 JI00-7::8 JI00-5 .. 6

Multibus Signals:

P.DOC[SUN,AVB] Page 8-2

Connects P2.RxD as DTE Connects P2.TxD as DTE Connects P2.RxD as DCE Connects P2.TxD as DCE

[PROMs.

Connects UI0l: :UI04(23) to Al2 Connects U101::UI04{23} to

vce

Prewired for a system where the 68000 is reset-master and cluck-master. B.INIT\ J901-1 .. 2 Drive INIT from Multibus

Remove J901-3::4 if used. B.INIT\ J90 1-3: : 4 Drives INIT to Multibus B.BCLK\ J901-5::6 Drives BCLK to Multibus B.BPRN\ J901-7::8 Grounds BPRN for last master B.CCLK\ J901-9::10 Drives CClK to Mu1tibus

B.MRDC\ J900-1 .. 2 Connect for operation without B.MWTC\ J900-3 .. 4 Connect for operation without B.IORC\ J900-5 .. 6 Connect for operation without B.IOWC\ J900-7 .. 8 Connect for operation without ADEN\ J900-9 .. 10 Connect for operation without Interrupt Level Assignment:

Prewired to standard interrupt assignments

with on-board interrupts isolated from Multibus. B.INT7

B.INT6 B.INT5 B.INT4 B.INT3 B.INT2 B.INTI

B. INTO

J902-1 .. 2 J902-3 .. 4

J902-5 .. 6

J902-7: :8 J902-9: : 10 J902-11::12 J902-13::14 J902-15::16 Memory expansion board:

M.CASO\ M.CAS1\

J903-1 .. 3 J903-2 .. 4

non-maskab1e interrupt, used by refresh timer used by on-board Timer2 used by on-board UART

not used

Drives M.CASO\ from M.CAS2\ Drives M.CASl\ from M.CAS3\

in chain.

(17)

Lsiiii"

016 1 00U48~ 2 CU

014 _~_{01 01}₆ Cll 013 _tz_{02 02}₁₁ CXl OIl _a_{03 03 14} 00

yo 3 015 VI 6 014

'1'1 10 01~

'1'3 13 012 ell Of

Wf. cn

:Pp

OE. ex\

r

-e MC6800

00 00

~

01 01

02 02

03 OJ

I ₀₄ 0' II ₀₁₁ 05 II

011 De

liz ₀₇ 07

et _De 08

lie ₀₉ 0;

119 ₀₁₀ DID

118

011 011 II ₀₁₂ Oil lie ₀₁₃ 013 65

014 014 54 ₀₁₆ 015 29 _A1 A1 30 _A2 AZ 31

A3 A3

3 _A4

""

3 _A5 A6 3 _All All 3! _A7 A7 3! _AI! AI 3 _1.9 A,

31

AID Ala 35 _All 1.\1 4C _A\2 A12 41 _.a₁₃ 1.13 'I _1.14 AI' 'J 1.16 1.16 ,~

Atll 1.16 4! _A17 1.17 4! _AU All

,

_At; 1.19

'8 _A20 A2D

lie _1.21 1.21 U _A22 AU III _AZ3 1.23 ! _AS\ AS\ UDS\ UDS\ !

LOS\ LOS\ ~ _R/Ii\ lIIli\ OTACI(\

1C DTACK\

21 _FCO FCO 27 _Fel FCt

211 _FCZ FCZ

IPLO\ ZIi JPlO\ IPl t\ 2 _IPl1\

IPLZ\ 2 _IPlZ\

vce 1 _111\ 1

IG\ vee 1 _IACl\

"""'ITii""

-zm-ulloe UIID7 1.12 _{6 AD} _II_AD 1.\3 _II_Al _I!_AI A14

, A2 AZ

All A3 , 1.3

lAID 3",

'"

lAle _Ali _Ali

XAI7 _{1 All} _{1 All} XAI8 _{1 A7} _{I 1.7}

UI9 HAS Ie 1.8

XAZD _{15 All} _151.9 IIf PMAP\ ID

liE 10 liE

~Ol ~Ol

~OZ ~02

~03 ~ 03

~ _{04 CS} !!!1L1.! 0' CS

GNO

,--

Ie

usus

~A2:.:3=--_ _ _ ...:..:j A~50Jo I A2Z 01 Z eE. PROMO\ A21 OZ 3 CE.SIO\ BOOTA E AD 03 4 C E . PROMt \ Fez 04 II CE. SPARE\ 011 I! CE. PMAP' oe 7 CE .SMAP\ 07 II SYS.AceESS\

74S281

All t A~eoJO I WE .SMAP'

All' _{01 1 CLR.}loon

A21 _{01 3} WE. TIMER\ R/W' _{03 '} DE. TIMER\ Fez _0'_&WE. PMAP\

06 I! VE .en 06 7 OLen 07 II OE .PORT\

OS\

2148 U404

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28 Feb 1982 22:28 PO.SAI[SUN,AVB]

comment Proprietary VLSI SYSTEMS INC.:

begin "pO"

require "prom.sai" sourcelfile: $32;

define

a23 =[aO],

a22 =[al],

a21 =[a2],

boot =[a3],

fe2 =[a4].

adrs =[(cvb(a23)·d2 + cvb(a22)*dl + cvb(a21)*dO)].

s.access=[(boot v (adrs > 0»],

ce.promD=[(fc2 A «adrs=l) v boot A (adrs=O»)].

ce.proml=[(fc2 A (adrs=2»],

ce.sio =(fc2 A (adrs=3»].

ce.timer=[(fc2 A (adrs=4»].

ce.pmap =[(fc2 A (adrs=5»].

ce.smap =[(fc2 A (adrs=6»];

prombegin

prom(O, dO, prom(O, dl, prom(O, d2, prom(D, d3, prom( 0, d4, prom(O, d5, prom(O, d6, prom(O, d7,

"'ce.timer); ... ce.promO); "'ce.sio); "'ce.proml); 0) ;

"'ce.pmap): "'ce.smap); "'s.access);

promend;

writeprom("pO",O); end;

(25)

28 Feb 1982 22:28 P1.SAI[SUN,AVB]

comment Proprietary VlSI SYSTEMS INC.; begin "pt"

require "prom.sai" soureelfile; $32;

define

a23 =[aO],

a22 =[al],

a21 =[a2],

read =[a3],

fe2 =[a4],

adrs =[(evb(a23)*d2 + evb(a22)*dl + evb(a21)*dO)],

write =[(~read)].

clr.boot=[(fc2 1\ write 1\ (adrs=l»].

oe.timer=[(fe2 1\ read 1\ (adrs=4»].

we.timer=[(fc2 1\ write 1\ (adrs=4»)] •

we.pmap :[(fc2 1\ wr ite 1\ (adrs=5»] •

we.smap =[(feZ 1\ write 1\ (adrs=6»].

oe.cx =[(fcZ 1\

we.cx = [ ( f e 2 1 \

oe.port =[(fe2 1\

prombegin

prom(O, dO, prom(O, dl, prom( 0, d2, prom(O, d3, prom(O, d4. prom(O, d5, prom(O, d6, prom( O. d7.

read 1\ (adrs=6»].

wr ite 1\ (adrs=7»)].

read 1\ (adrs=7)));

~we. smap);

~clr.boot); ~we.timer); ~oe.timer); ~we.pmap); -we. ex): ... oe.ex); "'oe.port):

promend:

writeprom("pl",O): end;

(26)

28 Feb 1982 22:29 P2.SAI[SUN.AVB] Page I

comment Proprietary VLSI SYSTEMS INC.;

begin "p2"

require "prom.sai" sourcelfile;

$512;

define

protl prot2 prot3 protO

sys.access.i fcl

fcO read fe2

prot

sys.aecess execute.cycle read. cycle write.cycle

protcode

en.access

prombegin

prom(O, dO, prom(O, dl, prom( 0, d2, prom(O, d3,

=[aO], =[al], =[a2], =[a3], =[a4], =[a5], =[a6], =[a7], =[a8],

=[(cvb(protO)·dO +cvb(protl)·dl +cvb(prot2)·d2 +cvb(prot3)·d3)], =[(~sys.access.i)],

=[( fcl A ~fcO A read)],

=[(~fcl A fcO A read)],

=[(~fcl A fcO A~read)],

=[(case prot of (

" _{- - - ,}" "_x_" ,

"r _ _ ", "r_x_",

"rw _ _ ",

"rwx_", "r_r_", "rw_r_", "r_rw_", "rw_rw_", "rw_r_x", "rw_rwx", "r_xr_x", "rwxr_x", "rwx_x", "rwxrwx") )] ,

=[(~sys.access A (

fc2 A read.cycle A protcode[1 for 1]="r"

v fc2 A write. cycle A protcode[2 for 1]="w"

v fc2 A execute.cycle A protcode[3 for 1]="x"

v~fc2 A read. cycle A protcode[4 for l]="r"

v~fc2 A write.cycle A protcode[5 for 1]="w"

v~fc2 A execute.cycle A protcode[6 for 1]="x"

»] :

0); . 0);

en.access): ~en.access);

promend;

(27)

24 Dec 1981 16:18 PO.HEX[SUN,AVB]

:10000000EF6F6F6F6F6F6F6F6F6F6F6F6FoF6F6F80 :10001000EF6E672F6D4F6B6F6D6E672F6D4F6B6F50

:0000000000

(28)

24 Dec 1981 16:18 P1.HEX[SUN,AVB]

:10000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFOO :10001000FFFBFFFEFOEFFFOFFFF7FFBFFFFFFF7FEF :0000000000

(29)

24 Oec 1981 16:18 P2.HEX[SUN.AVB]

:100000000808080808080808080808080808080870 :100010000808080808080808080808080808080860 :100020000808080808080808080808080808080860 :100030000808080808080808080808080808080840 :100040000808080808080808080808080808080830 :100050000808080804080808080808080404080430 :100060000808080808080808080808080808080810 :100070000808080808080808080808080808080800 :1000800008080808080808080808080808080808FO :1000900008080808080808080808080808080808EO :1000A0000808080808080808080808080808080800 :100080000808080808040404080808080804040408 :1000C00008080808080808080808080808080808BO :1000D00008080804040404080808080404040404C4 :1000E0000808080808080808080808080808080890 :1000F0000808080808080808080808080808080880 :10010000080808080808080808080808080808086F :10011000080808080808080808080808080808085F :10012000080808080808080808080808080808084F :10013000080808080808080808080808080808083F :10014000080808080808080808080808080808082F :100150000808040808040804080804040404040443 :10016000080808080808080808080808080808080F :1001700008080808080808080808080808080808FF :1001800008080808080808080808080808080808EF :10019000080808080808080808080808080808080F :1001AOOOOB0808080B0808080808080808060808CF :10016000080B080808080404040404080808040408 :1001C000080808080808080808080808080e0808AF :100100000804040404040404080404040404040407 :1001E000080808080808080808080808080808088F :1001F000080806060806080808080808080808087F :0000000000