GATE+ISRO DIGITAL LOGIC AND COMPUTER ORGANIZATION 2015_sequential circuits

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GATE

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ISRO 2015

( Quick Reference )

Computer Science & Information Technology

( Digital Logic

+

Computer Organization )

( First Edition )

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Preface

Dear Reader, Dear Reader,

Please hang on a minute and just read through before proceeding further. Please hang on a minute and just read through before proceeding further. “ If you want to know the an

“ If you want to know the answer of any ‘ Compswer of any ‘ Computer Oruter Organizatganization ’ ion ’ or or ‘ Digital Lo‘ Digital Logic ’ pregic ’ previous yeavious yearsrs ‘ GATE

‘ GATE / / ISRO ’ ISRO ’ question, question, don’t go don’t go and and search the search the Google!, just Google!, just search through thsearch through this is book.book.”” This book

This book is dedicated to is dedicated to all those all those preparpreparing for ing for GAGATE, ISRO and other TE, ISRO and other competicompetitivtive e examiexaminationsnations. . It is It is orgaorganizednized into two parts covering subjects Digital logic & Computer organization. First part on Digital logic and second part into two parts covering subjects Digital logic & Computer organization. First part on Digital logic and second part on Computer organization.

on Computer organization. Eac

Each h parpart t is futher diviis futher divided into sectioded into sections. ns. EacEach h secsectiotion n incincludeludes s the requithe required theorred theory y parpart t in in bribrief as ef as welwell l as theas the pre

previous years GAvious years GATE and TE and ISRISRO O questiquestions with ons with explaexplanationsnations. . WWe e tried to tried to includeinclude GATE GATE questions questions from 1992 till from 1992 till 2014

2014 and and ISRO ISRO questions questions from 2007 till 2014 from 2007 till 2014. Each and every question is answered in simple and lucid manner.. Each and every question is answered in simple and lucid manner. Patt

Pattern based question orderinern based question ordering is g is used in used in this book. this book. QuestiQuestions having similar structons having similar structure are grouped in ure are grouped in a mannera manner that the answers can be linked. We believe, “ Pattern based question ordering ” will help you to improve your skills that the answers can be linked. We believe, “ Pattern based question ordering ” will help you to improve your skills in problem solving in

in problem solving in those areas descrithose areas described in bed in the book.the book.

The theory parts in brief will help you as a “ Quick reference ” to revise the concepts and formulas. We hope, this The theory parts in brief will help you as a “ Quick reference ” to revise the concepts and formulas. We hope, this book will give you a clear insight into the solutions and the way of solving problems.

book will give you a clear insight into the solutions and the way of solving problems.

Constructive suggestion and criticism always go a long way in enhancing any endeavor. We request you to respond Constructive suggestion and criticism always go a long way in enhancing any endeavor. We request you to respond with your valuable comment

with your valuable comment / / viewsviews / / feedbafeedback for ck for the bettermethe betterment of nt of this book this book at:at: https:

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Wish you sh you all the best.all the best.

R

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Part I

D I G

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1

S E Q U E N T I A L C I R C U I T S

A sequential circuit is a digital logic circuit, whose output value depends on present and past inputs. It includes A sequential circuit is a digital logic circuit, whose output value depends on present and past inputs. It includes a combinational circuit and memory element.

a combinational circuit and memory element.

1.1

1.1 f l i p f l i p

--

f l o p sf l o p s

A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit) until A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit) until direc

directed by ted by an input signal to an input signal to switch stateswitch states.s. 1.1.1

1.1.1

Basic

Basic Flip-ﬂop

Flip-ﬂop circ

circuits

uits

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1.1.2

Note:

Duty cycle :

Duty cycle : It It is the percentais the percentage of one ge of one period in which signal is actiperiod in which signal is active. ve. Duty cycle of 60% means theDuty cycle of 60% means the signal is ON for 60% of time and OFF for 40% of time.

signal is ON for 60% of time and OFF for 40% of time. Propagation delay :

Propagation delay : It is the time a flip-flop takes to change its output afteIt is the time a flip-flop takes to change its output after the clock edge.r the clock edge. Race around condition :

Race around condition : In JK flIn JK flip floip flop, whep, when Jn J==1 and K1 and K==1 a 1 a toggtoggling occling occursurs. . SinSince clocce clock pulsek pulse is more than propagation delay, within on clock pulse the output keep on toggling again and again and is more than propagation delay, within on clock pulse the output keep on toggling again and again and output become indeterminate. This situation is known as

output become indeterminate. This situation is known as race around condition. race around condition.

Master Slave Flip ﬂops :

Master Slave Flip flops : This is This is a cascade of flip flop a cascade of flip flop arraarrangementngement, in , in which first one (masterwhich first one (master) responds) responds with clock high and second (slav

with clock high and second (slave) responds with clock lowe) responds with clock low. . Thus the ﬁnal output changes only whenThus the ﬁnal output changes only when clock is low. Thus race around condition is get eliminated.

clock is low. Thus race around condition is get eliminated.

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1.1.3

1.1.3 Flip-ﬂops Flip-ﬂops - [GA- [GATE QueTE Questions] stions] 1.

1. In an SR latch made by cross-couplIn an SR latch made by cross-coupling two NANing two NAND gates, if both S and R D gates, if both S and R inputs are set to 0, then it will resultinputs are set to 0, then it will result in

in

[GATE-2004 CS] [1 mark] [ISRO-2007]

2.

2. Which of the following input sequences for a Which of the following input sequences for a cross-coupled R-S flip-flop realized with two Ncross-coupled R-S flip-flop realized with two NAND gates mayAND gates may lead to an oscillation?

lead to an oscillation?

[GATE-2007 IT] [1 mark]

3.

3. In the sequential circuIn the sequential circuit shown belowit shown below, if , if the initial valuthe initial value of e of the outputthe output QQ11QQ00 isis 00 00, what are the next four, what are the next four

values of

values of Q Q11QQ00??

[GATE-2010 CS

[GATE-2010 CS & & IT] IT] [2 [2 mark] mark] [ISRO-2014][ISRO-2014]

4.

4. The folloThe following arrangewing arrangement of master-ment of master-slavslave flip flopse flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively), has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

[GATE-2000 CS] [2 mark] [GATE-2000 CS] [2 mark] 15 15                                                                                                                                                                     

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5.

5. The folloThe following synchronwing synchronous sequentiaous sequential circuit built using JK flip-flops is initialil circuit built using JK flip-flops is initialized with Qzed with Q22QQ11QQ00 = = 000.000.

The state sequence for this circuit for the

The state sequence for this circuit for the next 3 next 3 clock cycleclock cycles iss is

[GATE-2014 SET-3] [2 mark]

6.

6. ConsConsideider the circr the circuit in the diaguit in the diagramram. . TheThe ⊕⊕ operator represents Ex-OR. The D flip-flops are initialized to operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared)

zeroes (cleared)

The following data: 100110000 is supplied to the "data" terminal in nine clock cycles. After that the values The following data: 100110000 is supplied to the "data" terminal in nine clock cycles. After that the values of

of qq22qq11qq00 are : are :

[GATE-2006 CS] [2 mark]

7.

7. ConsideConsider the followir the following state diagrang state diagram and its realizatim and its realization by a on by a JK flip-flop.JK flip-flop.

The combinational circuit generates J and K in terms of x,y and Q. The Boolean expression for J and K are: The combinational circuit generates J and K in terms of x,y and Q. The Boolean expression for J and K are:

x

x⊕⊕ y y xx⊕⊕ y y xx⊕⊕ y y

⊕ ⊕ y y

16 16                                                                                                 ⊕⊕       ⊕⊕     xx     ⊕⊕      ⊕⊕  

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8.

8. YYou are given a free running clock with a ou are given a free running clock with a duty cycle of 50% and duty cycle of 50% and a digital wava digital waveformeform f f which changes only which changes only at the negativ

at the negative edge e edge of the clock. of the clock. Which one of Which one of the followthe following circuits (using clocking circuits (using clocked D ed D flip-floflip-flops) will delayps) will delay the phase of

the phase of f f by 180 by 180◦◦ ?? (a) (a) (b) (b) (c) (c) (d) (d) [GATE-2006 CS] [1 mark] [GATE-2006 CS] [1 mark] 9.

9. ConsideConsider the follor the following circwing circuit.uit.

The flip-flops are positive edge triggered D flip-flops. Each state is designated as a two bit string Q

The flip-flops are positive edge triggered D flip-flops. Each state is designated as a two bit string Q00QQ11. Let. Let

the initial state be 00.

the initial state be 00. The state transitiThe state transition sequence is:on sequence is:

(a) (a) (b)(b) ((cc)) ((dd)) [GATE-2005 CS] [2 mark] [GATE-2005 CS] [2 mark] 17 17

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10.

10. ConsideConsider the followir the following circuit with initing circuit with initial state Qal state Q00==QQ11==0. The D Flip-ﬂops are positive edge triggered and0. The D Flip-ﬂops are positive edge triggered and

have set up times 20 ns and hold times 0. have set up times 20 ns and hold times 0.

Consider the following timing diagrams of X and C; the clock period of C

Consider the following timing diagrams of X and C; the clock period of C≥≥40 ns.40 ns. Which one is the correct plot of Y?

Which one is the correct plot of Y?

11.

11. Consider the following circuit inConsider the following circuit involving a positive edge triggered D volving a positive edge triggered D flip-flop.flip-flop.

Consider the following timing diagram. Let A

Consider the following timing diagram. Let Aii represent the logic level on the line A in i represent the logic level on the line A in ithth clock period.clock period.

Let A’ represent the complement of A. The correct output sequence on Y over the clock period 1 through 5 Let A’ represent the complement of A. The correct output sequence on Y over the clock period 1 through 5 is is 1 1 11 33 44 11 22 33 44 22 22 33 44 22 33 44 55 [GATE-2005 CS] [2 mark] [GATE-2005 CS] [2 mark] 18 18     00            00             11            11          

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1.1.4

1.1.4 Flip-ﬂops Flip-ﬂops - [ISR- [ISRO QuO Questions] estions] 1.

1. In an RS flip-flop, if the S In an RS flip-flop, if the S line(line(Set line) is set high(1) and the R line(ReSet line) is set high(1) and the R line(Reset line) is set low(0set line) is set low(0), then the state), then the state of the flip flop is

of the ﬂip ﬂop is

[ISRO - 2011 CS]

2.

2. The charaThe charactericteristic equatistic equation of an SR on of an SR flip flop is given byflip flop is given by

1 1 QQnn SS QQnn + +11 S S nn RR nn [ISRO - 2007 CS] [ISRO - 2007 CS] 19 19                                                     nn++      nn     nn++11         nn           nn++11     

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1.2

1.2 r e g i s t e r s r e g i s t e r s

&

c o u n t e r s c o u n t e r s

1.2.1

Registers

Regis

Registers are memory deviceters are memory devices that s that can be can be used to used to store more than one store more than one bit of bit of informinformation.ation.

Shift Registers

A register that provide the ability to shift its contents is known as shift registers. A register that provide the ability to shift its contents is known as shift registers.

Linear Feedback Shift

Linear Feedback Shift Registers

Registers

A Linear Feedback Shift Register is a shift register whose input bits is a linear function of previous A Linear Feedback Shift Register is a shift register whose input bits is a linear function of previous state.

state.

In the above example input bit at A

In the above example input bit at A33 is is determdetermined by XORed combination of bits Ained by XORed combination of bits A00 and A and A22, with every, with every

opera

operation a tion a bit is bit is shiftshifted right.ed right. 1.2.2

1.2.2

Counters

Counters are sequential circuits which goes through a sequence of states upon application of input Counters are sequential circuits which goes through a sequence of states upon application of input pulses.

pulses. Modulus Modulus of a counter is the number of unique state a counter may have. of a counter is the number of unique state a counter may have. Two types of counters:

Two types of counters:

•

• Ripple counter Ripple counter (Asynchronous)(Asynchronous)

•

• Synchronous counter Synchronous counter

Ripple

Ripple counter

counter

In a

In a Ripple counteRipple counter, the flip flop r, the flip flop output transioutput transition serves as a tion serves as a source for triggersource for triggering other flip ing other flip flops.flops.

20 20

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Synchronous counters

In synchronous sequential circuits, all the flip flop’s clock input are applied to the same clock signal, In synchronous sequential circuits, all the flip flop’s clock input are applied to the same clock signal, so that all flip flop output changes at the same time.

so that all ﬂip ﬂop output changes at the same time.

Ring counter

A Ring counter is composed of a circular shift register, where the output of last shift register is fed A Ring counter is composed of a circular shift register, where the output of last shift register is fed back to input of ﬁrst register. This counter circulates a single

back to input of ﬁrst register. This counter circulates a single 1 1 around the ring. around the ring.

A ring counter can also be represented using a combination of up counter and n to 2

A ring counter can also be represented using a combination of up counter and n to 2nndecoder circuit.decoder circuit.

In a ring counter, count is read by noting which flip flop is in state 1. The output pulse of one stage In a ring counter, count is read by noting which flip flop is in state 1. The output pulse of one stage is delayed by a time T from a pulse in the preceding stage. Thus a ring counter is analogous to

is delayed by a time T from a pulse in the preceding stage. Thus a ring counter is analogous to Stepping Stepping switch

switch where each triggering pulse causes an advance of switch by where each triggering pulse causes an advance of switch by one step.one step. Patt

Pattern produceern produced by d by Ring counter : Ring counter : 1000, 0100, 0010, 0001, 1000, ....1000, 0100, 0010, 0001, 1000, ....

NOT

NOTE

E ::

Ri

Ring ng cocoununteter r is is ththe e cocoststliliesest t synsynchchroronounouss counter.

counter. With

With n n flip flops flip flops maximum modulus maximum modulus == N N

21 21

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Johnson counter

Johnson counter (Twisted Ring

(Twisted Ring counter)

counter)

Johnson counter is a variation of Ring counter obtained by taking feedback output from

Johnson counter is a variation of Ring counter obtained by taking feedback output from Q Q (instead (instead of Q in Ring counter), to the ﬁrst stage.

of Q in Ring counter), to the ﬁrst stage.

Patt

Pattern in Johnson counter : ern in Johnson counter : 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000, ...

Note :

Johnson counter performs

Johnson counter performs gray counting gray counting Maximum modu

Maximum moduluslus==2n2n

1.2.3

1.2.3 Counters Counters - [- [GATGATE QE Questions] uestions] 1.

1. What is the ﬁnal value storeWhat is the ﬁnal value stored in the d in the linear felinear feedback shifedback shift registet register if the input is r if the input is 101101?101101?

2.

2. The minimum numbThe minimum number of D flip-flops neeer of D flip-flops needed to design a mod-25ded to design a mod-258 counter is8 counter is

[GATE-2011 CS

[GATE-2011 CS & & IT] IT] [1 [1 mark]mark]

3.

3. HoHow w manmany y pulspulses are es are neeneeded to ded to chachange the nge the concontentents of ts of a a 8-b8-bit up it up coucountenter r frofrom m 101010101100 to 1100 to 0010001001110111 (right

(rightmost bit most bit is the is the LSB)?LSB)?

22 22

                           

                   

(23)

4.

4. LeLett k k = = 2 2nn. A circuit is built by giving the output of an n-bit binary counter as input to an bit decoder. This. A circuit is built by giving the output of an n-bit binary counter as input to an bit decoder. This circuit is equivalent to a

circuit is equivalent to a

[GATE-2014 SET-2] [1 mark]

5.

5. For the initiaFor the initial state of 000, the function perfol state of 000, the function performed by the arrangermed by the arrangement of the J-K flip flops in ment of the J-K flip flops in figure is :figure is :

Common Data Questions[6-7] Common Data Questions[6-7]

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

6.

6. If all the flip-flops were reset to 0 at poIf all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) representedwer on, what is the total number of distinct outputs (states) represented by PQR

by PQR generagenerated by ted by the counter?the counter?

23 23                                                                                                                                                                    

(24)

7.

7. If at some If at some instaninstance prior to the ce prior to the occuraoccurance of the nce of the clock edge, Pclock edge, P, Q , Q and R and R have a value 0, 1 have a value 0, 1 and 0 and 0 respecrespectivtivelyely,, what shall be the value of PQR after the clock edge?

what shall be the value of PQR after the clock edge?

[GATE-2011 CS

[GATE-2011 CS & & IT] IT] [2 [2 mark]mark]

8.

8. The control signal funcThe control signal function of a tion of a 4-bit binary counte4-bit binary counter are given belowr are given below( where X is ( where X is "don’"don’t care"):t care"):

The counter is connected as follows: Assume that the counter and gate delays are negligible. If the counter The counter is connected as follows: Assume that the counter and gate delays are negligible. If the counter

starts at 0,

starts at 0, then it then it cyclcycles through es through the followithe following sequence.ng sequence.

9.

9. ConsideConsider the circuit giver the circuit given below with initial state Qn below with initial state Q00 == 1, 1, QQ11 == Q Q22 == 0. The state of the circuit is given by 0. The state of the circuit is given by

the value 4Q

the value 4Q22 + + 2Q2Q11 + + QQ00

Which one of

Which one of the followthe following is ing is correcorrect state sequence of the ct state sequence of the circuicircuit?t?

[GATE-2001 CS] [2 mark] [GATE-2001 CS] [2 mark] 24 24                                                                                                                  

(25)

10.

10. ConsideConsider the r the partipartial implementaal implementation of tion of a 2-bit counter using T a 2-bit counter using T flip-floflip-flops followinps following the g the sequencsequence 0-2-3-1-0,e 0-2-3-1-0, as shown below.

as shown below.

To complete the circuit, the input X should be To complete the circuit, the input X should be

⊕ ⊕ Q Q22

1.2.4

1.2.4 Counters Counters - [- [ISRO ISRO Questions] Questions] 1.

1. Ring counRing counter is anter is analogous talogous too

[ISRO - 2007 CS]

2.

2. In a In a thrthree stage couee stage countenter, usinr, using g RS flip RS flip flopflops s whawhat will be t will be the valthe value of ue of the countthe counter afteer after givinr giving g 9 9 pulspulses toes to input? Assume that the

input? Assume that the valuvalue of e of countecounter before giving any pulses is 1.r before giving any pulses is 1.

[ISRO - 2013 CS] [ISRO - 2013 CS] 25 25     22     22   11      11       11 ⊕ ⊕ Q Q22                                                                    

(26)

1.3

S

e q u e n t i a le q u e n t i a l

C

i r c u i t si r c u i t s

–

– A

A

n s w e r sn s w e r s

1.3.1

Flip-ﬂops

Flip-ﬂops -

- [GA

[GATE]

TE]

1.3.2

Flip-ﬂops

Flip-ﬂops -

- [ISRO]

[ISRO]

1.3.3

Registers

& &

_{Counters - [GATE]}

1.3.4

Registers

& &

_{Counters - [ISRO]}

26 26                                                                                                       

(27)

1.4

A

n s w e r s w i t hn s w e r s w i t h

E

x p l a n a t i o n sx p l a n a t i o n s

1.4.1

Flip-ﬂops

Flip-ﬂops -

- [GA

[GATE]

TE]

1.

1. AnAns:s: (d) indeterminat(d) indeterminate statee state 2.

2. AnAns:s: (a) 11(a) 11, 00, 00

In a cross coupled R-S flip-flop realized using NAND gate, for input 11 the output will be the previous output. In a cross coupled R-S flip-flop realized using NAND gate, for input 11 the output will be the previous output. Input 00

Input 00 leads to oscillatioleads to oscillation.n. 3.

3. AnAns:s: (a) 11, 10(a) 11, 10, 01, 00, 01, 00

Initial values of Q Initial values of Q11QQ00==0000 Q Q₀₀₍₍_prev_prev₎₎ ∵∵ 0 0 Q Q₁₁₍₍_prev_prev₎₎ ∵∵ ₀₀ 1 1(( prev prev)) ∵∵ 00 4.

4. AnAns:s: (a) 1, (a) 1, 00

In the above configuration input of D flip flop is the output P of JK flip flop. Since, 1 is constantly given as In the above configuration input of D flip flop is the output P of JK flip flop. Since, 1 is constantly given as input to JK flip flop, each time the output toggles.

input to JK ﬂip ﬂop, each time the output toggles.

27 27             00                                                                                      11                                     11                         

(28)

5.

5. AnAns:s: (c) 100, 11(c) 100, 110, 1110, 111

Initial values are Q

Initial values are Q22QQ11QQ00 = = 0 0 0 0 00

The state sequence for next 3 clock cycles is given by : The state sequence for next 3 clock cycles is given by :

6.

6. AnAns:s: (c) 010 (c) 010

28 28

(29)

7.

7. AnAns:s: (d) x (d) x⊕⊕ y and x y and x⊕⊕ y y

From the above table: From the above table: J(X,Y,Q) J(X,Y,Q) ==(2,4)(2,4) ++_φ_φ(1,3,5,7)(1,3,5,7) ∴ ∴ JJ== X X YY++XXY Y ==XX⊕⊕YY K(X,Y,Q) K(X,Y,Q) == (3,5)(3,5) ++ _φ_φ(0,2,4,6)(0,2,4,6) ∴ ∴ KK== X X YY++XXY Y ==XX⊕⊕YY 29 29

(30)

8.

8. AnAns:s: (c)(c)

9.

9. AnAns:s: (d) (d)

State transition sequence of Q

State transition sequence of Q00QQ11 is is ::

30 30

(31)

10.

10. AnsAns:: (a) (a)

11.

11. AnsAns:: (a) A (a) A00AA11AA11’A’A33AA44

From the given ﬁgure:

From the given ﬁgure: A AiiXX++Q’.X’Q’.X’

∴

∴ Answer isAnswer is (a) A (a) A₀₀ A A₁₁ A A₁₁’A’A₃₃ A A₄₄

1.4.2

Flip-ﬂops

Flip-ﬂops -

- [ISRO]

[ISRO]

1.

1. AnAns:s: (a) Se(a) Set to 1t to 1 2.

2. AnAns:s: (d) Q (d) Qnn++11==SS++ R RQQnn

31 31

(32)

1.4.3

Counters

Counters -

- [GA

[GATE]

TE]

1.

1. AnAns:s: (a) 0110 (a) 0110

2.

2. AnAns:s: (a) 9 (a) 9

A mod -258 counter counts from 0 to 257. A mod -258 counter counts from 0 to 257.

∴

∴ Number of bits requiredNumber of bits required==  log log

2

2 257 257   ==99

∴

∴ Number of D flip flops requiredNumber of D flip flops required==99

3. 3. AnAns:s: (d) 123 (d) 123 (10101100) (10101100)22 = = (172)(172)1010 (00100111) (00100111)22 = = (39)(39)1010

Since this is an 8 bit counter it counts from 0 to 255. Since this is an 8 bit counter it counts from 0 to 255. Th

The e cocoununteter r cocoununts ts frfrom om 17172 2 to to 25255 5 ((83 pulses83 pulses)) T

Thheen n ffrroom m 0 0 tto o 339 9 ((40 pulses40 pulses))

∴

∴Total number of pulsesTotal number of pulses==4040++8383==123123

4.

4. AnAns:s: (c) k-bit r(c) k-bit ring countering counter 5.

5. AnAns:s: (c) Mod-6 (c) Mod-6 countercounter

The given counter is Johnson counter. The given counter is Johnson counter. Number of ﬂip ﬂops,

Number of flip flops, n n ==33 With n flip flops maximum mod

With n ﬂip ﬂops maximum mod==2n2n==66 6.

6. AnAns:s: (b) 4 (b) 4 From the ﬁgure, From the ﬁgure, P

P Next Next statestate = = R R QQ Ne Ne xtstatextstate = = P P

+

R R RR Ne Ne xtstatextstate = = QQ R R

Given that, all the flip flops were reset to 0 on power on. Given that, all the flip flops were reset to 0 on power on.

∴

∴Number of statesNumber of states ==44..

7.

7. AnAns:s: (d) 011 (d) 011

From the above answer it

From the above answer it is clear that, if is clear that, if currecurrent state isnt state is 010 010 then next state will be then next state will be 011 011 32

(33)

8.

8. AnAns:s: (c) 0(c) 0, 1, 2, 3, 1, 2, 3, 4, 4

Here count starts from 0. Counter counts next until clear

Here count starts from 0. Counter counts next until clear = = 1. From the above conﬁguration, clear 1. From the above conﬁguration, clear = =1 when1 when A

A33 and A and A11 becomes 1. i.e., 0101 (5). becomes 1. i.e., 0101 (5).

∴

∴The given counter is a mod-5 counter The given counter is a mod-5 counter which counts from which counts from 0 to 4 0 to 4.. ∴

∴The sequence is (c) 0, 1, 2, 3, 4The sequence is (c) 0, 1, 2, 3, 4

9.

9. AnAns:s: (b) 1, 2(b) 1, 2, 5, 3, 7, 6, 4, 5, 3, 7, 6, 4

10.

10. AnsAns: (d) : (d) QQ11 ⊕ ⊕ Q Q22

1.4.4

Counters

Counters -

- [ISRO]

[ISRO]

1.

1. AnAns:s: (c) Stepping (c) Stepping SwitchSwitch 2.

2. AnAns:s: (b) 2 (b) 2

Since the given counter is three stage counter, it can count from

Since the given counter is three stage counter, it can count from 0 to 7 0 to 7 ( (∵∵2233 ==88).).

Initially the value is 1. By applying ﬁrst 6 pulse it will count upto

Initially the value is 1. By applying ﬁrst 6 pulse it will count upto 7 7. For the. For the next 3 pulses next 3 pulses it will count: 0, 1 it will count: 0, 1 and

and 2 2..

33 33

(34)

(35)

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35 35