1. Which interrupt has the highest priority?
a) INTR b) TRAP c) RST6.5
2. In 8085 name the 16 bit registers?
a) Stack pointer b) Program counter c) a & b
3. Which of the following is hardware interrupts?
a) RST5.5, RST6.5, RST7.5 b) INTR, TRAP c) a & b
4. What is the RST for the TRAP?
a) RST5.5 b) RST4.5 c) RST4
5. What are level Triggering interrupts?
a) INTR&TRAP b)RST6.5&RST5.5 c)RST7.5&RST6.5
6. Which interrupt is not level sensitive in 8085?
a) RST6.5 is a raising edge-trigging interrupt.
b) RST7.5 is a raising edge-trigging interrupt.
c) a & b.
7. What are software interrupts?
a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP
8. Which stack is used in 8085?
a) FIFO b) LIFO c) FILO
9. Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU.
b) Because 8085 processor has 8 bit data bus.
c) a & b.
10. What is SIM?
a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
11. RIM is used to check whether, ______
a) The write operation is done or not
b) The interrupt is Masked or not
c) a & b
12. What is meant by Maskable interrupts?
a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none
13. In 8086, Example for Non maskable interrupts are
a) Trapb) RST6.5 c) INTR
14. What does microprocessor speed depends on?
a) Clock b) Data bus width c) Address bus width
15. Can ROM be used as stack?
16. Which processor structure is pipelined?
a) all x80 processors b) all x85 processors c) all x86 processors
17. Address line for RST3 is?
a) 0020H b) 0028H c) 0018H
18. In 8086 the overflow flag is set when
a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set
M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/1 Microprocessors and
Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors
d) During subtraction
19. The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
c) Require a bigger address decoder
d) All the above
20. BHE of 8086 microprocessor signal is used to interface the
a) Even bank memory
b) Odd bank memory
c) I/O
d) DMA
21. In 8086 microprocessor the following has the highest priority among all type
interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW
22. In 8086 microprocessor one of the following statements is not true.
a) Coprocessor is interfaced in MAX mode
b) Coprocessor is interfaced in MIN mode
c) I/O can be interfaced in MAX / MIN mode
d) Supports pipelining
23. 8088 microprocessor differs with 8086 microprocessor in
a) Data width on the output
b) Address capability
c) Support of coprocessor
d) Support of MAX / MIN mode
24. Address line for TRAP is?
a) 0023H b) 0024H c) 0033H
M. Krishna Kumar/IISc. Bangalore M1/V1/June 04/2 Microprocessors and
Microcontrollers/ Multiple Choice Questions
Architecture of Microprocessors
Key:
1.1 C 1.2 C 1.3 C 1.4 B 1.5 B 1.6 B
1.7 A 1.8 B 1.9 A 1.10 C 1.11 B 1.12 B
1.13 A 1.14 C 1.15 B 1.16 C 1.17 C 1.18 B
1.19 D 1.20 B 1.21 A 1.22 B 1.23 A 1.24 B
_________________________________________________________________
1. The 8051 microcontroller is of ___pin package as a ______ processor.
a) 30, 1byte b) 20, 1 byte c) 40, 8 bit d) 40, 8 byte
2. The SP is of ___ wide register. And this may be defined anywhere in the ______.
a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM.
c) 16 bit, on-chip 128 byte ROM d) 8 bit, on chip 128 byte RAM.
3. After reset, SP register is initialized to address________.
a) 8H b) 9H c) 7H d) 6H
4. What is the address range of SFR Register bank?
a) 00H-77H b) 40H-80H c) 80H-7FH d) 80H-FFH
5. Which pin of port 3 is has an alternative function as write control signal for
external data memory?
a) P3.8 b) P3.3 c) P3.6 d) P3.1
6. What is the Address (SFR) for TCON, SCON, SBUF, PCON and PSW
respectively?
a) 88H, 98H, 99H, 87H, 0D0H. b) 98H, 99H, 87H, 88H, 0D0H
c) 0D0H, 87H, 88H, 99H, 98H d) 87H, 88H, 0D0H, 98H, 99H
7. Match the following:
1) TCON i) contains status information
2) SBUF ii) timer / counter control register.
3) TMOD iii) idle bit, power down bit
4) PSW iv) serial data buffer for Tx and Rx.
5) PCON v) timer/ counter modes of operation.
a) 1->ii, 2->iv, 3->v, 4->i, 5->iii. b) 1->i, 2->v, 3->iv, 4->iii, 5->ii.
c) 1->v, 2->iii, 3->ii, 4->iv, 5->i. d) 1->iii, 2->ii, 3->i, 4->v, 5->iv.
8. Which of the following is of bit operations?
i) SP
ii) P2
iii) TMOD
iv) SBUF
v) IP
a) ii, v only b) ii, iv, v only c) i, v only d) iii, ii only
9. Serial port interrupt is generated, if ____ bits are set
a) IE b) RI, IE c) IP, TI d) RI, TI
10. In 8051 which interrupt has highest priority?
a)IE1 b)TF0 c)IE0 d)TF1
11. Intel 8096 is of ___ bit microcontroller family called as ______.
a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96
12. 8096 has following features fill up the following,
i) ____ Register file,
ii) ____ I/O Ports
iii) ____ architecture.
a) 256 byte, five 8bit, register to register
b) 256 byte, four 8bit, register to register
c) 232 byte, five 8bit, register to register
d) 232 byte, six 8 bit, register to register
13. How many synchronous and asynchronous modes are there in serial port of 8096?
M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/1 Microprocessors and
Microcontrollers/ Multiple Choice Questions
Architecture of Micro controllers
a) 2, 2 respectively b) 3,1 respectively c) 1, 3 respectively d) 1, 2 respectively
14. In 8096 we have _____interrupt sources and _______ interrupt vectors.
a) 18, 8 b) 21, 6 c) 21, 8 d) 16, 8
15. 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following
i) two quasi-bidirectional I/O lines
ii) two output lines
iii) four input lines
iv) open drain outputs
a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv
16. 8096 write-protected mode, no code can write to memory address between __.
a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH
17. If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM
together with _____ memory and devices.
a) EA, high, internal, external
b) EA, low, internal, external
c) EA, high, external, internal
d) EA, low, external, internal
18. In 8096, CCB bit 3 is ____.
a) write strobe mode select b) address valid strobe select
c) bus width select d) Internal read control mode
19. In 8096, mode ____ of serial port are ___ modes commonly used for ____
communications.
a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller
c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller
20. What is the function of watchdog timer?
a) The watchdog Timer is an external timer that resets the system if the software
fails to operate properly.
b) The watchdog Timer is an internal timer that sets the system if the software fails
to operate properly.
c) The watchdog Timer is an internal timer that resets the system if the software fails
to operate properly.
d) None of them
M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/2 Microprocessors and
Microcontrollers/ Multiple Choice Questions
Architecture of Micro controllers
Key:
5.1 C 5.2 D 5.3 C 5.4 D 5.5 C 5.6 A
5.7 A 5.8 A 5.9 D 5.10 C 5.11 D 5.12 C
5.13 C 5.14 C 5.15 C 5.16 C 5.17 A 5.18 B
5.19 C 5.20 C
________________________
1. The contents of different registers are given below. Form Effective addresses for
different addressing modes are as follow :
Offset = 5000H
[AX]- 1000H, [BX]- 2000H, [SI]- 3000H, [DI]- 4000H, [BP]- 5000H,
[SP]- 6000H, [CS]- 0000H, [DS]- 1000H, [SS]- 2000H, [IP]- 7000H.
I. MOV AX, [5000H]
a) 5000Hb) 15000H
c) 10500H
II. MOV AX, [BX] [SI]
a) 13000H
b) 15000H
c) 12000H
III. MOV AX, 5000H [BX] [SI]
a) 20000H
b) 1A000H c) 1A00H
2. The conditional branch instruction JNS performs the operations when if __
a) ZF =0 b) SF=0
c) PF=0
d) CF=0
3. Vector address of TRAP
a) 24H
b) 36H
c) 24 d) 18H
4. SOD pin can drive a D flip-flop?
a) SOD cannot drive any flip-flops.
b) SOD cannot drive D flip-flop, but can drive any other flop-flops.
c) Yes, SOD can drive D flop-flop.
d) No, SOD cannot drive any other flop-flops except D flop-flop.
5. IDIV and DIV instructions perform the same operations for?
a) Unsigned number b) Signed number c) Signed number & Unsigned number d)
none of above.
6. What is the output of the following code
AL=88 BCD,
CL=49 BCD
ADD
AL, CL
DAA
a) D7, CF=1
b) 37, CF=1 c) 73, CF=1 d) 7D, CF=1
7. What is the output of the following code
AL= 49 BCD, BH= 72 BCD
SUB
AL, BH
DAS
a) AL=D7, CF=1. b) AL=7D, CF=1.
c) AL=77, CF=1 d) none of them.
8. What is the output of the following code
AL= -28 decimal, BL=59 decimal
IMUL
BL
AX=? , MSB=?
a) AX= F98CH, MSB=1. b) AX= 1652, MSB=1. c) BX F9C8H, MSB=1.
d)
BX= 1652, MSB=1.
9. What is the output of the following code
AL= 00110100 BL= 00111000
AAA
a) AL = 6CH
b) 12H c) 12 d) C6H
10. What is the output of the following code
AL=00110101
BL= 39H
M. Krishna Kumar/IISc. Bangalore
M2/V1/June 04/1
Microprocessors and Microcontrollers/Assembly language of 8086
Multiple Choice Questions
SUB
AL, BL
AAS
a) AL= 00000100, CF=1 b) BL=00000100, CF=0 c) AL=11111100 CF=1
d) BL=
00000100, CF=1
11. What is the output of the following code
CF =0,
BH = 179
RCL
BH, 1
a) CF=0, OF= 1, BH= 01100101 b) CF=1, OF=1, BH=01100110
c) CF=1, OF =0, BH= 01001101 d) CF=0, OF=0, BH=00101100
12. What is the output of the following code
SI=10010011 10101101, CF=0
SHR
SI, 1
a) 37805, CF=1, OF=1 b) 18902, CF=1, OF=1
c) 19820, CF=1, OF=1 c) 53708, CF=1, OF=1
13. What is the output of the following code
BX=23763 CL=8
ROL
BX, CL
a) 0101110011010011, CF=0
b) 1101001101011100, CF=0
c) 0110100010011101, CF=1
c) 1011100110001100, CF=1
14. What is the output of the following code
PUSH AL
b) Increment SP by 2 & push a word to stack
c) Decrement SP by 2 & push a AL to stack
d) Illegal
15. What is the output of the following code
AX = 37D7H,
BH = 151 decimal
DIV
BH
a) AL = 65H, AH= 94 decimal
b) AL= 5EH, AH= 101 decimal
c) AH= E5H, AL= 5EH
d) AL= 56H, AH= 5EH
16. In 8086 microprocessor one of the following instructions is executed before an
arithmetic operation
a) AAM b) AAD
c) DAS
d) DAA
M. Krishna Kumar/IISc. Bangalore
M2/V1/June 04/2
Microprocessors and Microcontrollers/Assembly language of 8086
Key:
2.1 (I) B (II) C (III) B
2.6 B
2.7 C
2.12 B
2.13 B
M. Krishna Kumar/IISc. Bangalore
2.2 B
2.8 A
2.14 D
2.3 A
2.9 C
2.15 B
Multiple Choice Questions
2.4 C
2.10 A
2.16 B
2.5 B
2.11 B
_________________________________________
1. Access time is faster for
a) ROM
b) SRAM
c) DRAM
2. In 8279 Strobed input mode, the control line goes low. The data on return lines is
strobed in the ____.
a) FIFO byte by byte
b) FILO byte by byte
c) LIFO byte by byte
d) LILO byte by byte.
3. ___ bit in ICW1 indicates whether the 8259A is cascade mode or not?
a) LTIM=0 b) LTIM=1 c) SNGL=0 d) SNGL=1
4. In 8255, under the I/O mode of operation we have __ modes. Under which mode
will have the following features
i) A 5 bit control port is available.
ii) Three I/O lines are available at Port C.
a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2
5. In ADC 0808 if _______ pin high enables output.
a) EOC
b) I/P0-I/P7 c) SOC
d) OE
6. In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line
goes ____ to interrupt the CPU.
a) CS, high b) A0, high
c) IRQ, high d) STB, high
7. In 8279 Status Word, data is read when ________ pins are low, and write to the
display RAM with ____________ are low.
a) A0, CS, RD & A0, WR, CS.
b) CS, WR, A0 & A0, CS, RD
c) A0, RD & WR, CS
d) CS, RD & A0, CS.
8. In 8279, the keyboard entries are debounced and stored in an _________, that is
further accessed by the CPU to read the key codes.
a) 8-bit FIFO b) 8-byte FIFO
c) 16 byte FIFO
d) 16 bit FIFO
9. The 8279 normally provides a maximum of _____ seven segment display
interface with CPU.
10. For the most Static RAM the write pulse width should be at least
a) 10ns
b) 60ns
c) 300ns
d) 1μs
11. BURST refresh in DRAM is also called as
a) Concentrated refresh b) distributed refresh
c) Hidden refresh d) none
12. For the most Static RAM the maximum access time is about
a) 1ns b) 10ns
c) 100ns
d) 1μs
13. Which of the following statements on DRAM are correct?
i) Page mode read operation is faster than RAS read.
ii) RAS input remains active during column address strobe.
iii) The row and column addresses are strobed into the internal buffers using RAS
and CAS inputs respectively.
a) i & iii
b) i & ii
c) all d) iii
14. 8086 microprocessor is interfaced to 8253 a programmable interval timer. The
maximum number by which the clock frequency on one of the timers is divided
by
a) 216 b) 28 c) 210 d) 220
M. Krishna Kumar/IISc. Bangalore
M3/V1/June 04/1
Microprocessors and Microcontrollers/Interfacing with 8086
Multiple Choice Questions
15. 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s
are in master slave configuration the number of interrupts available to the 8086
microprocessor is
a) 8 b) 16 c) 15 d) 64
M. Krishna Kumar/IISc. Bangalore
M3/V1/June 04/2
Microprocessors and Microcontrollers/Interfacing with 8086
Key:
3.1 B
3.7 A
3.12 C
3.2 A
3.8 B
3.13 C
3.3 C
3.9 B
3.14 A
M. Krishna Kumar/IISc. Bangalore
3.4 B
3.10 B
3.15 D
Multiple Choice Questions
3.5 D
3.11 A
3.6 C
___________________________________________________________
1. The coprocessors operate in ______ with a processor on the same buses and with
the same instruction _______.
a) Parallel, byte stream.
b) Series, byte stream.
c) Series, bite stream d) Parallel, bite stream.
2. Why 8087 is referred to as Coprocessor?
i) Because 8087 is used in parallel with main processor in a system, rather than
serving as a main processor itself.
ii) Because 8087 is used in serial with main processor in a system, rather than
serving as a main processor itself.
iii) Because main Microprocessor handles the general program execution and the
8087 handles specialized math computations.
a) i & iii
b) ii & iii
c) iii only.
d) i only.
3. 8087 connection to 8086, to enable the _________ bank of memory _______pins
are to be connected.
a) Lower, BHE
b) Upper, BHE
c) Lower, INT
d) Upper, INT.
4. ___ Connection and the _______ instruction will solve the problem of
synchronization between processor and coprocessor.
a) INT & NMI, WAIT
b) RQ/GT0 & RQ/GT1, FWAIT
c) BUSY & TEST, FWAIT d) S0 & QS0, WAIT
5. _______ input is available, so that another coprocessor can be connected and
function in _________ with the 8087.
.
a) RQ/GT0, parallel b) RQ/GT1, parallel c) QS1 & QS0, parallel
d) S0 & S1, parallel.
6. In 8087, _______ many register stack are there? And of _____ registers. These
registers are used as _________ stack.
a) 7, 40 bit, FIFO. b) 8, 60 bit, LILO. c) 8, 80 bit, LIFO d) 7, 80 bit, FILO.
7. If ______ and ________ connections are made so that an error condition in 8087
can interrupt to the processor.
a) BHE, RQ/GT1
b) BUSY, TEST
c) INT, NMI d) RQ/GT0, RQ/GT1
8. In 8087, which instruction is used for division real reversed______.
a) FDIV
b) FIDIVR
c) FDIVR
d) FDIVRP
9. Which of the following is of compare instruction in 8087?
a) FTST
b) FPREM
c) FPATAN d) FLDI
10. In 8087 coprocessor one of the following instructions is not valid
a. FSIN
b. FPTAN
c. FIDIV
d. FSQRT
11. One of the following signals belongs to the 8087 coprocessor is
a. HOLD
b. BUSY
c. TEST
d. NMI
M. Krishna Kumar/IISc. Bangalore
M4/V1/June 04/1
Microprocessors and Microcontrollers/Coprocessor
Key:
4.7 C
Multiple Choice Questions
4.2 A 4.3 B 4.4 A 4.5 B 4.6 C
4.8 C 4.9 A 4.10 A 4.11 C
______________________________________________________
1. The 8051 microcontroller is of ___pin package as a ______ processor.
a) 30, 1byte b) 20, 1 byte c) 40, 8 bit
d) 40, 8 byte
2. The SP is of ___ wide register. And this may be defined anywhere in the ______.
a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM.
c) 16 bit, on-chip 128 byte ROM
d) 8 bit, on chip 128 byte RAM.
3. After reset, SP register is initialized to address________.
a) 8H b) 9H c) 7H d) 6H
4. What is the address range of SFR Register bank?
a) 00H-77H b) 40H-80H c) 80H-7FH d) 80H-FFH
5. Which pin of port 3 is has an alternative function as write control signal for
external data memory?
a) P3.8 b) P3.3 c) P3.6 d) P3.1
6. What is the Address (SFR) for TCON, SCON, SBUF, PCON and PSW
respectively?
a) 88H, 98H, 99H, 87H, 0D0H.
b) 98H, 99H, 87H, 88H, 0D0H
c) 0D0H, 87H, 88H, 99H, 98H
d) 87H, 88H, 0D0H, 98H, 99H
7. Match the following:
1) TCON
i) contains status information
2) SBUF
ii) timer / counter control register.
3) TMOD
iii) idle bit, power down bit
4) PSW
iv) serial data buffer for Tx and Rx.
5) PCON
v) timer/ counter modes of operation.
a) 1->ii, 2->iv, 3->v, 4->i, 5->iii.
b) 1->i, 2->v, 3->iv, 4->iii, 5->ii.
c) 1->v, 2->iii, 3->ii, 4->iv, 5->i.
d) 1->iii, 2->ii, 3->i, 4->v, 5->iv.
8. Which of the following is of bit operations?
i) SP
ii) P2
iii) TMOD
iv) SBUF
v) IP
a) ii, v only b) ii, iv, v only c) i, v only
d) iii, ii only
9. Serial port interrupt is generated, if ____ bits are set
a) IE b) RI, IE
c) IP, TI
d) RI, TI
10. In 8051 which interrupt has highest priority?
a)IE1 b)TF0 c)IE0 d)TF1
11. Intel 8096 is of ___ bit microcontroller family called as ______.
a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96
12. 8096 has following features fill up the following,
i) ____ Register file,
ii) ____ I/O Ports
iii) ____ architecture.
a) 256 byte, five 8bit, register to register
b) 256 byte, four 8bit, register to register
c) 232 byte, five 8bit, register to register
d) 232 byte, six 8 bit, register to register
13. How many synchronous and asynchronous modes are there in serial port of 8096?
M. Krishna Kumar/IISc. Bangalore
M5/V1/June 04/1
Microprocessors and Microcontrollers/
Architecture of Micro controllers
Multiple Choice Questions
a) 2, 2 respectively b) 3,1 respectively c) 1, 3 respectively d) 1, 2 respectively
14. In 8096 we have _____interrupt sources and _______ interrupt vectors.
a) 18, 8
b) 21, 6
c) 21, 8
d) 16, 8
15. 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following
i) two quasi-bidirectional I/O lines
iii) four input lines
iv) open drain outputs
a) 4, i, iv
b) 6, ii, iii
c) 4, i,ii,iii
d) 6, i, ii, iv
16. 8096 write-protected mode, no code can write to memory address between __.
a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH
17. If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM
together with _____ memory and devices.
a) EA, high, internal, external
b) EA, low, internal, external
c) EA, high, external, internal
d) EA, low, external, internal
18. In 8096, CCB bit 3 is ____.
a) write strobe mode select b) address valid strobe select
c) bus width select
d) Internal read control mode
19. In 8096, mode ____ of serial port are ___ modes commonly used for ____
communications.
a) 1, 8bit, single processor
b) 0, 7bit, multiple microcontroller
c) 2, 9 bit, multiple processors
d) 3, 8 bit, multiple microcontroller
20. What is the function of watchdog timer?
a) The watchdog Timer is an external timer that resets the system if the software
fails to operate properly.
b) The watchdog Timer is an internal timer that sets the system if the software fails
to operate properly.
c) The watchdog Timer is an internal timer that resets the system if the software fails
to operate properly.
d) None of them
M. Krishna Kumar/IISc. Bangalore
M5/V1/June 04/2
Microprocessors and Microcontrollers/
Architecture of Micro controllers
Key:
5.1 C
5.7 A
5.13 C
5.19 C
Multiple Choice Questions
5.2 D 5.3 C 5.4 D 5.5 C 5.6 A
5.8 A 5.9 D 5.10 C 5.11 D 5.12 C
5.14 C 5.15 C 5.16 C 5.17 A 5.18 B
5.20 C
___________________________________________
‘
1. Which of the following instruction perform as of indirect RAM to accumulator?
a) MOV A, Rn
b) MOV @Ri, A
c) MOV A, @Ri d) MOV Rn, A
2. ACALL instruction allows specifying ______address in the instruction and
calling subroutine within ______ program memory block.
a) 2byte, 3K
b) 11bit, 2K c) 9bit, 2K
d) 1byte, 3K
3. Which of the following instruction perform the move accumulator to external
RAM of 16bit address?
a) MOV @ DPTR, A
b) MOVX @ Ri, A
c) MOV A, @ Ri d) MOVX @ DPTR, A
4. Which of the following instruction perform jump indirect relative to DPTR
a) JMP A+DPTR b) JMP DPTR
c) JMP @A+DPTR
d) SJMP A+DPTR
5. Which of the following instruction is wrong
a) INC DPTR
b) MOV @DPTR, A
c) MOV A, @A+DPTR d) DEC DPTR
6. Which of the following instruction is of logical instructions?
i) CPL A
ii) JC rel
iii) DA A
iv) ANL A, Rn
v) RR A
vi) CPL bit
a) i, v
b) v, iii, I
c) iv, ii d) v, iii, ii
7. What instruction performs Compare immediate to indirect and jump if not equal.
a) CJNE A, #data, rel
b) CJNE Rn, #data, rel
c) CJNE @ Ri, #data, rel d) CJNE A, data, rel
8. What is the Result of RR A instruction if accumulator contains 1000 0000.
a) 0000 0001
b) 0000 0000 c) 0100 0000 d) 0000 0010
9. MOV 45, #4FH
MOV R0, 45H
INC R0
MOV @R0, #30H
What is the location value of R0 and the content at that place?
a) 45H, 4F b) 50H, 30H c) 30H, 50H d) 50H, 45H
10. Which of the following is of type memory initialized Directive?
i) DS
ii) SET iii) DW
iv) DBIT
a) i, iii
b) ii c) iii d) iv, ii
11. Which of the following is not a program linking directive
i) EXTRN ii) SEGMENT iii) NAME
iv) PUBLIC v) USING
a) iv, v
b) ii, iii c) i, iii d) ii, v
12. SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset.
a) 2 byte, 08H
b) 8 bit, 07H c) 1 byte, 09H d) 8 bit, 06H
13. Which of the following instruction is used to set bit port directly?
a) SET P1.0
b) MOV P1.0, bit
c) SETB P1.0 d) JB P1.0, bit
14. MOV A, #56H
MOV R1, #50H
M. Krishna Kumar/IISc. Bangalore
M6/V1/June 04/1
Microprocessors and Microcontrollers/Assembly language of 8051
MOV 50H, # 45H
XCHD A, @R1
a) 56H, 45H
b) 45H, 50H c) 50H, 56H
M. Krishna Kumar/IISc. Bangalore
Multiple Choice Questions
d) 45H, 56H
M6/V1/June 04/2
Microprocessors and Microcontrollers/Assembly language of 8051
Key:
6.1 C
6.7 C
6.13 C
Multiple Choice Questions
6.2 B 6.3 D 6.4 C 6.5 B 6.6 A
6.8 C 6.9 B 6.10 C 6.11 D 6.12 B
6.14 D
_________________________________________________________________
Microprocessors and Microcontrollers/Interfacing with 8051
Multiple Choice Questions
1. In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt
if ____.
a) 000BH, a high to low transition on pin INT1
b) 001BH, a low to high transition on pin INT1
c) 0013H, a high to low transition on pin INT1
d) 0023H, a low to high transition on pin INT1
2. Serial port vector address is of _______. And causes an interrupt when ________.
a) 0013H, either TI or RI flag is set
b) 0023H, either TI or RI flag is reset
c) 0013H, either TI or RI flag is reset
d) 0023H, either TI or RI flag is set
3. In serial communication modes, mode 1 the Baud rate =
a) BR=2SMOD/32 * (Timer 0 over flow rate)
b) BR=2SMOD/16 * (Timer 1 over flow rate)
c) BR=2SMOD/16 * (Timer 0 over flow rate)
d) BR=2SMOD/32 * (Timer 1 over flow rate)
4. In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor
communication and is of ____ bit address.
a) SM1, 9EH b) TB8 , 9CH c) SM2 , 9DH d) SM0, 9FH
a) 6, RS, RW b) 5, RW, EN c) 8, RS, EN, RW
d) 9, RS, EN, RW
6. Resolution of ADC is defined as
a) 1/ (2N – 1) b) 2N-1 c) 1/ (2N-1) d) 2N-1
7. In microcontroller and LCD interface which line will instruct the LCD that
microcontroller is sending data?
a) DB0 b) RW c) EN d) RS
8. Which bit of TMOD will exactly configure timer / counter as a timer or counter.
i) TMOD.6 of C/T for timer 1
ii) TMOD.6 of C/T for timer 0
iii) TMOD.2 of C/T for timer 0
iv) TMOD.2 of C/T for timer 1
a) i, ii b) ii, iv c) i, iii d) iii, iv
M. Krishna Kumar/IISc. Bangalore
M7/V1/June 04/1
Microprocessors and Microcontrollers/Interfacing with 8051
Multiple Choice Questions
Key:
7.1 C 7.2 D 7.3 D 7.4 C 7.5 C 7.6 C 7.7 C 7.8 C
________________________________________________________________
1. Segmentation unit allows segments of _____ size at maximum.
a) 4Gbytes
b) 6Mbytes c) 4Mbytes d) 6Gbytes
2. If ______input pin of 80386 if activated, allows address pipelining during 80386
bus cycles.
a) BS16
b) NA c) PEREQ
d) ADS
3. Virtual Mode Flag bit can be set using ____ instruction or any task switch
operation only in the _____ mode
a) IRET, Virtual b) POPF, Real c) IRET, protected d) POPF, protected
4. The interrupt vector table of 80386 has been allocated ______ space starting from
_______ to _______.
a) 1Kbyte, 00000H, 003FFH
b) 2Kbyte, 10000H, 004FFH
c) 3Kbyte, 01000H, 007FFH
d) 4Kbyte, 01000H, 009FFH
5. The ___ bit decides whether it is a system descriptor or code/data segment
descriptor
a) P
b) S c) D d) G
6. A new signal group on the 80486 is the ______.
a) PARITY
b) DP0-DP3 c) PCHK
d) all
7. _____is used to control the cache with two new control bits not present in the
80386 microprocessor. What are the bits used to control the 8K byte cache?
a) CR0, CD, NW b) CR0, NW, PWT
c) Control Register Zero, PWT, PCD
d) none
8. To prevent another master from taking over the bus during a critical operation, the
486 can assert its _____signal.
a) LOCK# or PLOCK# b) HOLD or BOFF c) HLDA
d) HOLD
9. 80386 support which type of descriptor table from the following?
a) TDS
b) ADS
c) GDS
d) MDS
10. 80386 support overall ___ addressing modes to facilitate efficient execution of
higher level language programs.
a) 9
b) 10 c) 11 d) 12
M. Krishna Kumar/IISc. Bangalore
M8/V1/June 04/1
Microprocessors and Microcontrollers/High end processors
Key:
8.1 A
8.7 A
Multiple Choice Questions
8.2 B 8.3 C 8.4 A 8.5 B 8.6 D
8.8 A 8.9 C 8.10 C
_______________________________________________________
1) Who is the brain of computer:
a. ALU
b. CPU
c. MU
d. None of these
2) Which technology using the microprocessor is fabricated on a single chip:
a. POS
b. MOS
c. ALU
d. ABM
3) MOS stands for:
a. Metal oxide semiconductor
b. Memory oxide semiconductor
c. Metal oxide select
d. None of these
4) In which form CPU provide output:
a. Computer signals
b. Digital signals
c. Metal signals
d. None of these
5) How many types of microprocessor comprises:
a. 3
b. 6
c. 9
d. 4
6) Which is the microprocessor comprises:
a. Register section
b. One or more ALU
c. Control unit
d. All of these
7) The register section is related to______ of the computer:
a. Processing
b. ALU
c. Main memory
d. None of these
8) What is the store by register:
a. data
b. operands
c. memory
d. None of these
9) How many types of classification of processor based on register section:
a. 1
b. 2
c. 3
d. 4
10) In Microprocessor one of the operands holds a special register called:
a. Calculator
b. Dedicated
c. Accumulator
d. None of these
11) Accumulator based microprocessor example are:
a. Intel 8085
b. Motorola 6809
c. A and B
d. None of these
12) A set of register which contain are:
a. data
c. result
d. all of these
13) How many types are primarily register:
a. 1
b. 2
c. 3
d. 4
14) There are primarily two types of register:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
15) Which register is a temporary storage location:
a. general purpose register
b. dedicated register
c. A and B
d. none of these
16) How many parts of dedicated register:
a. 2
b. 4
c. 5
d. 6
17) Name of typical dedicated register is:
a. PC
b. IR
c. SP
d. All of these
18) PC stands for:
a. Program counter
b. Points counter
c. Paragraph counter
d. Paint counter
19) IR stands for:
a. Intel register
b. In counter register
c. Index register
d. Instruction register
20) SP stands for:
a. Status pointer
b. Stack pointer
c. a and b
d. None of these
21) The act of acquiring an instruction is referred as the____ the instruction:
a. Fetching
b. Fetch cycle
c. Both a and b
d. None of these
22) How many bit of instruction on our simple computer consist of one____:
a. 2-bit
b. 6-bit
c. 12-bit
d. None of these
23) How many parts of single address computer instruction :
a. 1
b. 2
c. 3
d. 4
24) Single address computer instruction has two parts:
a. The operation code
b. The operand
c. A and B
d. None of these
25) LA stands for:
a. Load accumulator
b. Least accumulator
c. Last accumulator
d. None of these
26) ED stands for:
a. Enable MRD
b. Enable MDR
c. Both a and b
d. None of these
27) LM stands for:
a. Least MAR
b. Load MAR
c. Least MRA
d. Load MRA
28) Causing a flag to became 0 is called:
a. Clearing a flag
b. Case a flag
c. Both a and b
d. None of these
29) Which are the flags of status register:
a. Over flow flag
b. Carry flag
c. Half carry flag
d. Zero flag
e. Interrupt flag
f. Negative flag
g. All of these
30) The carry is operand by:
a. C
31) The sign is operand by:
a. S
32) The zero is operand by:
a. Z
33) The overflow is operand by:
a. O
34) _____ is the condition:
a. CD
b. IR
c. Both a and b
d. None of these
35) ____ causes the address of the next microprocessor to be obtained from the
memory:
a. CRJA
b. ROM
c. MAP
d. HLT
36) _________ Stores the instruction currently being executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
37) In which register instruction is decoded prepared and ultimately executed:
a. Instruction register
b. Current register
c. Both a and b
d. None of these
38) The status register is also called the____:
a. Condition code register
b. Flag register
c. A and B
d. None of these
39) BCD stands for:
a. Binary coded decimal
b. Binary coded decoded
c. Both a & b
d. none of these
40) Which is used to store critical pieces of data during subroutines and interrupts:
a. Stack
b. Queue
c. Accumulator
d. Data register
41) The area of memory with addresses near zero are called:
a. High memory
b. Mid memory
c. Memory
d. Low memory
42) The point where control returns after a subprogram is completed is known as the :
a. Return address
b. Main Address
c. Program Address
d. Current Address
43) The subprogram finish the return instruction recovers the return address from the:
a. Queue
b. Stack
c. Program counter
d. Pointer
44) The processor uses the stack to keep track of where the items are stored on it this
by using the:
a. Stack pointer register
b. Queue pointer register
c. Both a & b
d. None of these
45) Which point to the ___ of the stack:
a. TOP
b. START
c. MID
d. None of these
46) Stack words on:
a. LILO
b. LIFO
c. FIFO
d. None of these
47) Which is the basic stack operation:
a. PUSH
b. POP
c. BOTH A and B
d. None of these
48) SP stand for:
a. Stack pointer
b. Stack pop
c. Stack push
d. None of these
49) How many bit stored by status register:
a. 1 bit
b. 4 bit
c. 6 bit
d. 8 bit
50) Which is the important part of a combinational logic block:
a. Index register
b. Barrel shifter
c. Both a & b
d. None of these
51) The structure of the stack is _______ type structure:
a. First in last out
b. Last in last out
c. Both a & b
d. None of these
52) The data in the stack is called:
a. Pushing data
b. Pushed
c. Pulling
d. None of these
53) The CU is designed by using which techniques:
a. HARDWIRED CONTROLS
b. MICROPROGRAMING
c. NANOPROGRAMING
d. ALL OF THESE
54) The 16 bit register is separated into groups of 4 bit where each groups is called:
a. BCD
b. Nibble
c. Half byte
d. None of these
55) A nibble can be represented in the from of:
a. Octal digit
b. Decimal
c. Hexadecimal
d. None of these
56) The left side of any binary number is called:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
57) MSD stands for:
a. Least significant digit
b. Most significant digit
c. Medium significant digit
d. low significant digit
58) _____ a subsystem that transfer data between computer components inside a
computer or between computer:
a. Chip
b. Register
c. Processor
d. Bus
a. Processor
b. Multiplexer
c. Backbone bus
d. None of these
60) The external system bus architecture is created using from ______ architecture:
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
61) The network of wires or electronic path ways on mother board back side:
a. PCB
b. BUS
c. BOTH A and B
d. None of these
62) Which Bus connects CPU & level 2 cache:
a. Rear side bus
b. Front side bus
c. Memory side bus
d. None of these
63) Which bus carry addresses:
a. System bus
b. Address bus
c. Control bus
d. Data bus
64) A 16 bit address bus can generate___ addresses:
a. 32767
b. 25652
c. 65536
d. none of these
65) The processor 80386/80486 and the Pentium processor uses _____ bits address
bus:
a. 16
b. 32
c. 36
d. 64
66) CPU can read & write data by using :
a. Control bus
b. Data bus
c. Address bus
d. None of these
67) Which bus transfer singles from the CPU to external device and others that carry
singles from external device to the CPU:
a. Control bus
b. Data bus
c. Address bus
d. None of these
68) Which is not the control bus signal:
a. READ
b. WRITE
c. RESET
d. None of these
69) When memory read or I/O read are active data is to the processor :
a. Input
b. Output
c. Processor
d. None of these
70) When memory write or I/O read are active data is from the processor:
a. Input
b. Output
c. Processor
d. None of these
71) Using 12 binary digits how many unique house addresses would be possible:
a. 28=256
b. 212=4096
c. 216=65536
d. None of these
72) PROM stands for:
a. Programmable read-only memory
73) EPROM stands for:
a. Erasable Programmable read-only memory
74) Each memory location has:
a. Address
b. Contents
c. Both A and B
d. None of these
75) Which is the type of microcomputer memory:
a. Processor memory
b. Primary memory
c. Secondary memory
d. All of these
76) Secondary memory can store____:
a. Program store code
b. Compiler
c. Operating system
d. All of these
77) Secondary memory is also called____:
a. Auxiliary
b. Backup store
c. Both A and B
d. None of these
78) Customized ROMS are called:
a. Mask ROM
b. Flash ROM
c. EPROM
d. None of these
79) The ram which is created using bipolar transistors is called:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. DDR RAM
80) Which type of RAM needs regular referred:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
81) Which RAM is created using MOS transistors:
a. Dynamic RAM
b. Static RAM
c. Permanent RAM
d. SD RAM
82) Which latch is mostly used creating memory register:
a. SR-Latch
b. JK-Latch
c. D-Latch
d. T-Latch
83) Which statement is false about WR signal:
a. WR signal controls the input buffer
b. The bar over WR means that this is an active low signal
c. The bar over WR means that this is an active high signal
d. If WR is 0 then the input data reaches the latch input
84) Which technique is used for main memory array design:
a. Linear decoding
b. Fully decoding
c. Both A and B
d. None of these
85) CS stands for:
a. Cable select
b. Chip select
c. Control select
d. Cable system
86) WE stands for:
a. Write enable
b. Wrote enable
c. Write envy
d. None of these
87) When CS _____ the chip is not selected at all hence D7 to D0 are driven to high
impedance state:
a. High
b. Low
c. Medium
d. Stand by
88) The capacity of this chip is 1KB they are organized in the form of 1024 words with 8
bit word The what is the site of address bus:
a. 8 bit
b. 10 bit
c. 12 bit
d. 16 bit
89) Which storage technique dose not decoding circuit:
a. Linear decoding
b. Fully decoding
c. Partially
d. None of these
90) In linear decoding address bus of 16-bit wide can connect only ____ of RAM.
a. 16 KB
b. 6KB
c. 12KB
d. 64KB
91) Which statement is wrong according to linear decoding :
a. Address map is not contiguous.
c. If all unused address lines are not used as chip selectors then these
unused lines become don’t cares
d. None of these
92) The problem of bus confect and sparse address distribution are eliminated by the
use of ______ address technique:
a. Fully decoding
b. Half decoding
c. Both a & b
d. None of these
93) A microprocessor retries instructions from :
a. Control memory
b. Cache memory
c. Main memory
d. Virtual memory
94) Which register is used to communicate with memory:
a. MAR
b. MDR
c. Both A and B
d. None of these
95) SAM stands for:
a. Simple architecture machine
b. Solved architecture machine
c. Both a & b
d. None of these
96) MAR stands for:
a. Memory address register
b. Memory address recode
c. Micro address register
d. None of these
97) MDR stands for:
a. Memory data register
b. Memory data recode
c. Micro data register
d. None of these
98) VAM stands for:
a. Valid memory address
b. Virtual memory address
c. Variable memory address
d. None of these
a. VAM
b. SAM
c. MOC
d. None of these
100) Which bus plays a crucial role in I/O:
a. System bus
b. Control bus
c. Address bus
d. Both A and B
101) Which register is connected to the memory by way of the address bus:
a. MAR
b. MDR
c. SAM
d. None of these
102) How many bit of MAR register:
a. 8-bit
b. 16-bit
c. 32-bit
d. 64-bit
103) MOC stands for:
a. Memory operation complex
b. Micro operation complex
c. Memory operation complete
d. None of these
104) Which are the READ operation can in simple steps:
a. Address
b. Data
c. Control
d. All of these
105) The upper red arrow show that CPU sends out the control signals____ and
_____ indicate the data is read from the memory:
a. Memory request
b. Read
c. Both A and B
d. None of these
106) The information is transferred from the_____ and ____ specified register:
a. MDR
b. CPU
c. Both A and B
d. None of these
107) The information on the data bus is transferred to the ______register:
a. MOC
b. MDR
c. VAM
d. CPU
108) The lower red curvy arrow show that CPU places the address extracted from
the memory location on the_____:
a. Address bus
b. System bus
c. Control bus
d. Data bus
109) DMA stands for:
a. Direct memory access
b. Direct memory allocation
c. Data memory access
d. Data memory allocation
110) DMA stands for:
a. Dynamic memory access
b. Data memory access
c. Direct memory access
d. Both B and C
111) CRT stands for:
a. Cathode ray tube
b. Compared ray tube
c. Command ray tube
d. None of these
112) The CPU sends out a ____ signal to indicate that valid data is available on
the data bus:
a. Read
b. Write
c. Both A and B
d. None of these
113) The ____ place the data from a register onto the data bus:
a. CPU
b. ALU
c. Both A and B
d. None of these
114) The CPU removes the ___ signal to complete the memory write operation:
a. Read
c. Both A and B
d. None of these
115) The value memvar must be transferred to the ___:
a. Computer
b. CPU
c. Both A and B
d. None of these
116) The microcomputer system by using the ____device interface:
a. Input
b. Output
c. Both A and B
d. None of these
117) How bit microprocessor inexpensive a separate interface is provided with I/O
device:
a. 2 bit
b. 4 bit
c. 8 bit
d. 32 bit
118) How many ways of transferring data between the microprocessor and a
physical I/O device:
a. 2
b. 3
c. 4
d. 5
119) The standard I/O is also called:
a. Isolated I/O
b. Parallel I/O
c. both a and b
d. none of these
120) standard I/O uses which control pin on the micro processor:
a. IO/M
121) A___ on this pin indicates a memory operation:
a. Low
b. High
c. Medium
d. None of these
122) The external device is connected to a pin called the ______ pin on the
processor chip.
a. Interrupt
b. Transfer
c. Both
d. None of these
123) The DMA controllers are special hardware embedded into the chip in modern
integrate processor that ____and_____ to the system;
a. Data transfer
b. arbitrate access
c. Both A and B
d. None of these
124) The CPU completes yields control of the bus to the DMA controller via:
a. DMA acknowledge signal
b. DMA integrated signal
c. DMA implicitly signal
d. None of these
125) The mode of DMA are:
a. Single transfer
b. Block transfer
c. Burst –block transfer
d. Repeated single transfer
e. Repeated–block transfer
f. Repeated Burst –block transfer
g. All of these
__________________________________________________________
Set - 1
1. UNIVAC is
a. Universal Automatic Computer
b. Universal Array Computer
c. Unique Automatic Computer
d. Unvalued Automatic Computer
2. CD-ROM stands for
a. Compactable Read Only Memory
b. Compact Data Read Only Memory
c. Compactable Disk Read Only Memory
d. Compact Disk Read Only Memory
3. ALU is
a. Arithmetic Logic Unit
b. Array Logic Unit
c. Application Logic Unit
d. None of above
4. VGA is
a. Video Graphics Array
b. Visual Graphics Array
c. Volatile Graphics Array
d. Video Graphics Adapter
5. IBM 1401 is
a. First Generation Computer
b. Second Generation Computer
c. Third Generation Computer
d. Fourth Generation Computer
6. MSI stands for
a. Medium Scale Integrated Circuits
b. Medium System Integrated Circuits
c. Medium Scale Intelligent Circuit
d. Medium System Intelligent Circuit
7. The capacity of 3.5 inch floppy disk is
a. 1.40 MB
b. 1.44 GB
c. 1.40 GB
d. 1.44 MB
8. The first computer introduced in Nepal was
a. IBM 1400
b. IBM 1401
c. IBM 1402
d. IBM1402
9. WAN stands for
a. Wap Area Network
b. Wide Area Network
c. Wide Array Net
10. MICR stands for
a. Magnetic Ink Character Reader
b. Magnetic Ink Code Reader
c. Magnetic Ink Cases Reader
d. None
1. UNIVAC is
Correct Answer: a. Universal Automatic Computer
Explanation: There are no computers with the name as in other options.
UNIVAC was the first general purpose electronic digital computer designed for
commercial use, produced by Universal Accounting Company of John Mauchly
and J.P.Eckert in 1951.
2. CD-ROM stands for
Correct Answer: d. Compact Disk Read Only Memory
Explanation: There are no objects with the name as in other options. CD-ROM is
a non-volatile optical data storage medium using the same physical format as
audio compact disk, readable by a computer with a CD-ROM drive. The standard
12 cm diameter CD-ROM store about 660 megabytes.
3. ALU is
Correct Answer: a. Arithmetic Logic Unit
Explanation: ALU is a unit in Central Processing Unit in a computer system that
is responsible for arithmetic calculations and logical operations. Apart from ALU,
the CPU contains MU (Memory Unit) and CU (Control Unit).
4. VGA is
Correct Answer: a. Video Graphics Array
Explanation: VGA is a type of Graphics Adapter. Graphic Adapter is an electronic
board that controls the display of a monitor. This device helps the motherboard
to work with the monitor and in VGA and SVGA the last letter ‘A’ stands
for ‘Array’ whereas in MDA, CGA, MCGA the last letter ‘A’ stands for ‘Adapter’.
5. IBM 1401 is
Explanation: IBM 1401 is a Second Generation Computer and is the first computer
to enter Nepal in 2028 BS for census. Government of Nepal had brought this
computer on rent and later purchased for data processing in Bureau of Statistics.
After this computer, another ICL 2950/10, a British computer, was purchased by
the fund of UNDP and UNFPA for the census of 2038 BS is second computer in
Nepal.
6. MSI stands for
Correct Answer: a. Medium Scale Integrated Circuits
Explanation: After the invention of IC chips the development of computers
plunged into next phase. Small Scale Integration and Medium Scale Integration
(SSI and MSI) were used in third generation of computers and Large Scale
Integration and Very Large Scale Integration (LSI and VLSI) are being used in
fourth generation of computers. People are now expecting ULSI (Ultra Large
Scale Integration) Circuits to be used for fifth generation computers.
7. The capacity of 3.5 inch floppy disk is
Correct Answer: d. 1.44 MB
Explanation: Microfloppy disks (3.5 inch) if it is high density (MF2HD) can
store 1.44 MB and if it is low density (MF2DD), it can store 720 KB. Mini Floppy
disks (5.25 inch) if it is high density (MD2HD) can store 1.2 MB and low density
(MD2DD) stores 360 KB of data.
8. The first computer introduced in Nepal was
Correct Answer: b. IBM 1401
Explanation: IBM 1401, a second generation computer was brought in Nepal
by the Government of Nepal paying One Lakh and twenty five thousands per
month to use in the census in 2028 B.S. Before this computer, Nepal was using a
calculating device called Facit for statistical tasks.
9. WAN stands for
Correct Answer: b. Wide Area Network
Explanation: There are three different classes of computer network namely, Local
Area Network (LAN) that covers a small geographical area such as a room, a
building or a compound; Metropolitan Area Network (MAN) that has a citywide
coverage; and Wide Area Network (WAN) that covers the whole globe or beyond
the globe.
10. MICR stands for
Correct Answer: a. Magnetic Ink Character Reader
Explanation: MICR (Magnetic Ink Character Reader) is kind of scanner that can
scan and identify the writing of magnetic ink. This device is used in banks to
verify signatures in Checks.
________________________________________________
Set - 2
1. EBCDIC stands for
a. Extended Binary Coded Decimal Interchange Code b. Extended Bit Code Decimal Interchange Code c. Extended Bit Case Decimal Interchange Code d. Extended Binary Case Decimal Interchange Code 2. BCD is
a. Binary Coded Decimal b. Bit Coded Decimal c. Binary Coded Digit d. Bit Coded Digit
3. ASCII stands for
a. American Stable Code for International Interchange b. American Standard Case for Institutional Interchange c. American Standard Code for Information Interchange d. American Standard Code for Interchange Information
4. Which of the following is first generation of computer a. EDSAC
b. IBM-1401 c. CDC-1604 d. ICL-2900
5. Chief component of first generation computer was a. Transistors
c. Integrated Circuits d. None of above 6. FORTRAN is a. File Translation b. Format Translation c. Formula Translation d. Floppy Translation
7. EEPROM stand for
a. Electrically Erasable Programmable Read Only Memory b. Easily Erasable Programmable Read Only Memory c. Electronic Erasable Programmable Read Only Memory d. None of the above
8. Second Generation computers were developed during a. 1949 to 1955
b. 1956 to 1965 c. 1965 to 1970 d. 1970 to 1990
Correct Answer: 1956 to 1965
Explanation: Second generation computers used transistors as their main electronic component. Transistor was invented by Bell Lab Scientists John Burdeen, Walter Brattain and William Shockley in 1947 and won the Nobel Prize in 1956 but it was not used in computers till 1956. The second generation continued until the implementation of IC chips invented by Jack Kilby in Texas Instruments in 1958.
9. The computer size was very large in a. First Generation
b. Second Generation c. Third Generation d. Fourth Generation
10. Microprocessors as switching devices are for which generation computers a. First Generation
c. Third Generation d. Fourth Generation
1. EBCDIC stands for
Correct Answer: a. Extended Binary Coded Decimal Interchange Code
Explanation: EBCDIC is an 8-bit binary code for larger IBMs primarily mainframes
in which each byte represent one alphanumeric character or two decimal digits. 256
characters can be coded using EBCDIC.
2. BCD is
Correct Answer: a. Binary Coded Decimal
Explanation: BCD is a binary coded notation in which each of the decimal digits is
expressed as a 8-bit binary numeral. For example in binary coded decimal notation 12 is
0001 0010 as opposed to 1100 in pure binary.
3. ASCII stands for
Correct Answer: c. American Standard Code for Information Interchange
Explanation: ASCII is a code which converts characters – letters, digits, punctuations
and control characters such as Alt, Tab etc – into numeral form. ASCII code is used to
represent data internally in micro-computers. ASCII codes are 7 bits and can represent
0 to 127 and extended ASCII are 8 bits that represents 0 to 255.
4. Which of the following is first generation of computer
Correct Answer: a. EDSAC
Explanation: IBM-1401, CDC-1604 is second generation computer. ICL-2900 is a fourth
generation computer. EDSAC is important in the development of computer since it was
the first computer to use John von. Neumann’s Stored Program Concept. It used 3000
vacuum tubes and computers with vacuum tubes are of first generation computers.
5. Chief component of first generation computer was
Correct Answer: b. Vacuum Tubes and Valves
Explanation: Transistors were used for second generation computers and integrated
circuits in third generation. First generation computers used vacuum tubes and valves
as their main electronic component. Vacuum Tubes were invented by Lee DeForest in
1908.
6. FORTRAN is
Correct Answer: c. Formula Translation
Explanation: FORTRAN (Formula Translation) is one of the earlier High Level
programming languages used to write scientific applications. It was developed by IBM
in 1956.
7. EEPROM stand for
Correct Answer: a. Electrically Erasable Programmable Read Only Memory
Explanation: There are three types of ROM namely, PROM, EPROM and EEPROM.
PROM can’t be reprogrammed, EPROM can be erased by exposing it in high intensity
ultraviolet light and EEPROM can be erased and reprogrammed electrically. It is not
needed to be removed from the computer to be modified.
8. Second Generation computers were developed during
Correct Answer: 1956 to 1965
Explanation: Second generation computers used transistors as their main electronic
component. Transistor was invented by Bell Lab Scientists John Burdeen, Walter
Brattain and William Shockley in 1947 and won the Nobel Prize in 1956 but it was not
used in computers till 1956. The second generation continued until the implementation
of IC chips invented by Jack Kilby in Texas Instruments in 1958.
9. The computer size was very large in
Correct Answer: a. First Generation
Explanation: It is obvious that computers developed with more power, reliability, speed
and smaller sizes due to the enhancement of technology. First generation computers
used 1000s of vacuum tubes that required lot of space made them gigantic in size. Single
transistor could replace 1000 vacuum tubes and a single IC chip replaced 1000s of
transistors made computers smaller and more speedy.
10. Microprocessors as switching devices are for which generation computers
