Lecture 8 - Effect of source inductance on rectifier operation

Lecture 8 - Effect of source inductance on rectifier operation

Ideal VS real rectifier with source inductance

The output DC voltages of the rectifier circuits discussed so far have been found by assuming that diode currents transfer (commutate) from one diode to another instantaneously. However this can not happen when the AC source has some inductance Ls. (Change of current through any inductance must take some time!). This source inductance is associated with the leakage inductance of the supply transformer and the inductance of the AC supply network to the input transformer. The commutation process (or the overlap process) forces more than one diode or a pair of diodes (in a bridge rectifier) to conduct simultaneously, resulting in a drop voltage from the output terminals which is proportional to the load current.

The output dc voltage Vd of a rectifier falls with load current Id, by an amount which is much larger than additional voltage drop across the conducting diodes when the current through the diodes increases. The AC source inductance, which consists of the AC line and the input transformer leakage inductances, is mostly responsible for the additional voltage drop. Consider the half-wave diode rectifier shown below.

∼

D

L

s

I

d

Load

D

f

v

s

= V

max

sin

ω

t

i

s

I

Df

v

s

v

_i

Figure 8.1. Half-wave diode rectifier with source inductance.

Let us assume that the load current Id is smooth and ripple-free (i.e., of constant, due to the highly inductive load). Assume also that for

ω

t > 0, the load current flows through the rectifier diode and that for

ω

t >

π

, it commutates to the free-wheeling diode Df. This transfer of the load current between the rectifier and the freewheeling diodes can not however be instantaneous, because of the source inductance Ls. This transfer takes place over a small commutation or overlap angle

µ

, during which time, the current gradually falls to zero in one circuit and it rises to Id in the other circuit at the same rate. Clearly, the two diodes simultaneously conduct during the commutation process (

µ

).

Figure 8.2 Waveforms in the rectifier circuit of figure 8.1

v

s

i

D iDf vo vi Id µ

µ

µ

µ

µ

Because of the prolonged conduction of Df, the load voltage is clamped to zero for 0 <

ω

t <

µ

, resulting in some loss of positive voltage in the vo waveform. Consequently Vd is reduced, the extent of which depends on

µ

, which in turn depends on Ls and Id.

During the process of overlap, all of the ac source voltage drops across Ls, so that for 0 <

ω

t <

µ

, max s di v V sin t L dt

ω

= = 8.1 Integrating, Id max s s d 0 0 V sin td( t ) L di L I µ

ω

ω

=

ω

=

ω

∫

∫

8.2

or, V_max( 1 cos−

µ

)=

ω

L I_{s d} 8.3

and s _d max L cos = 1 - I V

ω

µ

8.4

The overlap, or commutation angle,

µ

can the found from (4) given Idand Ls.

d max max 0 0 1 1 V V sin( t )d( t ) V sin td( t ) 2 2 π µ

ω

ω

ω

ω

π

π

=

∫

−

∫

= max _{s d} max s _d max V 1 V L L I 1 I 2 2V

ω

ω

π

π

π

⎡ ⎤ − = _⎢ − _⎥ ⎣ ⎦ 8.5 max V π Id Vd

Figure 8.3 Voltage regulation characteristic of the rectifier of figure 8.1 due to source inductance

Overlap in a bridge rectifier due to source inductance

During the positive half cycle, diodes D1 and D4 carries the load current Id. During the negative half cycle, diodes D3 and D2 carry the load current. During overlap all four diodes carry the load current. The output voltage during overlap is zero and all of the supply voltage applies across the source inductor Ls.

Figure 8.4. A diode bridge rectifier with source inductance

Figure 8.6 Waveforms in the rectifier of figure 8.4 Vd vo Id D4 D2 D3 D1 N:1 ip Ls Load is Vmaxsinωt vi

µ

µ

µ

µ

µ

µ vo Id - Id

v

i vs is

Thus, during commutation overlap, max s di V sin t L dt

ω

= 8.6 Id max s s d 0 _Id V sin td( t ) L di 2 L I µ

ω

ω

ω

ω

− = =

∫

∫

s d max 2 L cos 1 I V

ω

µ

∴ = − 8.7

The dc output voltage of the converter is given by

d max max max

0 0

1 1 1

V V sin td( t ) V sin td( t ) V sin t( d t )

π π µ µ

ω

ω

ω

ω

ω

ω

π

π

π

=

∫

=

∫

−

∫

max s d max 2V L 1 I V

ω

π

⎛ ⎞ = _⎜ − _⎟ ⎝ ⎠ 8.8 max s d max 2V L 1 I V

ω

π

⎛ ⎞ = _⎜ − _⎟ ⎝ ⎠ 8.9 max 2V π Id Vd

Figure 8.5 Regulation characteristic of a 1-phase bridge rectifier due to source inductance

Effect of overlap on three-phase center-tap rectifier

In the three-phase, center-tap rectifier of figure below, the load current starts to commutate to diode D2 from

ω

t = 0+ when vb starts to become more positive than va. During overlap, both diodes D1 and D2 carry the load current which is assumed to remain constant during the process.

Figure 8.7 Three-phase center-tap rectifier with source inductance

Figure 8.7

Figure 8.8 Waveforms in the rectifier of figure 8.7

Ls va n vb n vc n Ls Ls n L o a d Id D 3 D 2 D 1 Vd vo vcn van v_bn vo vabi µ ia ib ic µ

During overlap, a an s o di v L v dt = + 8.10 b bn s o

di

v

L

v

dt

=

+

8.11

Assuming that Id remains constant during the overlap time, and noting that

a b d

i + =i I _{, so that}

a b

di di

dt = − dt . 8.12

Adding the voltage equations and canceling the equal but opposite terms, an bn o v v v 2 +

= _{, during the overlap process. 8.13}

Thus, during the commutation overlap, the converter output voltage vo is the average of the voltages of the lines undergoing commutation. Once the load current is fully commutated, vo jumps up to the potential vb. Form the ideal output voltage waveform, the area bounded by vb and (va +vb)/2 is lost due to overlap of two conducting diodes. In the following analysis, the line-neutral voltages are:

an max

v =V sin t

ω

; v_bn =V_max sin

(

ω

t−2 / 3

π

)

; v_cn =V_maxsin

(

ω

t−4 / 3

π

)

The part of the positive voltage pulse lost due to overlap starting from angle

ω

t =

π

/6 is given by bn an bn an bn s v v v v di v L 2 2 dt + − − = = _8.14

The area (shaded) inside the voltage pulse lost due to overlap is given by

Id 6 bn an s s d 0 6 v v d( t ) L di L I 2 π _µ π ω ω ω + _{⎛ − ⎞} = = ⎜ ⎟ ⎝ ⎠

∫

∫

8.15

Note that (vb - va) is the line-line voltage vba. The integral on the right hand side by shifting the origin by π/6 to the left. Thus

max s d 0 3V sin td( t ) L I 2 µ

ω

ω

=

ω

∫

8.16 ∴ s d max l l 2 L 1 cos I V

ω

µ

− − = , so that 8.17 s d max l l 2 L cos 1 I V

ω

µ

−

= − where Vmax l-l =

√

3 Vmax 8.18

The dc output voltage is

max l l max s s d d d max l l 3V 3 3 V 3 L L V I 1 I 2 2 2 V

ω

ω

π

π

π

− − ⎛ ⎞ = − = ⎜_⎜ − ⎟_⎟ ⎝ ⎠ 8.19

Figure 8.9 Regulation characteristic of the rectifier in figure 8.7 Id Vd max l l 3V 2

π

−

Effect of source inductance on three-phase diode bridge rectifier Load R L Vd vo = vL+ − vL− D1 D3 D5 D4 D6 D2 iL ia ib ic van vbn vcn vL+ vL− Ls Ls Ls _v abi

Figure 8.10 Three-phase diode bridge rectifier with source inductance As for the three-phase CT rectifier, the voltage equations are

a a s L di v L v dt + = + 8.20 b b s L di v L v dt + = +

8.21

when D1 and D3 are in overlap due to the source inductance Ls and where all voltages are with respect to the fictitious neutral point. vL+ is the potential of the positive voltage bus (cathodes of the upper diodes) of the rectifier with respect to the neutral point.

As before, during each overlap, the positive and negative dc buses have voltages which are average values of the commutating line-line potentials.

During the commutation overlap of diodes D1 and D3, the positive rail voltage is (vb + va)/2, and the positive voltage lost from VL+ as a result of the overlap is

b a b a b L b s v v v v di v v v L 2 2 dt + + − − = − = = 8.21

Integrating for the duration of the overlap

Id 6 b a s s d 0 6 v v d( t ) L di L I 2 π µ π

ω

ω

ω

+ _{⎛ − ⎞} = = ⎜ ⎟ ⎝ ⎠

∫

∫

8.22

Figure 8.11 Waveforms in the rectifier of figure 8.10

ia

ib

ic

Commutation notches in vabi vABi

vo

vc vb

Note again that (vb - va) is the line-line voltage. The integral in the right hand side by shifting the origin by π/6 to the left. Thus

max s d 0 3V sin td( t ) L I 2 µ

ω

ω

=

ω

∫

8.23 ∴ s d max l l 2 L 1 cos I V

ω

µ

− − = , so that 8.24 s d max l l 2 L cos 1 I V

ω

µ

−

= − where Vmax l-l=

√

3 Vmax 8.25

The dc output voltage Vdis given by

( )

max l l max l l max l l _s

d d 0 3V ₁ V 3V _{3 L} V sin td t I / 3 2 µ

ω

ω

ω

π

π

π

π

− − − = −

∫

= − 8.26 max l l _s d d max l l 3V _L V 1 I V

ω

π

− − ⎛ ⎞ = ⎜_⎜ − ⎟_⎟ ⎝ ⎠ 8.27

Figure 8.12. Voltage regulation characteristic of the three-phase diode bridge rectifier due to source inductance

Id Vd

max l l

3V

π

−